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@@ -25,30 +25,70 @@
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#include <config.h>
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#include <common.h>
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#include <phy.h>
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+#include <bitfield.h>
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#define REG_PHY_SPEC_STATUS 0x11
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#define REG_DEBUG_ADDR_OFFSET 0x1e
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#define REG_DEBUG_DATA 0x1f
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#define EXTREG_SLEEP_CONTROL 0x27
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-#define YT8512_DUPLEX 0x2000
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-#define YT8521_SPEED_MODE 0xc000
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-#define YT8521_DUPLEX 0x2000
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-#define YT8521_SPEED_MODE_BIT 14
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-#define YT8521_DUPLEX_BIT 13
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-#define YT8521_LINK_STATUS_BIT 10
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-
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-#define YT8521_EXTREG_SMI_SDS_PHY 0xa000
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-#define YT8521_EXTREG_CHIP_CONFIG 0xa001
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-#define YT8521_RXC_DLY_EN_BIT 8
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-#define YT8521_EXTREG_RGMII_CONFIG1 0xa003
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-#define YT8521_RX_DELAY_SEL_MASK 0x3C00UL
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-#define YT8521_TX_DELAY_SEL_FE_MASK 0xF0UL
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-#define YT8521_TX_DELAY_SEL_MASK 0xFUL
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+#define YTPHY_EXTREG_CHIP_CONFIG 0xa001
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+#define YTPHY_EXTREG_RGMII_CONFIG1 0xa003
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+#define YTPHY_PAD_DRIVES_STRENGTH_CFG 0xa010
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+#define YTPHY_DUPLEX 0x2000
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+#define YTPHY_DUPLEX_BIT 13
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+#define YTPHY_SPEED_MODE 0xc000
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+#define YTPHY_SPEED_MODE_BIT 14
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+#define YTPHY_RGMII_SW_DR_MASK GENMASK(5, 4)
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+#define YT8521_EXT_CLK_GATE 0xc
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+#define YT8521_EN_SLEEP_SW_BIT 15
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#define SPEED_UNKNOWN -1
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+#define PHY_ID_YT8531 0x4f51e91b
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+#define MOTORCOMM_PHY_ID_MASK 0x00000fff
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+
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+#define YT8512_EXTREG_LED0 0x40c0
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+#define YT8512_EXTREG_LED1 0x40c3
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+
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+#define YT8512_EXTREG_SLEEP_CONTROL1 0x2027
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+
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+#define YT8512_LED0_ACT_BLK_IND 0x1000
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+#define YT8512_LED0_DIS_LED_AN_TRY 0x0001
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+#define YT8512_LED0_BT_BLK_EN 0x0002
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+#define YT8512_LED0_HT_BLK_EN 0x0004
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+#define YT8512_LED0_COL_BLK_EN 0x0008
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+#define YT8512_LED0_BT_ON_EN 0x0010
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+#define YT8512_LED1_BT_ON_EN 0x0010
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+#define YT8512_LED1_TXACT_BLK_EN 0x0100
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+#define YT8512_LED1_RXACT_BLK_EN 0x0200
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+
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+#define YT8512_EN_SLEEP_SW_BIT 15
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+
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+struct ytphy_reg_field {
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+ const char *name;
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+ const u8 size; /* Size of the bitfield, in bits */
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+ const u8 off; /* Offset from bit 0 */
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+ const u8 dflt; /* Default value */
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+};
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+
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+static const struct ytphy_reg_field ytphy_rxtxd_grp[] = {
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+ { "rx_delay_sel", 4, 10, 0x0 },
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+ { "tx_delay_sel_fe", 4, 4, 0xf },
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+ { "tx_delay_sel", 4, 0, 0x1 }
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+};
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+
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+static const struct ytphy_reg_field ytphy_txinver_grp[] = {
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+ { "tx_inverted_1000", 1, 14, 0x0 },
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+ { "tx_inverted_100", 1, 14, 0x0 },
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+ { "tx_inverted_10", 1, 14, 0x0 }
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+};
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+
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+static const struct ytphy_reg_field ytphy_rxden_grp[] = {
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+ { "rxc_dly_en", 1, 8, 0x1 }
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+};
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+
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static int ytphy_read_ext(struct phy_device *phydev, u32 regnum)
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{
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int ret;
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@@ -71,216 +111,261 @@ static int ytphy_write_ext(struct phy_device *phydev, u32 regnum, u16 val)
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return phy_write(phydev, MDIO_DEVAD_NONE, REG_DEBUG_DATA, val);
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}
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-static int yt8511_config(struct phy_device *phydev)
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+static int ytphy_parse_status(struct phy_device *phydev)
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{
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- u16 val = 0;
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- int err = 0;
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+ int val;
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+ int speed, speed_mode, duplex;
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- genphy_config_aneg(phydev);
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+ val = phy_read(phydev, MDIO_DEVAD_NONE, REG_PHY_SPEC_STATUS);
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+ if (val < 0)
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+ return val;
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- /* disable sleep mode */
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- err = phy_write(phydev, MDIO_DEVAD_NONE, REG_DEBUG_ADDR_OFFSET, EXTREG_SLEEP_CONTROL);
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- if (err < 0) {
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- printf("%s: write EXTREG_SLEEP_CONTROL error!\n", __func__);
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- return err;
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+ duplex = (val & YTPHY_DUPLEX) >> YTPHY_DUPLEX_BIT;
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+ speed_mode = (val & YTPHY_SPEED_MODE) >> YTPHY_SPEED_MODE_BIT;
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+ switch (speed_mode) {
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+ case 2:
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+ speed = SPEED_1000;
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+ break;
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+ case 1:
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+ speed = SPEED_100;
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+ break;
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+ default:
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+ speed = SPEED_10;
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+ break;
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}
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- val = phy_read(phydev, MDIO_DEVAD_NONE, REG_DEBUG_DATA);
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- val &= ~(1 << 15);
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- err = phy_write(phydev, MDIO_DEVAD_NONE, REG_DEBUG_DATA, val);
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- if (err < 0) {
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- printf("%s: write REG_DEBUG_DATA error!\n", __func__);
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- return err;
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- }
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+ phydev->speed = speed;
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+ phydev->duplex = duplex;
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- /* config PLL clock */
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- err = phy_write(phydev, MDIO_DEVAD_NONE, REG_DEBUG_ADDR_OFFSET, 0xc);
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- if (err < 0) {
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- printf("%s: write 0xc error!\n", __func__);
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- return err;
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+ return 0;
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+}
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+
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+static int ytphy_of_inverted(struct phy_device *phydev)
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+{
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+ ofnode node;
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+ u32 val;
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+ u32 inver_10;
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+ u32 inver_100;
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+ u32 inver_1000;
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+
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+ node = phydev->node;
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+ if (!ofnode_valid(node)) {
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+ /* Look for a PHY node under the Ethernet node */
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+ node = dev_read_subnode(phydev->dev, "ethernet-phy");
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}
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- val = phy_read(phydev, MDIO_DEVAD_NONE, REG_DEBUG_DATA);
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- /* ext reg 0xc.b[2:1]
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- * 00-----25M from pll;
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- * 01---- 25M from xtl;(default)
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- * 10-----62.5M from pll;
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- * 11----125M from pll(here set to this value)
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- */
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-
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- val &= ~(3 << 1); /*00-----25M from pll*/
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- val |= (1 << 1); /*01-----25M from xtl; (default)*/
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- err = phy_write(phydev, MDIO_DEVAD_NONE, REG_DEBUG_DATA, val);
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- if (err < 0) {
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- printf("%s: set PLL error!\n", __func__);
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- return err;
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+ if (!ofnode_valid(node)) /* No node found*/
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+ return 0;
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+
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+ val = ytphy_read_ext(phydev, YTPHY_EXTREG_RGMII_CONFIG1);
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+ inver_10 = ofnode_read_u32_default(node, "tx_inverted_10", 0);
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+ inver_100 = ofnode_read_u32_default(node, "tx_inverted_100", 0);
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+ inver_1000 = ofnode_read_u32_default(node, "tx_inverted_1000", 0);
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+
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+ switch (phydev->speed) {
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+ case SPEED_1000:
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+ val = bitfield_replace(val, ytphy_txinver_grp[0].off,
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+ ytphy_txinver_grp[0].size, inver_1000);
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+ break;
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+ case SPEED_100:
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+ val = bitfield_replace(val, ytphy_txinver_grp[1].off,
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+ ytphy_txinver_grp[1].size, inver_100);
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+ break;
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+ case SPEED_10:
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+ val = bitfield_replace(val, ytphy_txinver_grp[2].off,
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+ ytphy_txinver_grp[2].size, inver_10);
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+ break;
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+ default:
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+ printf("UNKOWN SPEED\n");
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+ break;
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}
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- return 0;
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+ return ytphy_write_ext(phydev, YTPHY_EXTREG_RGMII_CONFIG1, val);
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}
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-static int yt8521_config(struct phy_device *phydev)
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+static int ytphy_startup(struct phy_device *phydev)
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{
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- int ret, val;
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- int regnum;
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+ int retval;
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- ret = 0;
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- ytphy_write_ext(phydev, YT8521_EXTREG_SMI_SDS_PHY, 0);
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+ retval = genphy_update_link(phydev);
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+ if (retval)
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+ return retval;
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+ ytphy_parse_status(phydev);
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- genphy_config_aneg(phydev);
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+ ytphy_of_inverted(phydev);
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- /* disable auto sleep */
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- val = ytphy_read_ext(phydev, EXTREG_SLEEP_CONTROL);
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- if (val < 0) {
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- regnum = EXTREG_SLEEP_CONTROL;
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- goto err;
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- }
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+ return 0;
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+}
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- val &= ~(1 << 15);
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- ret = ytphy_write_ext(phydev, EXTREG_SLEEP_CONTROL, val);
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- if (ret < 0) {
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- regnum = EXTREG_SLEEP_CONTROL;
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- goto err;
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+static int ytphy_of_config(struct phy_device *phydev)
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+{
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+ ofnode node;
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+ u32 val;
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+ u32 cfg;
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+ int i;
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+
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+ node = phydev->node;
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+ if (!ofnode_valid(node)) {
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+ /* Look for a PHY node under the Ethernet node */
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+ node = dev_read_subnode(phydev->dev, "ethernet-phy");
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}
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- /* enable tx delay 450ps per step */
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- val = ytphy_read_ext(phydev, YT8521_EXTREG_RGMII_CONFIG1);
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- if (val < 0) {
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- regnum = YT8521_EXTREG_RGMII_CONFIG1;
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- goto err;
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- }
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+ if (!ofnode_valid(node)) /* No node found*/
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+ return 0;
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- val &= ~(YT8521_RX_DELAY_SEL_MASK
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- |YT8521_TX_DELAY_SEL_FE_MASK
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- |YT8521_TX_DELAY_SEL_MASK);
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- val |= 0x5B;
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- ret = ytphy_write_ext(phydev, YT8521_EXTREG_RGMII_CONFIG1, val);
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- if (ret < 0) {
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- regnum = YT8521_EXTREG_RGMII_CONFIG1;
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- goto err;
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- }
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+ /*read rxc_dly_en config*/
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+ cfg = ofnode_read_u32_default(node, ytphy_rxden_grp[0].name, ~0);
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+ if (cfg != -1) {
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- /* disable rx delay */
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- val = ytphy_read_ext(phydev, YT8521_EXTREG_CHIP_CONFIG);
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- if (val < 0) {
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- regnum = YT8521_EXTREG_CHIP_CONFIG;
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- goto err;
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- }
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- val &= ~(1 << 8);
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- val |=BIT(YT8521_RXC_DLY_EN_BIT);
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- ret = ytphy_write_ext(phydev, YT8521_EXTREG_CHIP_CONFIG, val);
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- if (ret < 0) {
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- regnum = YT8521_EXTREG_CHIP_CONFIG;
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- goto err;
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- }
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+ val = ytphy_read_ext(phydev, YTPHY_EXTREG_CHIP_CONFIG);
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- /* enable RXC clock when no wire plug */
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- ret = ytphy_write_ext(phydev, YT8521_EXTREG_SMI_SDS_PHY, 0);
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- if (ret < 0) {
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- regnum = YT8521_EXTREG_SMI_SDS_PHY;
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- goto err;
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- }
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+ /*check the cfg overflow or not*/
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+ cfg = (cfg > ((1 << ytphy_rxden_grp[0].size) - 1)) ?
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+ ((1 << ytphy_rxden_grp[0].size) - 1) : cfg;
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- val = ytphy_read_ext(phydev, 0xc);
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- if (val < 0) {
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- regnum = 0xc;
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- goto err;
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+ val = bitfield_replace(val, ytphy_rxden_grp[0].off,
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+ ytphy_rxden_grp[0].size, cfg);
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+ ytphy_write_ext(phydev, YTPHY_EXTREG_CHIP_CONFIG, val);
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}
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- val &= ~(1 << 12);
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- ret = ytphy_write_ext(phydev, 0xc, val);
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- if (ret < 0) {
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- regnum = 0xc;
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- goto err;
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+ /* set drive strenght of rxd/rx_ctl rgmii pad */
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+ val = ytphy_read_ext(phydev, YTPHY_PAD_DRIVES_STRENGTH_CFG);
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+ val |= YTPHY_RGMII_SW_DR_MASK;
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+ ytphy_write_ext(phydev, YTPHY_PAD_DRIVES_STRENGTH_CFG, val);
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+
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+ val = ytphy_read_ext(phydev, YTPHY_EXTREG_RGMII_CONFIG1);
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+ for (i = 0; i < ARRAY_SIZE(ytphy_rxtxd_grp); i++) {
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+
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+ cfg = ofnode_read_u32_default(node,
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+ ytphy_rxtxd_grp[i].name, ~0);
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+ cfg = (cfg != -1) ? cfg : ytphy_rxtxd_grp[i].dflt;
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+
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+ /*check the cfg overflow or not*/
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+ cfg = (cfg > ((1 << ytphy_rxtxd_grp[i].size) - 1)) ?
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+ ((1 << ytphy_rxtxd_grp[i].size) - 1) : cfg;
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+
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+ val = bitfield_replace(val, ytphy_rxtxd_grp[i].off,
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+ ytphy_rxtxd_grp[i].size, cfg);
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}
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- return 0;
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-err:
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- printf("%s operate reg %d err.\n", __func__, regnum);
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- return ret;
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+ return ytphy_write_ext(phydev, YTPHY_EXTREG_RGMII_CONFIG1, val);
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}
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-static int yt8521_adjust_status(struct phy_device *phydev, int val, int is_utp)
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+static int yt8512_led_init(struct phy_device *phydev)
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{
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- int speed_mode, duplex;
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- int speed = SPEED_UNKNOWN;
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+ int ret;
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+ int val;
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+ int mask;
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- duplex = (val & YT8512_DUPLEX) >> YT8521_DUPLEX_BIT;
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- speed_mode = (val & YT8521_SPEED_MODE) >> YT8521_SPEED_MODE_BIT;
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- switch (speed_mode) {
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- case 0:
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- if (is_utp)
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- speed = SPEED_10;
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- break;
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- case 1:
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- speed = SPEED_100;
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- break;
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- case 2:
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- speed = SPEED_1000;
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- break;
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- case 3:
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- break;
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- default:
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- speed = SPEED_UNKNOWN;
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- break;
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- }
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+ val = ytphy_read_ext(phydev, YT8512_EXTREG_LED0);
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+ if (val < 0)
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+ return val;
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- phydev->speed = speed;
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- phydev->duplex = duplex;
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+ val |= YT8512_LED0_ACT_BLK_IND;
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- return 0;
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+ mask = YT8512_LED0_DIS_LED_AN_TRY | YT8512_LED0_BT_BLK_EN |
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+ YT8512_LED0_HT_BLK_EN | YT8512_LED0_COL_BLK_EN |
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+ YT8512_LED0_BT_ON_EN;
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+ val &= ~mask;
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+
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+ ret = ytphy_write_ext(phydev, YT8512_EXTREG_LED0, val);
|
|
|
+ if (ret < 0)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ val = ytphy_read_ext(phydev, YT8512_EXTREG_LED1);
|
|
|
+ if (val < 0)
|
|
|
+ return val;
|
|
|
+
|
|
|
+ val |= YT8512_LED1_BT_ON_EN;
|
|
|
+
|
|
|
+ mask = YT8512_LED1_TXACT_BLK_EN | YT8512_LED1_RXACT_BLK_EN;
|
|
|
+ val &= ~mask;
|
|
|
+
|
|
|
+ ret = ytphy_write_ext(phydev, YT8512_LED1_BT_ON_EN, val);
|
|
|
+
|
|
|
+ return ret;
|
|
|
}
|
|
|
|
|
|
-static int yt8521_parse_status(struct phy_device *phydev)
|
|
|
+static int yt8512_config(struct phy_device *phydev)
|
|
|
{
|
|
|
- int ret, val, link, link_utp;
|
|
|
+ int ret;
|
|
|
+ int val;
|
|
|
|
|
|
- /* reading UTP */
|
|
|
- ret = ytphy_write_ext(phydev, 0xa000, 0);
|
|
|
+ ret = 0;
|
|
|
+ genphy_config_aneg(phydev);
|
|
|
+
|
|
|
+ ret = yt8512_led_init(phydev);
|
|
|
+
|
|
|
+ /* disable auto sleep */
|
|
|
+ val = ytphy_read_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1);
|
|
|
+ if (val < 0)
|
|
|
+ return val;
|
|
|
+
|
|
|
+ val &= (~BIT(YT8512_EN_SLEEP_SW_BIT));
|
|
|
+
|
|
|
+ ret = ytphy_write_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1, val);
|
|
|
if (ret < 0)
|
|
|
return ret;
|
|
|
|
|
|
- val = phy_read(phydev, MDIO_DEVAD_NONE, REG_PHY_SPEC_STATUS);
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static int yt8521_config(struct phy_device *phydev)
|
|
|
+{
|
|
|
+ int ret, val;
|
|
|
+
|
|
|
+ ret = 0;
|
|
|
+ genphy_config_aneg(phydev);
|
|
|
+
|
|
|
+ /* disable auto sleep */
|
|
|
+ val = ytphy_read_ext(phydev, EXTREG_SLEEP_CONTROL);
|
|
|
if (val < 0)
|
|
|
return val;
|
|
|
|
|
|
- link = val & (BIT(YT8521_LINK_STATUS_BIT));
|
|
|
- if (link) {
|
|
|
- link_utp = 1;
|
|
|
- yt8521_adjust_status(phydev, val, 1);
|
|
|
- } else {
|
|
|
- link_utp = 0;
|
|
|
- }
|
|
|
+ val &= ~(1 << YT8521_EN_SLEEP_SW_BIT);
|
|
|
+ ret = ytphy_write_ext(phydev, EXTREG_SLEEP_CONTROL, val);
|
|
|
+ if (ret < 0)
|
|
|
+ return ret;
|
|
|
|
|
|
- if (link_utp) {
|
|
|
- phydev->link = 1;
|
|
|
- ytphy_write_ext(phydev, 0xa000, 0);
|
|
|
- } else {
|
|
|
- phydev->link = 0;
|
|
|
- }
|
|
|
+ /*set delay config*/
|
|
|
+ ret = ytphy_of_config(phydev);
|
|
|
+ if (ret < 0)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ val = ytphy_read_ext(phydev, YT8521_EXT_CLK_GATE);
|
|
|
+ if (val < 0)
|
|
|
+ return val;
|
|
|
+
|
|
|
+ val &= ~(1 << 12);
|
|
|
+ ret = ytphy_write_ext(phydev, YT8521_EXT_CLK_GATE, val);
|
|
|
+ if (ret < 0)
|
|
|
+ return ret;
|
|
|
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
|
-static int yt8521_startup(struct phy_device *phydev)
|
|
|
+static int yt8531_config(struct phy_device *phydev)
|
|
|
{
|
|
|
- int retval;
|
|
|
+ int ret;
|
|
|
|
|
|
- retval = genphy_update_link(phydev);
|
|
|
- if (retval)
|
|
|
- return retval;
|
|
|
+ ret = 0;
|
|
|
+ genphy_config_aneg(phydev);
|
|
|
|
|
|
- return yt8521_parse_status(phydev);
|
|
|
+ /*set delay config*/
|
|
|
+ ret = ytphy_of_config(phydev);
|
|
|
+ if (ret < 0)
|
|
|
+ return ret;
|
|
|
+ return 0;
|
|
|
}
|
|
|
|
|
|
-static struct phy_driver YT8511_driver = {
|
|
|
- .name = "YuTai YT8511",
|
|
|
- .uid = 0x0000010a,
|
|
|
- .mask = 0x00000fff,
|
|
|
- .features = PHY_GBIT_FEATURES,
|
|
|
- .config = &yt8511_config,
|
|
|
- .startup = &genphy_startup,
|
|
|
- .shutdown = &genphy_shutdown,
|
|
|
+static struct phy_driver YT8512_driver = {
|
|
|
+ .name = "YuTai YT8512",
|
|
|
+ .uid = 0x00000118,
|
|
|
+ .mask = 0x00000fff,
|
|
|
+ .features = PHY_GBIT_FEATURES,
|
|
|
+ .config = &yt8512_config,
|
|
|
+ .startup = &ytphy_startup,
|
|
|
+ .shutdown = &genphy_shutdown,
|
|
|
};
|
|
|
|
|
|
static struct phy_driver YT8521_driver = {
|
|
@@ -289,14 +374,25 @@ static struct phy_driver YT8521_driver = {
|
|
|
.mask = 0x00000fff,
|
|
|
.features = PHY_GBIT_FEATURES,
|
|
|
.config = &yt8521_config,
|
|
|
- .startup = &yt8521_startup,
|
|
|
+ .startup = &ytphy_startup,
|
|
|
.shutdown = &genphy_shutdown,
|
|
|
};
|
|
|
|
|
|
+static struct phy_driver YT8531_driver = {
|
|
|
+ .name = "YT8531 Gigabit Ethernet",
|
|
|
+ .uid = PHY_ID_YT8531,
|
|
|
+ .mask = MOTORCOMM_PHY_ID_MASK,
|
|
|
+ .features = PHY_GBIT_FEATURES,
|
|
|
+ .config = &yt8531_config,
|
|
|
+ .startup = &ytphy_startup,
|
|
|
+ .shutdown = &genphy_shutdown,
|
|
|
+};
|
|
|
+
|
|
|
int phy_yutai_init(void)
|
|
|
{
|
|
|
- phy_register(&YT8511_driver);
|
|
|
+ phy_register(&YT8512_driver);
|
|
|
phy_register(&YT8521_driver);
|
|
|
+ phy_register(&YT8531_driver);
|
|
|
|
|
|
return 0;
|
|
|
}
|