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@@ -5,303 +5,276 @@
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* Author: yanhong <yanhong.wang@starfivetech.com>
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*
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*/
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+#include <common.h>
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+#include <asm/io.h>
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#include "starfive_ddr.h"
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-#define G_SPEED_2133 1
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-
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-#define OFFSET_SEL 0x80000000
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-#define DDR_2G_MASK 0x40000000
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-
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-static struct ddr_reg_clrset ddr_start_data[] = {
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- {(OFFSET_SEL | 89), 0xffffff00, 0x00000051},
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- {(OFFSET_SEL | 78), 0xfffffcff, 0x0},
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- {(OFFSET_SEL | 345), 0xffffff00, 0x00000051},
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- {(OFFSET_SEL | 334), 0xfffffcff, 0x0},
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- {(OFFSET_SEL | 601), 0xffffff00, 0x00000051},
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- {(OFFSET_SEL | 590), 0xfffffcff, 0x0},
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- {(OFFSET_SEL | 857), 0xffffff00, 0x00000051},
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- {(OFFSET_SEL | 846), 0xfffffcff, 0x0},
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- {(OFFSET_SEL | 1793), 0xfffffeff, 0x0},
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- {(OFFSET_SEL | 1793), 0xfffcffff, 0x0},
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- {(OFFSET_SEL | 125), 0xfff0ffff, 0x00010000},
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- {(OFFSET_SEL | 102), 0xfffffffc, 0x00000001},
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- {(OFFSET_SEL | 105), 0xffffffe0, 0x00000001},
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- {(OFFSET_SEL | 92), 0xfffffffe, 0x00000001},
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- {(OFFSET_SEL | 94), 0xffffe0ff, 0x00000200},
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- {(OFFSET_SEL | 96), 0xfffff0ff, 0x00000400},
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- {(OFFSET_SEL | 89), 0xffffff00, 0x00000051},
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- {(OFFSET_SEL | 381), 0xfff0ffff, 0x00010000},
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- {(OFFSET_SEL | 358), 0xfffffffc, 0x00000001},
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- {(OFFSET_SEL | 361), 0xffffffe0, 0x00000001},
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- {(OFFSET_SEL | 348), 0xfffffffe, 0x00000001},
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- {(OFFSET_SEL | 350), 0xffffe0ff, 0x00000200},
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- {(OFFSET_SEL | 352), 0xfffff0ff, 0x00000400},
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- {(OFFSET_SEL | 345), 0xffffff00, 0x00000051},
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- {(OFFSET_SEL | 637), 0xfff0ffff, 0x00010000},
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- {(OFFSET_SEL | 614), 0xfffffffc, 0x00000001},
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- {(OFFSET_SEL | 617), 0xffffffe0, 0x00000001},
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- {(OFFSET_SEL | 604), 0xfffffffe, 0x00000001},
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- {(OFFSET_SEL | 606), 0xffffe0ff, 0x00000200},
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- {(OFFSET_SEL | 608), 0xfffff0ff, 0x00000400},
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- {(OFFSET_SEL | 601), 0xffffff00, 0x00000051},
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- {(OFFSET_SEL | 893), 0xfff0ffff, 0x00010000},
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- {(OFFSET_SEL | 870), 0xfffffffc, 0x00000001},
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- {(OFFSET_SEL | 873), 0xffffffe0, 0x00000001},
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- {(OFFSET_SEL | 860), 0xfffffffe, 0x00000001},
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- {(OFFSET_SEL | 862), 0xffffe0ff, 0x00000200},
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- {(OFFSET_SEL | 864), 0xfffff0ff, 0x00000400},
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- {(OFFSET_SEL | 857), 0xffffff00, 0x00000051},
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- {(OFFSET_SEL | 1895), 0xffffe000, 0x00001342},
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- {(OFFSET_SEL | 1835), 0xfffff0ff, 0x00000200},
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- {(OFFSET_SEL | 1793), 0xfffffeff, 0x00000100},
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- {62, 0xfffffeff, 0x0},
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- {66, 0xfffffeff, 0x0},
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- {166, 0xffffff80, 0x00000001},
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- {62, 0xfff0ffff, 0x00010000},
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- {62, 0xf0ffffff, 0x01000000},
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- {166, 0xffff80ff, 0x00000100},
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- {179, 0xff80ffff, 0x00010000},
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- {67, 0xffe0ffff, 0x00010000},
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- {67, 0xe0ffffff, 0x01000000},
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- {179, 0x80ffffff, 0x01000000},
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- {166, 0xff80ffff, 0x00010000},
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- {62, 0xfff0ffff, 0x00010000},
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- {62, 0xf0ffffff, 0x01000000},
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- {166, 0x80ffffff, 0x01000000},
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- {182, 0xff80ffff, 0x00010000},
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- {67, 0xffe0ffff, 0x00010000},
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- {67, 0xe0ffffff, 0x01000000},
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- {182, 0x80ffffff, 0x01000000},
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- {167, 0xffffff80, 0x00000017},
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- {62, 0xfff0ffff, 0x00010000},
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- {62, 0xf0ffffff, 0x01000000},
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- {167, 0xffff80ff, 0x00001700},
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- {185, 0xff80ffff, 0x00200000},
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- {67, 0xffe0ffff, 0x00010000},
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- {67, 0xe0ffffff, 0x01000000},
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- {185, 0x80ffffff, 0x20000000},
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- {10, 0xffffffe0, 0x00000002},
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- {0, 0xfffffffe, 0x00000001},
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-#ifdef G_DDR_SIMULATION
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- {(OFFSET_SEL | 1860), 0x80ffffff, 0x01000000},
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-#endif
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- {11 | DDR_2G_MASK, 0xfffffff0, 0x00000005},
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- {247, 0xffffffff, 0x00000008},
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- {249, 0xffffffff, 0x00000800},
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- {252, 0xffffffff, 0x00000008},
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- {254, 0xffffffff, 0x00000800},
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- {281, 0xffffffff, 0x33000000},
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- {305, 0xffffffff, 0x33000000},
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- {329, 0xffffffff, 0x33000000},
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- {353, 0xffffffff, 0x33000000},
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- {289, 0xffffffff, 0x66000000},
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- {313, 0xffffffff, 0x66000000},
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- {337, 0xffffffff, 0x66000000},
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- {361, 0xffffffff, 0x66000000},
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- {282, 0xffffffff, 0x00160000},
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- {306, 0xffffffff, 0x00160000},
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- {330, 0xffffffff, 0x00160000},
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- {354, 0xffffffff, 0x00160000},
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- {290, 0xffffffff, 0x00160000},
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- {314, 0xffffffff, 0x00160000},
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- {338, 0xffffffff, 0x00160000},
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- {362, 0xffffffff, 0x00160000},
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- {282, 0xffffff00, 0x17},
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- {306, 0xffffff00, 0x17},
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- {330, 0xffffff00, 0x17},
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- {354, 0xffffff00, 0x17},
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- {290, 0xffffff00, 0x17},
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- {314, 0xffffff00, 0x17},
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- {338, 0xffffff00, 0x17},
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- {362, 0xffffff00, 0x17},
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- {282, 0xffff00ff, 0x2000},
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- {306, 0xffff00ff, 0x2000},
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- {330, 0xffff00ff, 0x2000},
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- {354, 0xffff00ff, 0x2000},
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- {290, 0xffff00ff, 0x2000},
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- {314, 0xffff00ff, 0x2000},
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- {338, 0xffff00ff, 0x2000},
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- {362, 0xffff00ff, 0x2000},
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- {(OFFSET_SEL | 65), 0xffffffff, 0x00000100},
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- {(OFFSET_SEL | 321), 0xffffffff, 0x00000100},
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- {(OFFSET_SEL | 577), 0xffffffff, 0x00000100},
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- {(OFFSET_SEL | 833), 0xffffffff, 0x00000100},
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-};
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-
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-static struct ddr_reg_clrset ddr_start_data1[] = {
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-#ifdef G_SPEED_3200
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- {96, 0xff00ffff, 0x00180000},
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- {352, 0xff00ffff, 0x00180000},
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- {608, 0xff00ffff, 0x00180000},
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- {864, 0xff00ffff, 0x00180000},
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-#elif defined G_SPEED_2666
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- {96, 0xff00ffff, 0x00140000},
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- {352, 0xff00ffff, 0x00140000},
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- {608, 0xff00ffff, 0x00140000},
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- {864, 0xff00ffff, 0x00140000},
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-#elif defined G_SPEED_2133
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- {96, 0xff00ffff, 0x00120000},
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- {352, 0xff00ffff, 0x00120000},
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- {608, 0xff00ffff, 0x00120000},
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- {864, 0xff00ffff, 0x00120000},
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-#endif
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- {33, 0xffffff00, 0x0040},
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- {289, 0xffffff00, 0x0040},
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- {545, 0xffffff00, 0x0040},
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- {801, 0xffffff00, 0x0040},
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- {1038, 0xfcffffff, 0x03000000},
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- {1294, 0xfcffffff, 0x03000000},
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- {1550, 0xfcffffff, 0x03000000},
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- {83, 0xffc0ffff, 0x70000},
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- {339, 0xffc0ffff, 0x70000},
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- {595, 0xffc0ffff, 0x70000},
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- {851, 0xffc0ffff, 0x70000},
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- {1062, 0xf800ffff, 0x70000},
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- {1318, 0xf800ffff, 0x70000},
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- {1574, 0xf800ffff, 0x70000},
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- {1892, 0xfffc0000, 0x15547},
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- {1893, 0xfffc0000, 0x7},
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- {1852, 0xffffe000, 0x07a},
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- {1853, 0xffffffff, 0x0100},
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- {1822, 0xffffffff, 0xFF},
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- {1896, 0xfffffc00, 0x03d5},
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- {91, 0xfc00ffff, 0x03d50000},
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- {347, 0xfc00ffff, 0x03d50000},
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- {603, 0xfc00ffff, 0x03d50000},
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- {859, 0xfc00ffff, 0x03d50000},
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-};
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-
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-static struct ddr_reg_set ddr_start_data2[] = {
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-
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- {1912, 0xcc3bfc7},
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- {1913, 0xff8f},
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- {1914, 0x33f07ff},
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- {1915, 0xc3c37ff},
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- {1916, 0x1fffff10},
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- {1917, 0x230070},
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- {1918, 0x3ff7ffff},
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- {1919, 0xe10},
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- {1920, 0x1fffffff},
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- {1921, 0x188411},
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- {1922, 0x1fffffff},
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- {1923, 0x180400},
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- {1924, 0x1fffffff},
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- {1925, 0x180400},
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- {1926, 0x1fffffcf},
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- {1927, 0x188400},
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- {1928, 0x1fffffff},
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- {1929, 0x4188411},
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- {1837, 0x24410},
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- {1840, 0x24410},
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- {1842, 0x2ffff},
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-};
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-
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-static struct ddr_reg_clrset ddr_start_data3[] = {
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- {76, 0xff0000f8, 0x00ff8f07},
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- {332, 0xff0000f8, 0x00ff8f07},
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- {588, 0xff0000f8, 0x00ff8f07},
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- {844, 0xff0000f8, 0x00ff8f07},
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- {77, 0xffff0000, 0xff8f},
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- {333, 0xffff0000, 0xff8f},
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- {589, 0xffff0000, 0xff8f},
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- {845, 0xffff0000, 0xff8f},
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- {1062, 0xffffff00, 0xff},
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- {1318, 0xffffff00, 0xff},
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- {1574, 0xffffff00, 0xff},
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- {1028, 0xffffffff, 0x1000000},
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- {1284, 0xffffffff, 0x1000000},
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- {1540, 0xffffffff, 0x1000000},
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-};
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-
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-static struct ddr_reg_clrset ddr_start_data4[] = {
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- {130, 0x0000ffff, 0xffff0000},
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- {386, 0x0000ffff, 0xffff0000},
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- {642, 0x0000ffff, 0xffff0000},
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- {898, 0x0000ffff, 0xffff0000},
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- {131, 0xfffffff0, 0xf},
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- {387, 0xfffffff0, 0xf},
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- {643, 0xfffffff0, 0xf},
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- {899, 0xfffffff0, 0xf},
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- {29, 0xc0ffffff, 0x10000000},
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- {285, 0xc0ffffff, 0x10000000},
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- {541, 0xc0ffffff, 0x10000000},
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- {797, 0xc0ffffff, 0x10000000},
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- {30, 0xffffffff, 0x00080000},
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- {286, 0xffffffff, 0x00080000},
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- {542, 0xffffffff, 0x00080000},
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- {798, 0xffffffff, 0x00080000},
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- {31, 0xffffffc0, 0x00000010},
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- {287, 0xffffffc0, 0x00000010},
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- {543, 0xffffffc0, 0x00000010},
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- {799, 0xffffffc0, 0x00000010},
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- {1071, 0xfffffff0, 0x00000008},
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- {1327, 0xfffffff0, 0x00000008},
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- {1583, 0xfffffff0, 0x00000008},
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- {1808, 0xfffffff0, 0x00000008},
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- {1896, 0xfff0ffff, 0x00080000},
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+static struct ddr_reg_cfg ddr_start_cfg[] = {
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+ {89, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
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+ {78, 0xfffffcff, 0x0, (OFFSET_SEL | REGCLRSETALL)},
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+ {345, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
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+ {334, 0xfffffcff, 0x0, (OFFSET_SEL | REGCLRSETALL)},
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+ {601, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
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+ {590, 0xfffffcff, 0x0, (OFFSET_SEL | REGCLRSETALL)},
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+ {857, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
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+ {846, 0xfffffcff, 0x0, (OFFSET_SEL | REGCLRSETALL)},
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+ {1793, 0xfffffeff, 0x0, (OFFSET_SEL | REGCLRSETALL)},
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+ {1793, 0xfffcffff, 0x0, (OFFSET_SEL | REGCLRSETALL)},
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+ {125, 0xfff0ffff, 0x00010000, (OFFSET_SEL | REGCLRSETALL)},
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+ {102, 0xfffffffc, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
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+ {105, 0xffffffe0, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
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+ {92, 0xfffffffe, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
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+ {94, 0xffffe0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)},
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+ {96, 0xfffff0ff, 0x00000400, (OFFSET_SEL | REGCLRSETALL)},
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+ {89, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
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+ {381, 0xfff0ffff, 0x00010000, (OFFSET_SEL | REGCLRSETALL)},
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+ {358, 0xfffffffc, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
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+ {361, 0xffffffe0, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
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+ {348, 0xfffffffe, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
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+ {350, 0xffffe0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)},
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+ {352, 0xfffff0ff, 0x00000400, (OFFSET_SEL | REGCLRSETALL)},
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+ {345, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
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+ {637, 0xfff0ffff, 0x00010000, (OFFSET_SEL | REGCLRSETALL)},
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+ {614, 0xfffffffc, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
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+ {617, 0xffffffe0, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
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+ {604, 0xfffffffe, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
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+ {606, 0xffffe0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)},
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+ {608, 0xfffff0ff, 0x00000400, (OFFSET_SEL | REGCLRSETALL)},
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+ {601, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
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+ {893, 0xfff0ffff, 0x00010000, (OFFSET_SEL | REGCLRSETALL)},
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+ {870, 0xfffffffc, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
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+ {873, 0xffffffe0, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
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+ {860, 0xfffffffe, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
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+ {862, 0xffffe0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)},
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+ {864, 0xfffff0ff, 0x00000400, (OFFSET_SEL | REGCLRSETALL)},
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+ {857, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
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+ {1895, 0xffffe000, 0x00001342, (OFFSET_SEL | REGCLRSETALL)},
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+ {1835, 0xfffff0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)},
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+ {1793, 0xfffffeff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)},
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+ {62, 0xfffffeff, 0x0, REGCLRSETALL},
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+ {66, 0xfffffeff, 0x0, REGCLRSETALL},
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+ {166, 0xffffff80, 0x00000001, REGCLRSETALL},
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+ {62, 0xfff0ffff, 0x00010000, REGCLRSETALL},
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+ {62, 0xf0ffffff, 0x01000000, REGCLRSETALL},
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+ {166, 0xffff80ff, 0x00000100, REGCLRSETALL},
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+ {179, 0xff80ffff, 0x00010000, REGCLRSETALL},
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+ {67, 0xffe0ffff, 0x00010000, REGCLRSETALL},
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+ {67, 0xe0ffffff, 0x01000000, REGCLRSETALL},
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+ {179, 0x80ffffff, 0x01000000, REGCLRSETALL},
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+ {166, 0xff80ffff, 0x00010000, REGCLRSETALL},
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+ {62, 0xfff0ffff, 0x00010000, REGCLRSETALL},
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+ {62, 0xf0ffffff, 0x01000000, REGCLRSETALL},
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+ {166, 0x80ffffff, 0x01000000, REGCLRSETALL},
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+ {182, 0xff80ffff, 0x00010000, REGCLRSETALL},
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+ {67, 0xffe0ffff, 0x00010000, REGCLRSETALL},
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+ {67, 0xe0ffffff, 0x01000000, REGCLRSETALL},
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+ {182, 0x80ffffff, 0x01000000, REGCLRSETALL},
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+ {167, 0xffffff80, 0x00000017, REGCLRSETALL},
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+ {62, 0xfff0ffff, 0x00010000, REGCLRSETALL},
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+ {62, 0xf0ffffff, 0x01000000, REGCLRSETALL},
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+ {167, 0xffff80ff, 0x00001700, REGCLRSETALL},
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+ {185, 0xff80ffff, 0x00200000, REGCLRSETALL},
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+ {67, 0xffe0ffff, 0x00010000, REGCLRSETALL},
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+ {67, 0xe0ffffff, 0x01000000, REGCLRSETALL},
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|
+ {185, 0x80ffffff, 0x20000000, REGCLRSETALL},
|
|
|
+ {10, 0xffffffe0, 0x00000002, REGCLRSETALL},
|
|
|
+ {0, 0xfffffffe, 0x00000001, REGCLRSETALL},
|
|
|
+ {11, 0xfffffff0, 0x00000005, (F_CLRSET | REG2G)},
|
|
|
+ {247, 0xffffffff, 0x00000008, REGCLRSETALL},
|
|
|
+ {249, 0xffffffff, 0x00000800, REGCLRSETALL},
|
|
|
+ {252, 0xffffffff, 0x00000008, REGCLRSETALL},
|
|
|
+ {254, 0xffffffff, 0x00000800, REGCLRSETALL},
|
|
|
+ {281, 0xffffffff, 0x33000000, REGCLRSETALL},
|
|
|
+ {305, 0xffffffff, 0x33000000, REGCLRSETALL},
|
|
|
+ {329, 0xffffffff, 0x33000000, REGCLRSETALL},
|
|
|
+ {353, 0xffffffff, 0x33000000, REGCLRSETALL},
|
|
|
+ {289, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)},
|
|
|
+ {313, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)},
|
|
|
+ {337, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)},
|
|
|
+ {361, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)},
|
|
|
+ {289, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)},
|
|
|
+ {313, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)},
|
|
|
+ {337, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)},
|
|
|
+ {361, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)},
|
|
|
+ {282, 0xffffffff, 0x00160000, REGCLRSETALL},
|
|
|
+ {306, 0xffffffff, 0x00160000, REGCLRSETALL},
|
|
|
+ {330, 0xffffffff, 0x00160000, REGCLRSETALL},
|
|
|
+ {354, 0xffffffff, 0x00160000, REGCLRSETALL},
|
|
|
+ {290, 0xffffffff, 0x00160000, REGCLRSETALL},
|
|
|
+ {314, 0xffffffff, 0x00160000, REGCLRSETALL},
|
|
|
+ {338, 0xffffffff, 0x00160000, REGCLRSETALL},
|
|
|
+ {362, 0xffffffff, 0x00160000, REGCLRSETALL},
|
|
|
+ {282, 0xffffff00, 0x17, REGCLRSETALL},
|
|
|
+ {306, 0xffffff00, 0x17, REGCLRSETALL},
|
|
|
+ {330, 0xffffff00, 0x17, REGCLRSETALL},
|
|
|
+ {354, 0xffffff00, 0x17, REGCLRSETALL},
|
|
|
+ {290, 0xffffff00, 0x17, REGCLRSETALL},
|
|
|
+ {314, 0xffffff00, 0x17, REGCLRSETALL},
|
|
|
+ {338, 0xffffff00, 0x17, REGCLRSETALL},
|
|
|
+ {362, 0xffffff00, 0x17, REGCLRSETALL},
|
|
|
+ {282, 0xffff00ff, 0x2000, REGCLRSETALL},
|
|
|
+ {306, 0xffff00ff, 0x2000, REGCLRSETALL},
|
|
|
+ {330, 0xffff00ff, 0x2000, REGCLRSETALL},
|
|
|
+ {354, 0xffff00ff, 0x2000, REGCLRSETALL},
|
|
|
+ {290, 0xffff00ff, 0x2000, REGCLRSETALL},
|
|
|
+ {314, 0xffff00ff, 0x2000, REGCLRSETALL},
|
|
|
+ {338, 0xffff00ff, 0x2000, REGCLRSETALL},
|
|
|
+ {362, 0xffff00ff, 0x2000, REGCLRSETALL},
|
|
|
+ {65, 0xffffffff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {321, 0xffffffff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {577, 0xffffffff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {833, 0xffffffff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {96, 0x0, 0x300, (OFFSET_SEL | REGADDSETALL)},
|
|
|
+ {352, 0x0, 0x300, (OFFSET_SEL | REGADDSETALL)},
|
|
|
+ {608, 0x0, 0x300, (OFFSET_SEL | REGADDSETALL)},
|
|
|
+ {864, 0x0, 0x300, (OFFSET_SEL | REGADDSETALL)},
|
|
|
+ {96, 0xff00ffff, 0x00120000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {352, 0xff00ffff, 0x00120000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {608, 0xff00ffff, 0x00120000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {864, 0xff00ffff, 0x00120000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {33, 0xffffff00, 0x0040, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {289, 0xffffff00, 0x0040, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {545, 0xffffff00, 0x0040, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {801, 0xffffff00, 0x0040, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {1038, 0xfcffffff, 0x03000000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {1294, 0xfcffffff, 0x03000000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {1550, 0xfcffffff, 0x03000000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {83, 0xffc0ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {339, 0xffc0ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {595, 0xffc0ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {851, 0xffc0ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {1062, 0xf800ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {1318, 0xf800ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {1574, 0xf800ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {1892, 0xfffc0000, 0x15547, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {1893, 0xfffc0000, 0x7, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {1852, 0xffffe000, 0x07a, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {1853, 0xffffffff, 0x0100, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {1822, 0xffffffff, 0xFF, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {1896, 0xfffffc00, 0x03d5, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {91, 0xfc00ffff, 0x03d50000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {347, 0xfc00ffff, 0x03d50000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {603, 0xfc00ffff, 0x03d50000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {859, 0xfc00ffff, 0x03d50000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {1912, 0x0, 0xcc3bfc7, (OFFSET_SEL | REGSETALL)},
|
|
|
+ {1913, 0x0, 0xff8f, (OFFSET_SEL | REGSETALL)},
|
|
|
+ {1914, 0x0, 0x33f07ff, (OFFSET_SEL | REGSETALL)},
|
|
|
+ {1915, 0x0, 0xc3c37ff, (OFFSET_SEL | REGSETALL)},
|
|
|
+ {1916, 0x0, 0x1fffff10, (OFFSET_SEL | REGSETALL)},
|
|
|
+ {1917, 0x0, 0x230070, (OFFSET_SEL | REGSETALL)},
|
|
|
+ {1918, 0x0, 0x3ff7ffff, (OFFSET_SEL | REG4G | REG2G | F_SET)},
|
|
|
+ {1918, 0x0, 0x3ff7ffff, (OFFSET_SEL | REG8G | F_SET)},
|
|
|
+ {1919, 0x0, 0xe10, (OFFSET_SEL | REGSETALL)},
|
|
|
+ {1920, 0x0, 0x1fffffff, (OFFSET_SEL | REGSETALL)},
|
|
|
+ {1921, 0x0, 0x188411, (OFFSET_SEL | REGSETALL)},
|
|
|
+ {1922, 0x0, 0x1fffffff, (OFFSET_SEL | REGSETALL)},
|
|
|
+ {1923, 0x0, 0x180400, (OFFSET_SEL | REGSETALL)},
|
|
|
+ {1924, 0x0, 0x1fffffff, (OFFSET_SEL | REGSETALL)},
|
|
|
+ {1925, 0x0, 0x180400, (OFFSET_SEL | REGSETALL)},
|
|
|
+ {1926, 0x0, 0x1fffffcf, (OFFSET_SEL | REGSETALL)},
|
|
|
+ {1927, 0x0, 0x188400, (OFFSET_SEL | REGSETALL)},
|
|
|
+ {1928, 0x0, 0x1fffffff, (OFFSET_SEL | REGSETALL)},
|
|
|
+ {1929, 0x0, 0x4188411, (OFFSET_SEL | REGSETALL)},
|
|
|
+ {1837, 0x0, 0x24410, (OFFSET_SEL | REGSETALL)},
|
|
|
+ {1840, 0x0, 0x24410, (OFFSET_SEL | REGSETALL)},
|
|
|
+ {1842, 0x0, 0x2ffff, (OFFSET_SEL | REGSETALL)},
|
|
|
+ {76, 0xff0000f8, 0x00ff8f07, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {332, 0xff0000f8, 0x00ff8f07, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {588, 0xff0000f8, 0x00ff8f07, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {844, 0xff0000f8, 0x00ff8f07, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {77, 0xffff0000, 0xff8f, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {333, 0xffff0000, 0xff8f, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {589, 0xffff0000, 0xff8f, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {845, 0xffff0000, 0xff8f, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {1062, 0xffffff00, 0xff, (OFFSET_SEL | REG4G | REG2G | F_CLRSET)},
|
|
|
+ {1318, 0xffffff00, 0xff, (OFFSET_SEL | REG4G | REG2G | F_CLRSET)},
|
|
|
+ {1574, 0xffffff00, 0xff, (OFFSET_SEL | REG4G | REG2G | F_CLRSET)},
|
|
|
+ {1062, 0xffffff00, 0xfb, (OFFSET_SEL | REG8G | F_CLRSET)},
|
|
|
+ {1318, 0xffffff00, 0xfb, (OFFSET_SEL | REG8G | F_CLRSET)},
|
|
|
+ {1574, 0xffffff00, 0xfb, (OFFSET_SEL | REG8G | F_CLRSET)},
|
|
|
+ {1028, 0xffffffff, 0x1000000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {1284, 0xffffffff, 0x1000000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {1540, 0xffffffff, 0x1000000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {1848, 0x0, 0x3cf07f8, (OFFSET_SEL | REGSETALL)},
|
|
|
+ {1849, 0x0, 0x3f, (OFFSET_SEL | REGSETALL)},
|
|
|
+ {1850, 0x0, 0x1fffff, (OFFSET_SEL | REGSETALL)},
|
|
|
+ {1851, 0x0, 0x060000, (OFFSET_SEL | REGSETALL)},
|
|
|
+ {130, 0x0000ffff, 0xffff0000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {386, 0x0000ffff, 0xffff0000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {642, 0x0000ffff, 0xffff0000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {898, 0x0000ffff, 0xffff0000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {131, 0xfffffff0, 0xf, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {387, 0xfffffff0, 0xf, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {643, 0xfffffff0, 0xf, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {899, 0xfffffff0, 0xf, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {29, 0xc0ffffff, 0x10000000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {285, 0xc0ffffff, 0x10000000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {541, 0xc0ffffff, 0x10000000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {797, 0xc0ffffff, 0x10000000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {30, 0xffffffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {286, 0xffffffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {542, 0xffffffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {798, 0xffffffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {31, 0xffffffc0, 0x00000010, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {287, 0xffffffc0, 0x00000010, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {543, 0xffffffc0, 0x00000010, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {799, 0xffffffc0, 0x00000010, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {1071, 0xfffffff0, 0x00000008, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {1327, 0xfffffff0, 0x00000008, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {1583, 0xfffffff0, 0x00000008, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {1808, 0xfffffff0, 0x00000008, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
+ {1896, 0xfff0ffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)},
|
|
|
};
|
|
|
|
|
|
-void ddr_phy_start(u32 *phyreg, enum ddr_size_t size)
|
|
|
+void ddr_reg_set(u32 *reg, struct ddr_reg_cfg *data,
|
|
|
+ u32 len, u32 mask)
|
|
|
{
|
|
|
- u32 i, len;
|
|
|
- u32 *addr, *reg;
|
|
|
- u32 offset;
|
|
|
-
|
|
|
- reg = phyreg + 4096;
|
|
|
+ u32 *addr;
|
|
|
+ u32 i;
|
|
|
|
|
|
- len = sizeof(ddr_start_data)/sizeof(struct ddr_reg_clrset);
|
|
|
for (i = 0; i < len; i++) {
|
|
|
-
|
|
|
- if ((size == DDR_SIZE_4G) &&
|
|
|
- (ddr_start_data[i].offset & DDR_2G_MASK))
|
|
|
+ if (!(data[i].flag & mask))
|
|
|
continue;
|
|
|
|
|
|
- if (ddr_start_data[i].offset & OFFSET_SEL) {
|
|
|
- offset = ddr_start_data[i].offset & (~OFFSET_SEL);
|
|
|
- addr = reg;
|
|
|
- } else {
|
|
|
- offset = ddr_start_data[i].offset;
|
|
|
- addr = phyreg + 2048;
|
|
|
- }
|
|
|
- offset &= (~DDR_2G_MASK);
|
|
|
- DDR_REG_TRIGGER((addr + offset), ddr_start_data[i].mask,
|
|
|
- ddr_start_data[i].val);
|
|
|
- }
|
|
|
+ if (data[i].flag & OFFSET_SEL)
|
|
|
+ addr = reg + PHY_AC_BASE_ADDR + data[i].offset;
|
|
|
+ else
|
|
|
+ addr = reg + PHY_BASE_ADDR + data[i].offset;
|
|
|
|
|
|
- out_le32(reg + 96, in_le32(reg + 96) + 0x300);
|
|
|
- out_le32(reg + 352, in_le32(reg + 352) + 0x300);
|
|
|
- out_le32(reg + 608, in_le32(reg + 608) + 0x300);
|
|
|
- out_le32(reg + 864, in_le32(reg + 864) + 0x300);
|
|
|
+ if (data[i].flag & F_CLRSET)
|
|
|
+ DDR_REG_TRIGGER(addr, data[i].mask, data[i].val);
|
|
|
+ else if (data[i].flag & F_SET)
|
|
|
+ out_le32(addr, data[i].val);
|
|
|
+ else
|
|
|
+ out_le32(addr, in_le32(addr) + data[i].val);
|
|
|
+ }
|
|
|
+}
|
|
|
|
|
|
- len = sizeof(ddr_start_data1)/sizeof(struct ddr_reg_clrset);
|
|
|
- for (i = 0; i < len; i++)
|
|
|
- DDR_REG_TRIGGER((reg + ddr_start_data1[i].offset),
|
|
|
- ddr_start_data1[i].mask,
|
|
|
- ddr_start_data1[i].val);
|
|
|
+void ddr_phy_start(u32 *phyreg, enum ddr_size_t size)
|
|
|
+{
|
|
|
+ u32 len;
|
|
|
+ u32 mask;
|
|
|
|
|
|
- len = sizeof(ddr_start_data2)/sizeof(struct ddr_reg_set);
|
|
|
- for (i = 0; i < len; i++)
|
|
|
- out_le32((reg + ddr_start_data2[i].offset),
|
|
|
- ddr_start_data2[i].val);
|
|
|
+ switch (size) {
|
|
|
+ case DDR_SIZE_2G:
|
|
|
+ mask = REG2G;
|
|
|
+ break;
|
|
|
|
|
|
- len = sizeof(ddr_start_data3)/sizeof(struct ddr_reg_clrset);
|
|
|
- for (i = 0; i < len; i++)
|
|
|
- DDR_REG_TRIGGER((reg + ddr_start_data3[i].offset),
|
|
|
- ddr_start_data3[i].mask,
|
|
|
- ddr_start_data3[i].val);
|
|
|
+ case DDR_SIZE_4G:
|
|
|
+ mask = REG4G;
|
|
|
+ break;
|
|
|
|
|
|
- out_le32((reg + 1848), 0x3cf07f8);
|
|
|
- out_le32((reg + 1849), 0x3f);
|
|
|
- out_le32((reg + 1850), 0x1fffff);
|
|
|
- out_le32((reg + 1851), 0x060000);
|
|
|
+ case DDR_SIZE_8G:
|
|
|
+ mask = REG8G;
|
|
|
+ break;
|
|
|
|
|
|
- len = sizeof(ddr_start_data4)/sizeof(struct ddr_reg_clrset);
|
|
|
- for (i = 0; i < len; i++)
|
|
|
- DDR_REG_TRIGGER((reg + ddr_start_data4[i].offset),
|
|
|
- ddr_start_data4[i].mask,
|
|
|
- ddr_start_data4[i].val);
|
|
|
+ case DDR_SIZE_16G:
|
|
|
+ default:
|
|
|
+ return;
|
|
|
+ };
|
|
|
|
|
|
+ len = sizeof(ddr_start_cfg) / sizeof(struct ddr_reg_cfg);
|
|
|
+ ddr_reg_set(phyreg, ddr_start_cfg, len, mask);
|
|
|
out_le32(phyreg, 0x01);
|
|
|
}
|
|
|
-
|