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riscv: dts: jh7110: Add reset property to DDR control node

Add reset property configuration to DDR control device tree node.

Signed-off-by: Yan Hong Wang <yanhongwang@linux.starfivetech.com>
Yan Hong Wang 1 year ago
parent
commit
7efb109f1d
1 changed files with 5 additions and 1 deletions
  1. 5 1
      arch/riscv/dts/jh7110-u-boot.dtsi

+ 5 - 1
arch/riscv/dts/jh7110-u-boot.dtsi

@@ -59,8 +59,12 @@
 		};
 
 		dmc: dmc@100b0000 {
-			compatible = "starfive,jh7110-ddr";
+			compatible = "starfive,jh7110-dmc";
 			reg = <0x0 0x15700000 0x0 0x10000 0x0 0x13000000 0x0 0x10000>;
+			resets = <&rstgen RSTN_U0_DDR_AXI>,
+					<&rstgen RSTN_U0_DDR_OSC>,
+					<&rstgen RSTN_U0_DDR_APB>;
+			reset-names = "axi", "osc", "apb";
 			clock-frequency = <2133>;
 			u-boot,dm-spl;
 		};