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@@ -0,0 +1,45 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * Copyright (C) 2022 Starfive, Inc.
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+ * Author: yanhong <yanhong.wang@starfivetech.com>
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+ *
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+ */
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+
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+#include <dm.h>
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+#include <log.h>
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+#include <asm/csr.h>
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+
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+#define CSR_U74_FEATURE_DISABLE 0x7c1
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+
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+int spl_soc_init(void)
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+{
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+ int ret;
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+ struct udevice *dev;
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+
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+ /* DDR init */
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+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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+ if (ret) {
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+ debug("DRAM init failed: %d\n", ret);
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+ return ret;
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+ }
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+
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+ /*flash init*/
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+ ret = uclass_get_device(UCLASS_SPI_FLASH, 0, &dev);
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+ if (ret) {
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+ debug("SPI init failed: %d\n", ret);
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+ return ret;
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+ }
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+ return 0;
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+}
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+
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+void harts_early_init(void)
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+{
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+ /*
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+ * Feature Disable CSR
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+ *
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+ * Clear feature disable CSR to '0' to turn on all features for
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+ * each core. This operation must be in M-mode.
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+ */
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+ if (CONFIG_IS_ENABLED(RISCV_MMODE))
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+ csr_write(CSR_U74_FEATURE_DISABLE, 0);
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+}
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