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@@ -0,0 +1,688 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * Copyright (C) 2022 Starfive, Inc.
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+ * Author: yanhong <yanhong.wang@starfivetech.com>
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+ *
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+ */
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+
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+#include <common.h>
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+#include <malloc.h>
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+#include <clk-uclass.h>
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+#include <clk.h>
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+#include <dm/device.h>
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+#include <dm/devres.h>
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+#include <dm.h>
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+#include <linux/clk-provider.h>
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+#include <dt-bindings/clock/starfive-jh7110-clkgen.h>
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+#include <log.h>
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+#include <linux/clk-provider.h>
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+
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+#define STARFIVE_CLK_ENABLE_SHIFT 31 /*[31]*/
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+#define STARFIVE_CLK_INVERT_SHIFT 30 /*[30]*/
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+#define STARFIVE_CLK_MUX_SHIFT 24 /*[29:24]*/
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+#define STARFIVE_CLK_DIV_SHIFT 0 /*[23:0]*/
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+
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+#define SYS_OFFSET(id) (id * 4)
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+#define STG_OFFSET(id) ((id - JH7110_CLK_SYS_REG_END) * 4)
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+#define AON_OFFSET(id) ((id - JH7110_CLK_STG_REG_END) * 4)
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+
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+#define JH7110_PLL0 (JH7110_CLK_RTC+1)
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+#define JH7110_PLL1 (JH7110_CLK_RTC+2)
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+#define JH7110_PLL2 (JH7110_CLK_RTC+3)
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+
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+struct jh7110_clk_priv {
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+ void __iomem *sys;
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+ void __iomem *stg;
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+ void __iomem *aon;
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+};
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+
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+static const char *cpu_root_sels[2] = {
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+ [0] = "osc",
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+ [1] = "pll0_out",
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+};
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+
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+static const char *perh_root_sels[2] = {
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+ [0] = "pll0_out",
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+ [1] = "pll2_out",
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+};
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+
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+static const char *bus_root_sels[2] = {
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+ [0] = "osc",
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+ [1] = "pll2_out",
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+};
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+
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+static const char *qspi_ref_sels[2] = {
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+ [0] = "osc",
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+ [1] = "clk_qspi_ref_src",
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+};
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+
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+static const char *gmac5_tx_sels[2] = {
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+ [0] = "gmac1_gtxclk",
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+ [1] = "gmac1_rmii_rtx",
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+};
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+
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+static const char *aon_apb_func_sels[2] = {
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+ [0] = "osc_div4",
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+ [1] = "osc",
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+};
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+
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+static const char *u0_dw_gmac5_axi64_clk_tx_sels[2] = {
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+ [0] = "gmac0_gtxclk",
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+ [1] = "gmac0_rmii_rtx",
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+};
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+
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+static ulong starfive_clk_get_rate(struct clk *clk)
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+{
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+ struct clk *c;
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+ int ret;
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+
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+ debug("%s(#%lu)\n", __func__, clk->id);
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+
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+ ret = clk_get_by_id(clk->id, &c);
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+ if (ret)
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+ return ret;
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+
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+ return clk_get_rate(c);
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+}
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+
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+static ulong starfive_clk_set_rate(struct clk *clk, unsigned long rate)
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+{
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+ struct clk *c;
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+ int ret;
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+
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+ debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
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+
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+ ret = clk_get_by_id(clk->id, &c);
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+ if (ret)
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+ return ret;
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+
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+ return clk_set_rate(c, rate);
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+}
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+
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+static int __starfive_clk_enable(struct clk *clk, bool enable)
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+{
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+ struct clk *c;
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+ int ret;
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+
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+ debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
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+
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+ ret = clk_get_by_id(clk->id, &c);
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+ if (ret)
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+ return ret;
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+
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+ if (enable)
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+ ret = clk_enable(c);
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+ else
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+ ret = clk_disable(c);
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+
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+ return ret;
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+}
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+
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+static int starfive_clk_disable(struct clk *clk)
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+{
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+ return __starfive_clk_enable(clk, 0);
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+}
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+
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+static int starfive_clk_enable(struct clk *clk)
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+{
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+ return __starfive_clk_enable(clk, 1);
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+}
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+
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+static int starfive_clk_set_parent(struct clk *clk, struct clk *parent)
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+{
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+ struct clk *c, *cp;
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+ int ret;
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+
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+ debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
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+
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+ ret = clk_get_by_id(clk->id, &c);
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+ if (ret)
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+ return ret;
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+
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+ ret = clk_get_by_id(parent->id, &cp);
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+ if (ret)
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+ return ret;
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+
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+ ret = clk_set_parent(c, cp);
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+ c->dev->parent = cp->dev;
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+
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+ return ret;
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+}
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+
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+static const struct clk_ops starfive_clk_ops = {
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+ .set_rate = starfive_clk_set_rate,
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+ .get_rate = starfive_clk_get_rate,
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+ .enable = starfive_clk_enable,
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+ .disable = starfive_clk_disable,
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+ .set_parent = starfive_clk_set_parent,
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+};
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+
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+static struct clk *starfive_clk_mux(void __iomem *reg,
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+ const char *name,
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+ unsigned int offset,
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+ u8 width,
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+ const char * const *parent_names,
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+ u8 num_parents)
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+{
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+ return clk_register_mux(NULL, name, parent_names, num_parents, 0,
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+ reg + offset, STARFIVE_CLK_MUX_SHIFT, width, 0);
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+}
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+
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+static struct clk *starfive_clk_gate(void __iomem *reg,
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+ const char *name,
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+ const char *parent_name,
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+ unsigned int offset)
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+{
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+ return clk_register_gate(NULL, name, parent_name, 0, reg+offset,
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+ STARFIVE_CLK_ENABLE_SHIFT, 0, NULL);
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+}
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+
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+static struct clk *starfive_clk_fix_factor(void __iomem *reg,
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+ const char *name,
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+ const char *parent_name,
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+ unsigned int mult,
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+ unsigned int div)
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+{
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+ return clk_register_fixed_factor(NULL, name, parent_name,
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+ 0, mult, div);
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+
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+}
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+
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+static struct clk *starfive_clk_divider(void __iomem *reg,
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+ const char *name,
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+ const char *parent_name,
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+ unsigned int offset,
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+ u8 width)
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+{
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+ return clk_register_divider(NULL, name, parent_name, 0, reg+offset, 0,
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+ width, CLK_DIVIDER_ONE_BASED);
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+}
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+
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+
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+static struct clk *starfive_clk_composite(void __iomem *reg,
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+ const char *name,
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+ const char * const *parent_names,
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+ unsigned int num_parents,
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+ unsigned int offset,
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+ unsigned int mux_width,
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+ unsigned int gate_width,
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+ unsigned int div_width)
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+{
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+ struct clk *clk = ERR_PTR(-ENOMEM);
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+ struct clk_divider *div = NULL;
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+ struct clk_gate *gate = NULL;
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+ struct clk_mux *mux = NULL;
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+ int mask_arry[4] = {0x1, 0x3, 0x7, 0xF};
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+ int mask;
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+
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+ if (mux_width) {
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+ if (mux_width > 4)
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+ goto fail;
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+ else
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+ mask = mask_arry[mux_width-1];
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+
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+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
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+ if (!mux)
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+ goto fail;
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+
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+ mux->reg = reg + offset;
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+ mux->mask = mask;
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+ mux->shift = STARFIVE_CLK_MUX_SHIFT;
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+ mux->num_parents = num_parents;
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+ mux->flags = 0;
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+ mux->parent_names = parent_names;
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+ }
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+
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+ if (gate_width) {
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+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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+
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+ if (!gate)
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+ goto fail;
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+
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+ gate->reg = reg + offset;
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+ gate->bit_idx = STARFIVE_CLK_ENABLE_SHIFT;
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+ gate->flags = 0;
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+ }
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+
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+ if (div_width) {
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+ div = kzalloc(sizeof(*div), GFP_KERNEL);
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+ if (!div)
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+ goto fail;
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+
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+ div->reg = reg + offset;
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+ div->shift = STARFIVE_CLK_DIV_SHIFT;
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+ div->width = div_width;
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+ div->flags = CLK_DIVIDER_ONE_BASED;
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+ div->table = NULL;
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+ }
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+
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+ clk = clk_register_composite(NULL, name,
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+ parent_names, num_parents,
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+ &mux->clk, &clk_mux_ops,
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+ &div->clk, &clk_divider_ops,
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+ &gate->clk, &clk_gate_ops, 0);
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+
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+ if (IS_ERR(clk))
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+ goto fail;
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+
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+ return clk;
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+
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+fail:
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+ kfree(gate);
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+ kfree(div);
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+ kfree(mux);
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+ return ERR_CAST(clk);
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+}
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+
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+static struct clk *starfive_clk_fix_parent_composite(void __iomem *reg,
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+ const char *name,
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+ const char *parent_names,
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+ unsigned int offset,
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+ unsigned int mux_width,
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+ unsigned int gate_width,
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+ unsigned int div_width)
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+{
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+ const char * const *parents;
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+
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+ parents = &parent_names;
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+
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+ return starfive_clk_composite(reg, name, parents, 1, offset,
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+ mux_width, gate_width, div_width);
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+}
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+
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+static struct clk *starfive_clk_gate_divider(void __iomem *reg,
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+ const char *name,
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+ const char *parent,
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+ unsigned int offset,
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+ unsigned int width)
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+{
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+ const char * const *parent_names;
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+
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+ parent_names = &parent;
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+
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+ return starfive_clk_composite(reg, name, parent_names, 1,
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+ offset, 0, 1, width);
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+}
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+
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+static struct clk *starfive_clk_gate_dis(void __iomem *reg,
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+ const char *name,
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+ const char *parent_name,
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+ unsigned int offset)
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+{
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+ return clk_register_gate(NULL, name, parent_name, 0, reg+offset,
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+ STARFIVE_CLK_ENABLE_SHIFT,
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+ CLK_GATE_SET_TO_DISABLE, NULL);
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+}
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+
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+static int jh7110_clk_init(struct udevice *dev)
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+{
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+ struct jh7110_clk_priv *priv = dev_get_priv(dev);
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+
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+ clk_dm(JH7110_PLL0,
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+ starfive_clk_fix_factor(priv->sys,
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+ "pll0_out", "osc", 52, 1));
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+ clk_dm(JH7110_PLL1,
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+ starfive_clk_fix_factor(priv->sys,
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+ "pll1_out", "osc", 44, 1));
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+ clk_dm(JH7110_PLL2,
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+ starfive_clk_fix_factor(priv->sys,
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+ "pll2_out", "osc", 51, 1));
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+
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+ /*root*/
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+ clk_dm(JH7110_CPU_ROOT,
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+ starfive_clk_mux(priv->sys, "cpu_root",
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+ SYS_OFFSET(JH7110_CPU_ROOT), 1,
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+ cpu_root_sels, ARRAY_SIZE(cpu_root_sels)));
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+ clk_dm(JH7110_CPU_CORE,
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+ starfive_clk_divider(priv->sys,
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+ "cpu_core", "cpu_root",
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+ SYS_OFFSET(JH7110_CPU_CORE), 3));
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+ clk_dm(JH7110_CPU_BUS,
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+ starfive_clk_divider(priv->sys,
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+ "cpu_bus", "cpu_core",
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+ SYS_OFFSET(JH7110_CPU_BUS), 2));
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+ clk_dm(JH7110_DDR_ROOT,
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+ starfive_clk_fix_factor(priv->sys,
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+ "ddr_root", "pll1_out", 1, 1));
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+ clk_dm(JH7110_GMACUSB_ROOT,
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+ starfive_clk_fix_factor(priv->sys,
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+ "gmacusb_root", "pll0_out", 1, 1));
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+ clk_dm(JH7110_PERH_ROOT,
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+ starfive_clk_mux(priv->sys, "perh_root",
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+ SYS_OFFSET(JH7110_PERH_ROOT), 1,
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+ perh_root_sels, ARRAY_SIZE(perh_root_sels)));
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+
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+ clk_dm(JH7110_BUS_ROOT,
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+ starfive_clk_mux(priv->sys, "bus_root",
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+ SYS_OFFSET(JH7110_BUS_ROOT), 1,
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+ bus_root_sels, ARRAY_SIZE(bus_root_sels)));
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+ clk_dm(JH7110_AXI_CFG0,
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+ starfive_clk_divider(priv->sys,
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+ "axi_cfg0", "bus_root",
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+ SYS_OFFSET(JH7110_AXI_CFG0), 2));
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+ clk_dm(JH7110_STG_AXIAHB,
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+ starfive_clk_divider(priv->sys,
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+ "stg_axiahb", "axi_cfg0",
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+ SYS_OFFSET(JH7110_STG_AXIAHB), 2));
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+ clk_dm(JH7110_AHB0,
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+ starfive_clk_gate(priv->sys,
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+ "ahb0", "stg_axiahb",
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+ SYS_OFFSET(JH7110_AHB0)));
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+ clk_dm(JH7110_AHB1,
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+ starfive_clk_gate(priv->sys,
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+ "ahb1", "stg_axiahb",
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+ SYS_OFFSET(JH7110_AHB1)));
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+ clk_dm(JH7110_APB_BUS_FUNC,
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+ starfive_clk_divider(priv->sys,
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+ "apb_bus_func", "stg_axiahb",
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+ SYS_OFFSET(JH7110_APB_BUS_FUNC), 4));
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+
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+ clk_dm(JH7110_OSC_DIV4,
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+ starfive_clk_divider(priv->aon,
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+ "osc_div4", "osc",
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+ AON_OFFSET(JH7110_OSC_DIV4), 3));
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+ clk_dm(JH7110_AON_APB_FUNC,
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+ starfive_clk_mux(priv->aon, "aon_apb_func",
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+ AON_OFFSET(JH7110_AON_APB_FUNC), 1,
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+ aon_apb_func_sels, ARRAY_SIZE(aon_apb_func_sels)));
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+
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+ clk_dm(JH7110_APB_BUS,
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+ starfive_clk_fix_factor(priv->sys,
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+ "apb_bus", "aon_apb_func", 1, 1));
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+ clk_dm(JH7110_APB0,
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+ starfive_clk_gate(priv->sys,
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+ "apb0", "apb_bus",
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+ SYS_OFFSET(JH7110_APB0)));
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+ clk_dm(JH7110_APB12,
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+ starfive_clk_fix_factor(priv->sys,
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+ "apb12", "apb_bus", 1, 1));
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|
|
+ clk_dm(JH7110_AON_APB,
|
|
|
+ starfive_clk_fix_factor(priv->sys,
|
|
|
+ "aon_apb", "apb_bus_func", 1, 1));
|
|
|
+
|
|
|
+ /*hifi4*/
|
|
|
+ clk_dm(JH7110_HIFI4_CORE,
|
|
|
+ starfive_clk_divider(priv->sys,
|
|
|
+ "hifi4_core", "bus_root",
|
|
|
+ SYS_OFFSET(JH7110_HIFI4_CORE), 4));
|
|
|
+
|
|
|
+ /*QSPI*/
|
|
|
+ clk_dm(JH7110_QSPI_CLK_AHB,
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u0_cdns_qspi_clk_ahb", "ahb1",
|
|
|
+ SYS_OFFSET(JH7110_QSPI_CLK_AHB)));
|
|
|
+ clk_dm(JH7110_QSPI_CLK_APB,
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u0_cdns_qspi_clk_apb", "apb12",
|
|
|
+ SYS_OFFSET(JH7110_QSPI_CLK_APB)));
|
|
|
+ clk_dm(JH7110_QSPI_REF_SRC,
|
|
|
+ starfive_clk_divider(priv->sys,
|
|
|
+ "u0_cdns_qspi_ref_src", "gmacusb_root",
|
|
|
+ SYS_OFFSET(JH7110_QSPI_REF_SRC), 5));
|
|
|
+ clk_dm(JH7110_QSPI_CLK_REF,
|
|
|
+ starfive_clk_composite(priv->sys,
|
|
|
+ "u0_cdns_qspi_clk_ref",
|
|
|
+ qspi_ref_sels, ARRAY_SIZE(qspi_ref_sels),
|
|
|
+ SYS_OFFSET(JH7110_QSPI_CLK_REF), 1, 1, 0));
|
|
|
+
|
|
|
+ /*SDIO*/
|
|
|
+ clk_dm(JH7110_SDIO0_CLK_AHB,
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u0_dw_sdio_clk_ahb", "ahb0",
|
|
|
+ SYS_OFFSET(JH7110_SDIO0_CLK_AHB)));
|
|
|
+ clk_dm(JH7110_SDIO1_CLK_AHB,
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u1_dw_sdio_clk_ahb", "ahb0",
|
|
|
+ SYS_OFFSET(JH7110_SDIO1_CLK_AHB)));
|
|
|
+ clk_dm(JH7110_SDIO0_CLK_SDCARD,
|
|
|
+ starfive_clk_fix_parent_composite(priv->sys,
|
|
|
+ "u0_dw_sdio_clk_sdcard", "axi_cfg0",
|
|
|
+ SYS_OFFSET(JH7110_SDIO0_CLK_SDCARD), 0, 1, 4));
|
|
|
+ clk_dm(JH7110_SDIO1_CLK_SDCARD,
|
|
|
+ starfive_clk_fix_parent_composite(priv->sys,
|
|
|
+ "u1_dw_sdio_clk_sdcard", "axi_cfg0",
|
|
|
+ SYS_OFFSET(JH7110_SDIO1_CLK_SDCARD), 0, 1, 4));
|
|
|
+
|
|
|
+ /*STG*/
|
|
|
+ clk_dm(JH7110_USB_125M,
|
|
|
+ starfive_clk_divider(priv->sys,
|
|
|
+ "usb_125m", "gmacusb_root",
|
|
|
+ SYS_OFFSET(JH7110_USB_125M), 4));
|
|
|
+
|
|
|
+ /*GMAC1*/
|
|
|
+ clk_dm(JH7110_GMAC5_CLK_AHB,
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u1_dw_gmac5_axi64_clk_ahb", "ahb0",
|
|
|
+ SYS_OFFSET(JH7110_GMAC5_CLK_AHB)));
|
|
|
+ clk_dm(JH7110_GMAC5_CLK_AXI,
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u1_dw_gmac5_axi64_clk_axi", "stg_axiahb",
|
|
|
+ SYS_OFFSET(JH7110_GMAC5_CLK_AXI)));
|
|
|
+ clk_dm(JH7110_GMAC_SRC,
|
|
|
+ starfive_clk_divider(priv->sys,
|
|
|
+ "gmac_src", "gmacusb_root",
|
|
|
+ SYS_OFFSET(JH7110_GMAC_SRC), 3));
|
|
|
+ clk_dm(JH7110_GMAC1_GTXCLK,
|
|
|
+ starfive_clk_divider(priv->sys,
|
|
|
+ "gmac1_gtxclk", "gmacusb_root",
|
|
|
+ SYS_OFFSET(JH7110_GMAC1_GTXCLK), 4));
|
|
|
+ clk_dm(JH7110_GMAC1_RMII_RTX,
|
|
|
+ starfive_clk_divider(priv->sys,
|
|
|
+ "gmac1_rmii_rtx", "gmac1_rmii_refin",
|
|
|
+ SYS_OFFSET(JH7110_GMAC1_RMII_RTX), 5));
|
|
|
+ clk_dm(JH7110_GMAC5_CLK_PTP,
|
|
|
+ starfive_clk_gate_divider(priv->sys,
|
|
|
+ "u1_dw_gmac5_axi64_clk_ptp", "gmac_src",
|
|
|
+ SYS_OFFSET(JH7110_GMAC5_CLK_PTP), 5));
|
|
|
+
|
|
|
+ clk_dm(JH7110_GMAC5_CLK_RMII,
|
|
|
+ starfive_clk_fix_factor(priv->sys,
|
|
|
+ "u1_dw_gmac5_axi64_clk_rmii",
|
|
|
+ "gmac1_rmii_refin", 1, 1));
|
|
|
+
|
|
|
+ clk_dm(JH7110_GMAC5_CLK_TX,
|
|
|
+ starfive_clk_composite(priv->sys,
|
|
|
+ "u1_dw_gmac5_axi64_clk_tx",
|
|
|
+ gmac5_tx_sels, ARRAY_SIZE(gmac5_tx_sels),
|
|
|
+ SYS_OFFSET(JH7110_GMAC5_CLK_TX), 1, 1, 0));
|
|
|
+ clk_dm(JH7110_GMAC5_CLK_TX_INV,
|
|
|
+ starfive_clk_gate_dis(priv->sys,
|
|
|
+ "u1_dw_gmac5_axi64_clk_tx_inv",
|
|
|
+ "u1_dw_gmac5_axi64_clk_tx",
|
|
|
+ SYS_OFFSET(JH7110_GMAC5_CLK_TX_INV)));
|
|
|
+ clk_dm(JH7110_GMAC1_GTXC,
|
|
|
+ starfive_clk_gate_divider(priv->sys,
|
|
|
+ "gmac1_gtxc", "gmac1_gtxclk",
|
|
|
+ SYS_OFFSET(JH7110_GMAC1_GTXC), 6));
|
|
|
+
|
|
|
+ /*GMAC0*/
|
|
|
+ clk_dm(JH7110_AON_AHB,
|
|
|
+ starfive_clk_fix_factor(priv->sys, "aon_ahb",
|
|
|
+ "stg_axiahb", 1, 1));
|
|
|
+ clk_dm(JH7110_GMAC0_GTXCLK,
|
|
|
+ starfive_clk_gate_divider(priv->sys, "gmac0_gtxclk",
|
|
|
+ "gmacusb_root", SYS_OFFSET(JH7110_GMAC0_GTXCLK), 4));
|
|
|
+ clk_dm(JH7110_GMAC0_PTP,
|
|
|
+ starfive_clk_gate_divider(priv->sys, "gmac0_ptp",
|
|
|
+ "gmac_src", SYS_OFFSET(JH7110_GMAC0_PTP), 5));
|
|
|
+ clk_dm(JH7110_GMAC_PHY,
|
|
|
+ starfive_clk_gate_divider(priv->sys, "gmac_phy",
|
|
|
+ "gmac_src", SYS_OFFSET(JH7110_GMAC_PHY), 5));
|
|
|
+ clk_dm(JH7110_GMAC0_GTXC,
|
|
|
+ starfive_clk_gate_divider(priv->sys, "gmac0_gtxc",
|
|
|
+ "gmac0_gtxclk", SYS_OFFSET(JH7110_GMAC0_GTXC), 5));
|
|
|
+
|
|
|
+ /*UART0*/
|
|
|
+ clk_dm(JH7110_UART0_CLK_APB,
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u0_dw_uart_clk_apb", "apb0",
|
|
|
+ SYS_OFFSET(JH7110_UART0_CLK_APB)));
|
|
|
+ clk_dm(JH7110_UART0_CLK_CORE,
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u0_dw_uart_clk_core", "osc",
|
|
|
+ SYS_OFFSET(JH7110_UART0_CLK_CORE)));
|
|
|
+
|
|
|
+ /*UART1*/
|
|
|
+ clk_dm(JH7110_UART1_CLK_APB,
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u1_dw_uart_clk_apb", "apb0",
|
|
|
+ SYS_OFFSET(JH7110_UART1_CLK_APB)));
|
|
|
+ clk_dm(JH7110_UART1_CLK_CORE,
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u1_dw_uart_clk_core", "osc",
|
|
|
+ SYS_OFFSET(JH7110_UART1_CLK_CORE)));
|
|
|
+
|
|
|
+ /*UART2*/
|
|
|
+ clk_dm(JH7110_UART2_CLK_APB,
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u2_dw_uart_clk_apb", "apb0",
|
|
|
+ SYS_OFFSET(JH7110_UART2_CLK_APB)));
|
|
|
+ clk_dm(JH7110_UART2_CLK_CORE,
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u2_dw_uart_clk_core", "osc",
|
|
|
+ SYS_OFFSET(JH7110_UART2_CLK_CORE)));
|
|
|
+
|
|
|
+ /*UART3*/
|
|
|
+ clk_dm(JH7110_UART3_CLK_APB,
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u3_dw_uart_clk_apb", "apb0",
|
|
|
+ SYS_OFFSET(JH7110_UART3_CLK_APB)));
|
|
|
+ clk_dm(JH7110_UART3_CLK_CORE,
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u3_dw_uart_clk_core", "perh_root",
|
|
|
+ SYS_OFFSET(JH7110_UART3_CLK_CORE)));
|
|
|
+
|
|
|
+ /*UART4*/
|
|
|
+ clk_dm(JH7110_UART4_CLK_APB,
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u4_dw_uart_clk_apb", "apb0",
|
|
|
+ SYS_OFFSET(JH7110_UART4_CLK_APB)));
|
|
|
+ clk_dm(JH7110_UART4_CLK_CORE,
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u4_dw_uart_clk_core", "perh_root",
|
|
|
+ SYS_OFFSET(JH7110_UART4_CLK_CORE)));
|
|
|
+
|
|
|
+ /*UART5*/
|
|
|
+ clk_dm(JH7110_UART5_CLK_APB,
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u5_dw_uart_clk_apb", "apb0",
|
|
|
+ SYS_OFFSET(JH7110_UART5_CLK_APB)));
|
|
|
+ clk_dm(JH7110_UART5_CLK_CORE,
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u5_dw_uart_clk_core", "perh_root",
|
|
|
+ SYS_OFFSET(JH7110_UART5_CLK_CORE)));
|
|
|
+
|
|
|
+ clk_dm(JH7110_STG_APB,
|
|
|
+ starfive_clk_fix_factor(priv->stg,
|
|
|
+ "stg_apb", "apb_bus", 1, 1));
|
|
|
+
|
|
|
+ clk_dm(JH7110_HIFI4_CLK_CORE,
|
|
|
+ starfive_clk_gate(priv->stg,
|
|
|
+ "u0_hifi4_clk_core", "hifi4_core",
|
|
|
+ STG_OFFSET(JH7110_HIFI4_CLK_CORE)));
|
|
|
+
|
|
|
+ clk_dm(JH7110_USB0_CLK_USB_APB,
|
|
|
+ starfive_clk_gate(priv->stg,
|
|
|
+ "u0_cdn_usb_clk_usb_apb", "stg_apb",
|
|
|
+ STG_OFFSET(JH7110_USB0_CLK_USB_APB)));
|
|
|
+ clk_dm(JH7110_USB0_CLK_UTMI_APB,
|
|
|
+ starfive_clk_gate(priv->stg,
|
|
|
+ "u0_cdn_usb_clk_utmi_apb", "stg_apb",
|
|
|
+ STG_OFFSET(JH7110_USB0_CLK_UTMI_APB)));
|
|
|
+ clk_dm(JH7110_USB0_CLK_AXI,
|
|
|
+ starfive_clk_gate(priv->stg,
|
|
|
+ "u0_cdn_usb_clk_axi", "stg_axiahb",
|
|
|
+ STG_OFFSET(JH7110_USB0_CLK_AXI)));
|
|
|
+ clk_dm(JH7110_USB0_CLK_LPM,
|
|
|
+ starfive_clk_gate_divider(priv->stg,
|
|
|
+ "u0_cdn_usb_clk_lpm", "osc",
|
|
|
+ STG_OFFSET(JH7110_USB0_CLK_LPM), 2));
|
|
|
+ clk_dm(JH7110_USB0_CLK_STB,
|
|
|
+ starfive_clk_gate_divider(priv->stg,
|
|
|
+ "u0_cdn_usb_clk_stb", "osc",
|
|
|
+ STG_OFFSET(JH7110_USB0_CLK_STB), 3));
|
|
|
+ clk_dm(JH7110_USB0_CLK_APP_125,
|
|
|
+ starfive_clk_gate(priv->stg,
|
|
|
+ "u0_cdn_usb_clk_app_125", "usb_125m",
|
|
|
+ STG_OFFSET(JH7110_USB0_CLK_APP_125)));
|
|
|
+ clk_dm(JH7110_USB0_REFCLK,
|
|
|
+ starfive_clk_divider(priv->stg,
|
|
|
+ "u0_cdn_usb_refclk", "osc",
|
|
|
+ STG_OFFSET(JH7110_USB0_REFCLK), 2));
|
|
|
+
|
|
|
+ /*GMAC1*/
|
|
|
+ clk_dm(JH7110_U0_GMAC5_CLK_AHB,
|
|
|
+ starfive_clk_gate(priv->aon,
|
|
|
+ "u0_dw_gmac5_axi64_clk_ahb", "aon_ahb",
|
|
|
+ AON_OFFSET(JH7110_U0_GMAC5_CLK_AHB)));
|
|
|
+ clk_dm(JH7110_U0_GMAC5_CLK_AXI,
|
|
|
+ starfive_clk_gate(priv->aon,
|
|
|
+ "u0_dw_gmac5_axi64_clk_axi", "aon_ahb",
|
|
|
+ AON_OFFSET(JH7110_U0_GMAC5_CLK_AXI)));
|
|
|
+ clk_dm(JH7110_GMAC0_RMII_RTX,
|
|
|
+ starfive_clk_divider(priv->aon,
|
|
|
+ "gmac0_rmii_rtx", "gmac0_rmii_refin",
|
|
|
+ AON_OFFSET(JH7110_GMAC0_RMII_RTX), 5));
|
|
|
+ clk_dm(JH7110_U0_GMAC5_CLK_PTP,
|
|
|
+ starfive_clk_fix_factor(priv->aon,
|
|
|
+ "u0_dw_gmac5_axi64_clk_ptp",
|
|
|
+ "gmac0_ptp", 1, 1));
|
|
|
+ clk_dm(JH7110_U0_GMAC5_CLK_TX,
|
|
|
+ starfive_clk_composite(priv->aon,
|
|
|
+ "u0_dw_gmac5_axi64_clk_tx",
|
|
|
+ u0_dw_gmac5_axi64_clk_tx_sels,
|
|
|
+ ARRAY_SIZE(u0_dw_gmac5_axi64_clk_tx_sels),
|
|
|
+ AON_OFFSET(JH7110_U0_GMAC5_CLK_TX), 1, 1, 0));
|
|
|
+ clk_dm(JH7110_U0_GMAC5_CLK_TX_INV,
|
|
|
+ starfive_clk_gate_dis(priv->aon,
|
|
|
+ "u0_dw_gmac5_axi64_clk_tx_inv",
|
|
|
+ "u0_dw_gmac5_axi64_clk_tx",
|
|
|
+ AON_OFFSET(JH7110_U0_GMAC5_CLK_TX_INV)));
|
|
|
+ clk_dm(JH7110_U0_GMAC5_CLK_RMII,
|
|
|
+ starfive_clk_fix_factor(priv->aon,
|
|
|
+ "u0_dw_gmac5_axi64_clk_rmii",
|
|
|
+ "gmac0_rmii_refin", 1, 1));
|
|
|
+
|
|
|
+ /*otp*/
|
|
|
+ clk_dm(JH7110_OTPC_CLK_APB,
|
|
|
+ starfive_clk_gate(priv->aon,
|
|
|
+ "u0_otpc_clk_apb", "aon_apb",
|
|
|
+ AON_OFFSET(JH7110_OTPC_CLK_APB)));
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int jh7110_clk_probe(struct udevice *dev)
|
|
|
+{
|
|
|
+ struct jh7110_clk_priv *priv = dev_get_priv(dev);
|
|
|
+
|
|
|
+ priv->aon = dev_remap_addr_name(dev, "aon");
|
|
|
+ if (!priv->aon)
|
|
|
+ return -EINVAL;
|
|
|
+
|
|
|
+ priv->sys = dev_remap_addr_name(dev, "sys");
|
|
|
+ if (!priv->sys)
|
|
|
+ return -EINVAL;
|
|
|
+
|
|
|
+ priv->stg = dev_remap_addr_name(dev, "stg");
|
|
|
+ if (!priv->stg)
|
|
|
+ return -EINVAL;
|
|
|
+
|
|
|
+ return jh7110_clk_init(dev);
|
|
|
+}
|
|
|
+
|
|
|
+static const struct udevice_id jh7110_clk_of_match[] = {
|
|
|
+ { .compatible = "starfive,jh7110-clkgen" },
|
|
|
+ { }
|
|
|
+};
|
|
|
+
|
|
|
+U_BOOT_DRIVER(jh7110_clk) = {
|
|
|
+ .name = "jh7110_clk",
|
|
|
+ .id = UCLASS_CLK,
|
|
|
+ .of_match = jh7110_clk_of_match,
|
|
|
+ .probe = jh7110_clk_probe,
|
|
|
+ .ops = &starfive_clk_ops,
|
|
|
+ .priv_auto = sizeof(struct jh7110_clk_priv),
|
|
|
+ .flags = DM_FLAG_PRE_RELOC,
|
|
|
+};
|
|
|
+
|