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@@ -12,9 +12,7 @@
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* MX7ULP WDOG Register Map
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*/
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struct wdog_regs {
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- u8 cs1;
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- u8 cs2;
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- u16 reserve0;
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+ u32 cs;
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u32 cnt;
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u32 toval;
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u32 win;
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@@ -30,10 +28,12 @@ struct wdog_regs {
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#define UNLOCK_WORD0 0xC520 /* 1st unlock word */
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#define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
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-#define WDGCS1_WDGE (1<<7)
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-#define WDGCS1_WDGUPDATE (1<<5)
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+#define WDGCS_WDGE BIT(7)
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+#define WDGCS_WDGUPDATE BIT(5)
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-#define WDGCS2_FLG (1<<6)
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+#define WDGCS_RCS BIT(10)
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+#define WDGCS_ULK BIT(11)
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+#define WDGCS_FLG BIT(14)
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#define WDG_BUS_CLK (0x0)
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#define WDG_LPO_CLK (0x1)
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@@ -60,7 +60,6 @@ void hw_watchdog_reset(void)
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void hw_watchdog_init(void)
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{
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- u8 val;
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
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dmb();
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@@ -68,15 +67,19 @@ void hw_watchdog_init(void)
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__raw_writel(UNLOCK_WORD1, &wdog->cnt);
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dmb();
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- val = readb(&wdog->cs2);
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- val |= WDGCS2_FLG;
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- writeb(val, &wdog->cs2);
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+ /* Wait WDOG Unlock */
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+ while (!(readl(&wdog->cs) & WDGCS_ULK))
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+ ;
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hw_watchdog_set_timeout(CONFIG_WATCHDOG_TIMEOUT_MSECS);
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writel(0, &wdog->win);
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- writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */
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- writeb((WDGCS1_WDGE | WDGCS1_WDGUPDATE), &wdog->cs1);/* enable counter running */
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+ /* setting 1-kHz clock source, enable counter running, and clear interrupt */
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+ writel((WDGCS_WDGE | WDGCS_WDGUPDATE |(WDG_LPO_CLK << 8) | WDGCS_FLG), &wdog->cs);
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+
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+ /* Wait WDOG reconfiguration */
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+ while (!(readl(&wdog->cs) & WDGCS_RCS))
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+ ;
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hw_watchdog_reset();
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}
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@@ -90,11 +93,19 @@ void reset_cpu(void)
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__raw_writel(UNLOCK_WORD1, &wdog->cnt);
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dmb();
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+ /* Wait WDOG Unlock */
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+ while (!(readl(&wdog->cs) & WDGCS_ULK))
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+ ;
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+
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hw_watchdog_set_timeout(5); /* 5ms timeout */
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writel(0, &wdog->win);
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- writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */
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- writeb(WDGCS1_WDGE, &wdog->cs1);/* enable counter running */
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+ /* enable counter running */
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+ writel((WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs);
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+
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+ /* Wait WDOG reconfiguration */
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+ while (!(readl(&wdog->cs) & WDGCS_RCS))
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+ ;
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hw_watchdog_reset();
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