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@@ -0,0 +1,208 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * Copyright (C) 2022 Starfive, Inc.
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+ * Author: yanhong <yanhong.wang@starfivetech.com>
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+ *
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+ */
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+
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+#include <common.h>
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+#include <asm/io.h>
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+#include <asm/arch/jh7110-regs.h>
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+#include <cpu_func.h>
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+#include <dm/uclass.h>
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+#include <dm/device.h>
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+#include <env.h>
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+#include <inttypes.h>
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+#include <misc.h>
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+#include <linux/bitops.h>
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+#include <asm/arch/gpio.h>
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+
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+#define SYS_IOMUX_DOEN(gpio, oen) \
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+ clrsetbits_le32(SYS_IOMUX_BASE+GPIO_OFFSET(gpio), \
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+ GPIO_DOEN_MASK << GPIO_SHIFT(gpio), \
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+ (oen) << GPIO_SHIFT(gpio))
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+
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+#define SYS_IOMUX_DOUT(gpio, gpo) \
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+ clrsetbits_le32(SYS_IOMUX_BASE + GPIO_DOUT + GPIO_OFFSET(gpio),\
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+ GPIO_DOUT_MASK << GPIO_SHIFT(gpio),\
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+ ((gpo) & GPIO_DOUT_MASK) << GPIO_SHIFT(gpio))
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+
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+#define SYS_IOMUX_DIN(gpio, gpi)\
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+ clrsetbits_le32(SYS_IOMUX_BASE + GPIO_DIN + GPIO_OFFSET(gpi),\
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+ GPIO_DIN_MASK << GPIO_SHIFT(gpi),\
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+ ((gpio+2) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi))
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+
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+#define SYS_IOMUX_COMPLEX(gpio, gpi, gpo, oen) do {\
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+ SYS_IOMUX_DOEN(gpio, oen);\
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+ SYS_IOMUX_DOUT(gpio, gpo);\
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+ SYS_IOMUX_DIN(gpio, gpi); \
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+ } while (0)
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+
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+#define SYS_CLOCK_ENABLE(clk) \
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+ setbits_le32(SYS_CRG_BASE + clk, CLK_ENABLE_MASK)
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+
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+static void sys_reset_clear(ulong assert, ulong status, u32 rst)
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+{
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+ u32 value;
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+
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+ clrbits_le32(SYS_CRG_BASE + assert, BIT(rst));
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+ do {
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+ value = in_le32(SYS_CRG_BASE + status);
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+ } while ((value & BIT(rst)) != BIT(rst));
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+}
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+
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+static void jh7110_timer_init(void)
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+{
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+ SYS_CLOCK_ENABLE(TIMER_CLK_APB_SHIFT);
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+ SYS_CLOCK_ENABLE(TIMER_CLK_TIMER0_SHIFT);
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+ SYS_CLOCK_ENABLE(TIMER_CLK_TIMER1_SHIFT);
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+ SYS_CLOCK_ENABLE(TIMER_CLK_TIMER2_SHIFT);
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+ SYS_CLOCK_ENABLE(TIMER_CLK_TIMER3_SHIFT);
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+
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+ sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
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+ SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_APB_SHIFT);
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+ sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
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+ SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER0_SHIFT);
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+ sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
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+ SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER1_SHIFT);
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+ sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
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+ SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER2_SHIFT);
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+ sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
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+ SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER3_SHIFT);
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+}
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+
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+static void jh7110_gmac_init(int id)
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+{
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+ switch (id) {
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+ case 0:
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+ clrsetbits_le32(AON_SYSCON_BASE + AON_SYSCFG_12,
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+ GMAC5_0_SEL_I_MASK,
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+ BIT(GMAC5_0_SEL_I_SHIFT) & GMAC5_0_SEL_I_MASK);
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+ break;
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+
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+ case 1:
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+ clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_144,
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+ GMAC5_1_SEL_I_MASK,
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+ BIT(GMAC5_1_SEL_I_SHIFT) & GMAC5_1_SEL_I_MASK);
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+ break;
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+
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+ default:
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+ break;
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+ }
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+}
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+
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+static void jh7110_usb_init(void)
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+{
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+ clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
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+ USB_MODE_STRAP_MASK,
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+ (2<<USB_MODE_STRAP_SHIFT) & USB_MODE_STRAP_MASK);
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+ clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
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+ USB_OTG_SUSPENDM_BYPS_MASK,
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+ BIT(USB_OTG_SUSPENDM_BYPS_SHIFT)
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+ & USB_OTG_SUSPENDM_BYPS_MASK);
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+
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+ clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
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+ USB_OTG_SUSPENDM_MASK,
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+ BIT(USB_OTG_SUSPENDM_SHIFT) & USB_OTG_SUSPENDM_MASK);
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+ clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
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+ USB_PLL_EN_MASK,
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+ BIT(USB_PLL_EN_SHIFT) & USB_PLL_EN_MASK);
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+ clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
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+ USB_REFCLK_MODE_MASK,
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+ BIT(USB_REFCLK_MODE_SHIFT) & USB_REFCLK_MODE_MASK);
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+
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+ clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24,
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+ PDRSTN_SPLIT_MASK,
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+ BIT(PDRSTN_SPLIT_SHIFT) & PDRSTN_SPLIT_MASK);
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+ clrsetbits_le32(SYS_IOMUX_BASE + SYS_IOMUX_32,
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+ IOMUX_USB_MASK,
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+ BIT(IOMUX_USB_SHIFT) & IOMUX_USB_MASK);
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+}
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+
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+static void jh7110_mmc_init(int id)
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+{
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+ if (id == 0) {
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+ SYS_IOMUX_DOEN(62, LOW);
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+ SYS_IOMUX_DOUT(62, 19);
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+ } else {
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+ SYS_IOMUX_DOEN(10, LOW);
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+ SYS_IOMUX_DOUT(10, 55);
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+ SYS_IOMUX_COMPLEX(9, 44, 57, 19);
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+ SYS_IOMUX_COMPLEX(11, 45, 58, 20);
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+ SYS_IOMUX_COMPLEX(12, 46, 59, 21);
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+ SYS_IOMUX_COMPLEX(7, 47, 60, 22);
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+ SYS_IOMUX_COMPLEX(8, 48, 61, 23);
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+ }
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+}
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+
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+/*enable U74-mc hart1~hart4 prefetcher*/
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+static void enable_prefetcher(void)
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+{
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+ u32 hart;
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+ u32 *reg;
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+#define L2_PREFETCHER_BASE_ADDR 0x2030000
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+#define L2_PREFETCHER_OFFSET 0x2000
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+
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+ /*hart1~hart4*/
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+ for (hart = 1; hart < 5; hart++) {
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+ reg = (u32 *)((u64)(L2_PREFETCHER_BASE_ADDR
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+ + hart*L2_PREFETCHER_OFFSET));
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+
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+ mb(); /* memory barrier */
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+ setbits_le32(reg, 0x1);
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+ mb(); /* memory barrier */
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+ }
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+}
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+
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+int board_init(void)
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+{
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+ enable_caches();
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+
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+ /*enable hart1-hart4 prefetcher*/
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+// enable_prefetcher();
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+
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+ jh7110_gmac_init(0);
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+ jh7110_gmac_init(1);
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+ jh7110_timer_init();
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+
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+ jh7110_usb_init();
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+
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+ jh7110_mmc_init(0);
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+ jh7110_mmc_init(1);
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+
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+ return 0;
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+}
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+
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+#ifdef CONFIG_MISC_INIT_R
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+
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+int misc_init_r(void)
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+{
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+ char mac[6] = {0x66, 0x34, 0xb0, 0x6c, 0xde, 0xad };
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+
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+#if CONFIG_IS_ENABLED(STARFIVE_OTP)
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+ struct udevice *dev;
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+ char buf[8];
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+ int ret;
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+#define MACADDR_OFFSET 0x8
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+
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+ ret = uclass_get_device_by_driver(UCLASS_MISC,
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+ DM_DRIVER_GET(starfive_otp), &dev);
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+ if (ret) {
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+ debug("%s: could not find otp device\n", __func__);
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+ goto err;
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+ }
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+
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+ ret = misc_read(dev, MACADDR_OFFSET, buf, sizeof(buf));
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+ if (ret)
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+ printf("%s: error reading mac from OTP\n", __func__);
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+ else
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+ if (buf[0] != 0xff)
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+ memcpy(mac, buf, 6);
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+err:
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+#endif
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+ eth_env_set_enetaddr("ethaddr", mac);
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+
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+ return 0;
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+}
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+#endif
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+
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