jh7110-u-boot.dtsi 1.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118
  1. // SPDX-License-Identifier: GPL-2.0 OR MIT
  2. /*
  3. * Copyright (C) 2022 StarFive Technology Co., Ltd.
  4. */
  5. #include <dt-bindings/reset/starfive-jh7110.h>
  6. #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
  7. / {
  8. cpus: cpus {
  9. u-boot,dm-spl;
  10. timebase-frequency = <4000000>;
  11. cpu0: cpu@0 {
  12. u-boot,dm-spl;
  13. status = "okay";
  14. cpu0intctrl: interrupt-controller {
  15. u-boot,dm-spl;
  16. };
  17. };
  18. cpu1: cpu@1 {
  19. u-boot,dm-spl;
  20. status = "okay";
  21. cpu1intctrl: interrupt-controller {
  22. u-boot,dm-spl;
  23. };
  24. };
  25. cpu2: cpu@2 {
  26. u-boot,dm-spl;
  27. status = "okay";
  28. cpu2intctrl: interrupt-controller {
  29. u-boot,dm-spl;
  30. };
  31. };
  32. cpu3: cpu@3 {
  33. u-boot,dm-spl;
  34. status = "okay";
  35. cpu3intctrl: interrupt-controller {
  36. u-boot,dm-spl;
  37. };
  38. };
  39. cpu4: cpu@4 {
  40. u-boot,dm-spl;
  41. status = "okay";
  42. cpu4intctrl: interrupt-controller {
  43. u-boot,dm-spl;
  44. };
  45. };
  46. };
  47. soc {
  48. u-boot,dm-spl;
  49. clint: clint@2000000 {
  50. u-boot,dm-spl;
  51. };
  52. };
  53. };
  54. &uart0 {
  55. clock-frequency = <24000000>;
  56. current-speed = <115200>;
  57. status = "okay";
  58. u-boot,dm-spl;
  59. };
  60. &sdio0 {
  61. clock-frequency = <4000000>;
  62. max-frequency = <1000000>;
  63. bus-width = <8>;
  64. status = "okay";
  65. u-boot,dm-spl;
  66. };
  67. &sdio1 {
  68. clock-frequency = <4000000>;
  69. max-frequency = <1000000>;
  70. bus-width = <4>;
  71. status = "okay";
  72. u-boot,dm-spl;
  73. };
  74. &qspi {
  75. status = "okay";
  76. u-boot,dm-spl;
  77. };
  78. &rstgen {
  79. status = "okay";
  80. u-boot,dm-spl;
  81. };
  82. &nor_flash {
  83. u-boot,dm-spl;
  84. };
  85. &clkgen {
  86. u-boot,dm-spl;
  87. };
  88. &osc {
  89. u-boot,dm-spl;
  90. };
  91. &gmac1_rmii_refin{
  92. u-boot,dm-spl;
  93. };
  94. &stg_apb {
  95. u-boot,dm-spl;
  96. };
  97. &gmac0_rmii_refin {
  98. u-boot,dm-spl;
  99. };