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@@ -0,0 +1,421 @@
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+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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+/* Copyright (c) 2020 Microchip Technology Inc */
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+
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+/dts-v1/;
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+#include "dt-bindings/clock/microchip-mpfs-clock.h"
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+
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+/* Clock frequency (in Hz) of the rtcclk */
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+#define RTCCLK_FREQ 1000000
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+
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+/ {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ model = "Microchip MPFS Icicle Kit";
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+ compatible = "microchip,mpfs-icicle-kit";
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+
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+ aliases {
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+ serial0 = &uart0;
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+ ethernet0 = &emac1;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial0";
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+ };
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+
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+ cpucomplex: cpus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ timebase-frequency = <RTCCLK_FREQ>;
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+ cpu0: cpu@0 {
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+ clocks = <&clkcfg CLK_CPU>;
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+ compatible = "sifive,e51", "sifive,rocket0", "riscv";
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+ device_type = "cpu";
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+ i-cache-block-size = <64>;
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+ i-cache-sets = <128>;
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+ i-cache-size = <16384>;
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+ reg = <0>;
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+ riscv,isa = "rv64imac";
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+ status = "disabled";
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+ operating-points = <
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+ /* kHz uV */
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+ 600000 1100000
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+ 300000 950000
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+ 150000 750000
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+ >;
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+ cpu0intc: interrupt-controller {
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+ #interrupt-cells = <1>;
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+ compatible = "riscv,cpu-intc";
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+ interrupt-controller;
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+ };
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+ };
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+ cpu1: cpu@1 {
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+ clocks = <&clkcfg CLK_CPU>;
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+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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+ d-cache-block-size = <64>;
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+ d-cache-sets = <64>;
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+ d-cache-size = <32768>;
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+ d-tlb-sets = <1>;
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+ d-tlb-size = <32>;
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+ device_type = "cpu";
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+ i-cache-block-size = <64>;
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+ i-cache-sets = <64>;
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+ i-cache-size = <32768>;
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+ i-tlb-sets = <1>;
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+ i-tlb-size = <32>;
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+ mmu-type = "riscv,sv39";
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+ reg = <1>;
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+ riscv,isa = "rv64imafdc";
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+ tlb-split;
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+ status = "okay";
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+ operating-points = <
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+ /* kHz uV */
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+ 600000 1100000
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+ 300000 950000
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+ 150000 750000
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+ >;
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+ cpu1intc: interrupt-controller {
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+ #interrupt-cells = <1>;
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+ compatible = "riscv,cpu-intc";
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+ interrupt-controller;
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+ };
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+ };
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+ cpu2: cpu@2 {
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+ clocks = <&clkcfg CLK_CPU>;
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+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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+ d-cache-block-size = <64>;
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+ d-cache-sets = <64>;
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+ d-cache-size = <32768>;
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+ d-tlb-sets = <1>;
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+ d-tlb-size = <32>;
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+ device_type = "cpu";
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+ i-cache-block-size = <64>;
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+ i-cache-sets = <64>;
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+ i-cache-size = <32768>;
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+ i-tlb-sets = <1>;
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+ i-tlb-size = <32>;
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+ mmu-type = "riscv,sv39";
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+ reg = <2>;
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+ riscv,isa = "rv64imafdc";
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+ tlb-split;
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+ status = "okay";
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+ operating-points = <
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+ /* kHz uV */
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+ 600000 1100000
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+ 300000 950000
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+ 150000 750000
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+ >;
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+ cpu2intc: interrupt-controller {
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+ #interrupt-cells = <1>;
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+ compatible = "riscv,cpu-intc";
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+ interrupt-controller;
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+ };
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+ };
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+ cpu3: cpu@3 {
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+ clocks = <&clkcfg CLK_CPU>;
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+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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+ d-cache-block-size = <64>;
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+ d-cache-sets = <64>;
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+ d-cache-size = <32768>;
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+ d-tlb-sets = <1>;
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+ d-tlb-size = <32>;
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+ device_type = "cpu";
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+ i-cache-block-size = <64>;
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+ i-cache-sets = <64>;
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+ i-cache-size = <32768>;
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+ i-tlb-sets = <1>;
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+ i-tlb-size = <32>;
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+ mmu-type = "riscv,sv39";
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+ reg = <3>;
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+ riscv,isa = "rv64imafdc";
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+ tlb-split;
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+ status = "okay";
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+ operating-points = <
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+ /* kHz uV */
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+ 600000 1100000
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+ 300000 950000
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+ 150000 750000
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+ >;
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+ cpu3intc: interrupt-controller {
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+ #interrupt-cells = <1>;
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+ compatible = "riscv,cpu-intc";
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+ interrupt-controller;
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+ };
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+ };
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+ cpu4: cpu@4 {
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+ clocks = <&clkcfg CLK_CPU>;
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+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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+ d-cache-block-size = <64>;
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+ d-cache-sets = <64>;
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+ d-cache-size = <32768>;
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+ d-tlb-sets = <1>;
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+ d-tlb-size = <32>;
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+ device_type = "cpu";
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+ i-cache-block-size = <64>;
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+ i-cache-sets = <64>;
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+ i-cache-size = <32768>;
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+ i-tlb-sets = <1>;
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+ i-tlb-size = <32>;
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+ mmu-type = "riscv,sv39";
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+ reg = <4>;
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+ riscv,isa = "rv64imafdc";
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+ tlb-split;
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+ status = "okay";
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+ operating-points = <
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+ /* kHz uV */
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+ 600000 1100000
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+ 300000 950000
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+ 150000 750000
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+ >;
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+ cpu4intc: interrupt-controller {
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+ #interrupt-cells = <1>;
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+ compatible = "riscv,cpu-intc";
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+ interrupt-controller;
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+ };
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+ };
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+ };
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+ refclk: refclk {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <600000000>;
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+ clock-output-names = "msspllclk";
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+ };
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+ ddr: memory@80000000 {
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+ device_type = "memory";
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+ reg = <0x0 0x80000000 0x0 0x40000000>;
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+ clocks = <&clkcfg CLK_DDRC>;
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+ };
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+ soc: soc {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ compatible = "microchip,mpfs-icicle-kit", "simple-bus";
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+ ranges;
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+ clint0: clint@2000000 {
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+ compatible = "riscv,clint0";
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+ interrupts-extended = <&cpu0intc 3 &cpu0intc 7
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+ &cpu1intc 3 &cpu1intc 7
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+ &cpu2intc 3 &cpu2intc 7
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+ &cpu3intc 3 &cpu3intc 7
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+ &cpu4intc 3 &cpu4intc 7>;
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+ reg = <0x0 0x2000000 0x0 0x10000>;
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+ reg-names = "control";
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+ clock-frequency = <RTCCLK_FREQ>;
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+ };
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+ cachecontroller: cache-controller@2010000 {
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+ compatible = "sifive,fu540-c000-ccache", "cache";
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+ cache-block-size = <64>;
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+ cache-level = <2>;
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+ cache-sets = <1024>;
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+ cache-size = <2097152>;
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+ cache-unified;
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+ interrupt-parent = <&plic>;
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+ interrupts = <1 2 3>;
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+ reg = <0x0 0x2010000 0x0 0x1000>;
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+ };
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+ plic: interrupt-controller@c000000 {
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+ #interrupt-cells = <1>;
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+ compatible = "sifive,plic-1.0.0";
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+ reg = <0x0 0xc000000 0x0 0x4000000>;
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+ riscv,max-priority = <7>;
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+ riscv,ndev = <186>;
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+ interrupt-controller;
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+ interrupts-extended = <
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+ &cpu0intc 11
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+ &cpu1intc 11 &cpu1intc 9
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+ &cpu2intc 11 &cpu2intc 9
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+ &cpu3intc 11 &cpu3intc 9
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+ &cpu4intc 11 &cpu4intc 9>;
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+ };
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+ uart0: serial@20000000 {
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+ compatible = "ns16550a";
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+ reg = <0x0 0x20000000 0x0 0x400>;
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+ reg-io-width = <4>;
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+ reg-shift = <2>;
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+ interrupt-parent = <&plic>;
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+ interrupts = <90>;
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+ clock-frequency = <150000000>;
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+ clocks = <&clkcfg CLK_MMUART0>;
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+ status = "okay";
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+ };
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+ clkcfg: clkcfg@20002000 {
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+ compatible = "microchip,mpfs-clkcfg";
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+ reg = <0x0 0x20002000 0x0 0x1000>;
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+ reg-names = "mss_sysreg";
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+ clocks = <&refclk>;
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+ #clock-cells = <1>;
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+ clock-output-names = "cpu", "axi", "ahb", "envm",
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+ "mac0", "mac1", "mmc", "timer",
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+ "mmuart0", "mmuart1", "mmuart2",
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+ "mmuart3", "mmuart4", "spi0", "spi1",
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+ "i2c0", "i2c1", "can0", "can1", "usb",
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+ "reserved", "rtc", "qspi", "gpio0",
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+ "gpio1", "gpio2", "ddrc", "fic0",
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+ "fic1", "fic2", "fic3", "athena",
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+ "cfm";
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+ };
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+ emmc: mmc@20008000 {
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+ compatible = "cdns,sd4hc";
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+ reg = <0x0 0x20008000 0x0 0x1000>;
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+ interrupt-parent = <&plic>;
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+ interrupts = <88 89>;
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+ pinctrl-names = "default";
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+ clocks = <&clkcfg CLK_MMC>;
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+ bus-width = <4>;
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+ cap-mmc-highspeed;
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+ mmc-ddr-3_3v;
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+ max-frequency = <200000000>;
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+ non-removable;
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+ no-sd;
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+ no-sdio;
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+ voltage-ranges = <3300 3300>;
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+ status = "okay";
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+ };
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+ sdcard: sd@20008000 {
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+ compatible = "cdns,sd4hc";
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+ reg = <0x0 0x20008000 0x0 0x1000>;
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+ interrupt-parent = <&plic>;
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+ interrupts = <88>;
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+ pinctrl-names = "default";
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+ clocks = <&clkcfg CLK_MMC>;
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+ bus-width = <4>;
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+ disable-wp;
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+ cap-sd-highspeed;
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+ card-detect-delay = <200>;
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+ sd-uhs-sdr12;
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+ sd-uhs-sdr25;
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+ sd-uhs-sdr50;
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+ sd-uhs-sdr104;
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+ max-frequency = <200000000>;
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+ status = "disabled";
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+ };
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+ uart1: serial@20100000 {
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+ compatible = "ns16550a";
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+ reg = <0x0 0x20100000 0x0 0x400>;
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+ reg-io-width = <4>;
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+ reg-shift = <2>;
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+ interrupt-parent = <&plic>;
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+ interrupts = <91>;
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+ clock-frequency = <150000000>;
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+ clocks = <&clkcfg CLK_MMUART1>;
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+ status = "okay";
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+ };
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+ uart2: serial@20102000 {
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+ compatible = "ns16550a";
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+ reg = <0x0 0x20102000 0x0 0x400>;
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+ reg-io-width = <4>;
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+ reg-shift = <2>;
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+ interrupt-parent = <&plic>;
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+ interrupts = <92>;
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+ clock-frequency = <150000000>;
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+ clocks = <&clkcfg CLK_MMUART2>;
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+ status = "okay";
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+ };
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+ uart3: serial@20104000 {
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+ compatible = "ns16550a";
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+ reg = <0x0 0x20104000 0x0 0x400>;
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+ reg-io-width = <4>;
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+ reg-shift = <2>;
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+ interrupt-parent = <&plic>;
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+ interrupts = <93>;
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+ clock-frequency = <150000000>;
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+ clocks = <&clkcfg CLK_MMUART3>;
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+ status = "okay";
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+ };
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+ i2c0: i2c@2010a000 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "microchip,mpfs-mss-i2c";
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+ reg = <0x0 0x2010a000 0x0 0x1000>;
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+ interrupt-parent = <&plic>;
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+ interrupts = <58>;
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+ clocks = <&clkcfg CLK_I2C0>;
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+ status = "disabled";
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+ };
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+ i2c1: i2c@2010b000 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "microchip,mpfs-mss-i2c";
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+ reg = <0x0 0x2010b000 0x0 0x1000>;
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+ interrupt-parent = <&plic>;
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+ interrupts = <61>;
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+ clocks = <&clkcfg CLK_I2C1>;
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+ status = "disabled";
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+ pac193x@10 {
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+ compatible = "microchip,pac1934";
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+ reg = <0x10>;
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+ samp-rate = <64>;
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+ status = "disabled";
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+ ch1: channel0 {
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+ uohms-shunt-res = <10000>;
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+ rail-name = "VDD";
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+ channel_enabled;
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+ };
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+ ch2: channel1 {
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+ uohms-shunt-res = <10000>;
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+ rail-name = "VDDA25";
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+ channel_enabled;
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+ };
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+ ch3: channel2 {
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+ uohms-shunt-res = <10000>;
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+ rail-name = "VDD25";
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+ channel_enabled;
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+ };
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+ ch4: channel3 {
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+ uohms-shunt-res = <10000>;
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+ rail-name = "VDDA";
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+ channel_enabled;
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+ };
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+ };
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+ };
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+ emac0: ethernet@20110000 {
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+ compatible = "microchip,mpfs-mss-gem";
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+ reg = <0x0 0x20110000 0x0 0x2000>;
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+ interrupt-parent = <&plic>;
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+ interrupts = <64 65 66 67>;
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+ local-mac-address = [56 34 00 FC 00 02];
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+ phy-mode = "sgmii";
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+ clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AXI>;
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+ clock-names = "pclk", "hclk";
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+ status = "disabled";
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+
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ phy-handle = <&phy0>;
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+ phy0: ethernet-phy@8 {
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+ reg = <8>;
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+ ti,fifo-depth = <0x01>;
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+ };
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+ };
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+ emac1: ethernet@20112000 {
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+ compatible = "microchip,mpfs-mss-gem";
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+ reg = <0x0 0x20112000 0x0 0x2000>;
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+ interrupt-parent = <&plic>;
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+ interrupts = <70 71 72 73>;
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+ local-mac-address = [00 00 00 00 00 00];
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+ phy-mode = "sgmii";
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+ clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
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+ clock-names = "pclk", "hclk";
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+ status = "okay";
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+
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+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ phy-handle = <&phy1>;
|
|
|
+ phy1: ethernet-phy@9 {
|
|
|
+ reg = <9>;
|
|
|
+ ti,fifo-depth = <0x01>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ gpio: gpio@20122000 {
|
|
|
+ compatible = "microchip,mpfs-mss-gpio";
|
|
|
+ interrupt-parent = <&plic>;
|
|
|
+ interrupts = <13 14 15 16 17 18 19 20 21 22 23 24 25 26
|
|
|
+ 27 28 29 30 31 32 33 34 35 36 37 38 39
|
|
|
+ 40 41 42 43 44>;
|
|
|
+ gpio-controller;
|
|
|
+ clocks = <&clkcfg CLK_GPIO2>;
|
|
|
+ reg = <0x00 0x20122000 0x0 0x1000>;
|
|
|
+ reg-names = "control";
|
|
|
+ #gpio-cells = <2>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+ };
|
|
|
+};
|