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@@ -0,0 +1,187 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * Copyright (C) 2020 Microchip Technology Inc.
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+ * Padmarao Begari <padmarao.begari@microchip.com>
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+ */
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+#include <common.h>
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+#include <clk.h>
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+#include <clk-uclass.h>
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+#include <asm/io.h>
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+#include <dm/device.h>
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+#include <dm/devres.h>
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+#include <dm/uclass.h>
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+#include <dt-bindings/clock/microchip-mpfs-clock.h>
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+#include <linux/err.h>
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+
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+#include "mpfs_clk.h"
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+
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+#define MPFS_PERIPH_CLOCK "mpfs_periph_clock"
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+
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+#define REG_CLOCK_CONFIG_CR 0x08
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+#define REG_SUBBLK_CLOCK_CR 0x84
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+#define REG_SUBBLK_RESET_CR 0x88
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+
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+#define CFG_CPU_SHIFT 0x0
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+#define CFG_AXI_SHIFT 0x2
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+#define CFG_AHB_SHIFT 0x4
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+#define CFG_WIDTH 0x2
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+
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+/**
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+ * struct mpfs_periph_clock - per instance of peripheral clock
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+ * @id: index of a peripheral clock
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+ * @name: name of a peripheral clock
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+ * @shift: shift to a peripheral clock bit field
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+ * @flags: common clock framework flags
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+ */
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+struct mpfs_periph_clock {
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+ unsigned int id;
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+ const char *name;
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+ u8 shift;
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+ unsigned long flags;
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+};
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+
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+/**
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+ * struct mpfs_periph_hw_clock - hardware peripheral clock
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+ * @periph: peripheral clock instance
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+ * @sys_base: base address of the mpfs system register
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+ * @prate: the pll clock rate
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+ * @hw: clock instance
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+ */
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+struct mpfs_periph_hw_clock {
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+ struct mpfs_periph_clock periph;
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+ void __iomem *sys_base;
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+ u32 prate;
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+ struct clk hw;
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+};
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+
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+#define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_clock, hw)
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+
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+static int mpfs_periph_clk_enable(struct clk *hw)
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+{
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+ struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
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+ struct mpfs_periph_clock *periph = &periph_hw->periph;
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+ void __iomem *base_addr = periph_hw->sys_base;
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+ u32 reg, val;
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+
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+ if (periph->flags != CLK_IS_CRITICAL) {
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+ reg = readl(base_addr + REG_SUBBLK_RESET_CR);
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+ val = reg & ~(1u << periph->shift);
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+ writel(val, base_addr + REG_SUBBLK_RESET_CR);
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+
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+ reg = readl(base_addr + REG_SUBBLK_CLOCK_CR);
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+ val = reg | (1u << periph->shift);
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+ writel(val, base_addr + REG_SUBBLK_CLOCK_CR);
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+ }
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+
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+ return 0;
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+}
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+
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+static int mpfs_periph_clk_disable(struct clk *hw)
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+{
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+ struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
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+ struct mpfs_periph_clock *periph = &periph_hw->periph;
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+ void __iomem *base_addr = periph_hw->sys_base;
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+ u32 reg, val;
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+
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+ if (periph->flags != CLK_IS_CRITICAL) {
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+ reg = readl(base_addr + REG_SUBBLK_RESET_CR);
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+ val = reg | (1u << periph->shift);
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+ writel(val, base_addr + REG_SUBBLK_RESET_CR);
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+
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+ reg = readl(base_addr + REG_SUBBLK_CLOCK_CR);
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+ val = reg & ~(1u << periph->shift);
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+ writel(val, base_addr + REG_SUBBLK_CLOCK_CR);
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+ }
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+
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+ return 0;
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+}
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+
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+static ulong mpfs_periph_clk_recalc_rate(struct clk *hw)
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+{
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+ struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
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+ void __iomem *base_addr = periph_hw->sys_base;
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+ unsigned long rate;
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+ u32 val;
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+
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+ val = readl(base_addr + REG_CLOCK_CONFIG_CR) >> CFG_AHB_SHIFT;
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+ val &= clk_div_mask(CFG_WIDTH);
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+ rate = periph_hw->prate / (1u << val);
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+ hw->rate = rate;
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+
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+ return rate;
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+}
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+
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+#define CLK_PERIPH(_id, _name, _shift, _flags) { \
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+ .periph.id = _id, \
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+ .periph.name = _name, \
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+ .periph.shift = _shift, \
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+ .periph.flags = _flags, \
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+ }
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+
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+static struct mpfs_periph_hw_clock mpfs_periph_clks[] = {
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+ CLK_PERIPH(CLK_ENVM, "clk_periph_envm", 0, CLK_IS_CRITICAL),
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+ CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", 1, 0),
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+ CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", 2, 0),
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+ CLK_PERIPH(CLK_MMC, "clk_periph_mmc", 3, 0),
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+ CLK_PERIPH(CLK_TIMER, "clk_periph_timer", 4, 0),
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+ CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", 5, 0),
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+ CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", 6, 0),
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+ CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", 7, 0),
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+ CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", 8, 0),
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+ CLK_PERIPH(CLK_MMUART4, "clk_periph_mmuart4", 9, 0),
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+ CLK_PERIPH(CLK_SPI0, "clk_periph_spi0", 10, 0),
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+ CLK_PERIPH(CLK_SPI1, "clk_periph_spi1", 11, 0),
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+ CLK_PERIPH(CLK_I2C0, "clk_periph_i2c0", 12, 0),
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+ CLK_PERIPH(CLK_I2C1, "clk_periph_i2c1", 13, 0),
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+ CLK_PERIPH(CLK_CAN0, "clk_periph_can0", 14, 0),
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+ CLK_PERIPH(CLK_CAN1, "clk_periph_can1", 15, 0),
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+ CLK_PERIPH(CLK_USB, "clk_periph_usb", 16, 0),
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+ CLK_PERIPH(CLK_RTC, "clk_periph_rtc", 18, 0),
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+ CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", 19, 0),
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+ CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", 20, 0),
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+ CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", 21, 0),
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+ CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", 22, 0),
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+ CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", 23, CLK_IS_CRITICAL),
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+ CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", 24, 0),
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+ CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", 25, 0),
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+ CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", 26, 0),
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+ CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", 27, 0),
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+ CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", 28, 0),
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+ CLK_PERIPH(CLK_CFM, "clk_periph_cfm", 29, 0),
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+};
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+
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+int mpfs_clk_register_periphs(void __iomem *base, u32 clk_rate,
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+ const char *parent_name)
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+{
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+ int ret;
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+ int i, id, num_clks;
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+ const char *name;
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+ struct clk *hw;
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+
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+ num_clks = ARRAY_SIZE(mpfs_periph_clks);
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+ for (i = 0; i < num_clks; i++) {
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+ hw = &mpfs_periph_clks[i].hw;
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+ mpfs_periph_clks[i].sys_base = base;
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+ mpfs_periph_clks[i].prate = clk_rate;
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+ name = mpfs_periph_clks[i].periph.name;
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+ ret = clk_register(hw, MPFS_PERIPH_CLOCK, name, parent_name);
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+ if (ret)
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+ ERR_PTR(ret);
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+ id = mpfs_periph_clks[i].periph.id;
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+ clk_dm(id, hw);
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+ }
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+
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+ return 0;
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+}
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+
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+const struct clk_ops mpfs_periph_clk_ops = {
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+ .enable = mpfs_periph_clk_enable,
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+ .disable = mpfs_periph_clk_disable,
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+ .get_rate = mpfs_periph_clk_recalc_rate,
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+};
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+
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+U_BOOT_DRIVER(mpfs_periph_clock) = {
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+ .name = MPFS_PERIPH_CLOCK,
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+ .id = UCLASS_CLK,
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+ .ops = &mpfs_periph_clk_ops,
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+};
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