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@@ -1,5 +1,5 @@
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/*
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/*
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- * [origin: Linux kernel include/asm-arm/arch-at91/at91_pmc.h]
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+ * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_pmc.h]
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*
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*
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* Copyright (C) 2005 Ivan Kokshaysky
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* Copyright (C) 2005 Ivan Kokshaysky
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* Copyright (C) SAN People
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* Copyright (C) SAN People
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@@ -23,6 +23,7 @@
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#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
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#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
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#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
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#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
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#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
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#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
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+#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [AT91CAP9 revC only] */
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#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
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#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
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#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
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#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
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#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */
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#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */
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@@ -39,10 +40,14 @@
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#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
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#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
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#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */
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#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */
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+#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
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+#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
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+#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
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+#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */
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#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
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#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
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#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
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#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
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-#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */
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+#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */
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#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
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#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
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#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
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#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
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@@ -76,10 +81,17 @@
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#define AT91_PMC_PRES_32 (5 << 2)
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#define AT91_PMC_PRES_32 (5 << 2)
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#define AT91_PMC_PRES_64 (6 << 2)
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#define AT91_PMC_PRES_64 (6 << 2)
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#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
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#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
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-#define AT91_PMC_MDIV_1 (0 << 8)
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-#define AT91_PMC_MDIV_2 (1 << 8)
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-#define AT91_PMC_MDIV_3 (2 << 8)
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-#define AT91_PMC_MDIV_4 (3 << 8)
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+#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
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+#define AT91RM9200_PMC_MDIV_2 (1 << 8)
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+#define AT91RM9200_PMC_MDIV_3 (2 << 8)
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+#define AT91RM9200_PMC_MDIV_4 (3 << 8)
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+#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */
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+#define AT91SAM9_PMC_MDIV_2 (1 << 8)
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+#define AT91SAM9_PMC_MDIV_4 (2 << 8)
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+#define AT91SAM9_PMC_MDIV_6 (3 << 8)
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+#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */
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+#define AT91_PMC_PDIV_1 (0 << 12)
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+#define AT91_PMC_PDIV_2 (1 << 12)
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#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
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#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
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@@ -90,6 +102,8 @@
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#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
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#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
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#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
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#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
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#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
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#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
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+#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */
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+#define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */
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#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
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#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
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#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
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#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
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#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
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#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
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@@ -97,8 +111,8 @@
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#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
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#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
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#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */
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#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */
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-#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
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+#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
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-#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */
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+#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */
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#endif
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#endif
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