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+/*
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+ * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
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+ *
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+ * Copyright (C) 2005 David Brownell
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+ * Copyright (C) 2005 Ivan Kokshaysky
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+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ */
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+
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+#include <config.h>
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+#include <asm/arch/hardware.h>
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+#include <asm/arch/at91_pmc.h>
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+#include <asm/arch/clk.h>
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+#include <asm/arch/io.h>
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+
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+static unsigned long cpu_clk_rate_hz;
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+static unsigned long main_clk_rate_hz;
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+static unsigned long mck_rate_hz;
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+static unsigned long plla_rate_hz;
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+static unsigned long pllb_rate_hz;
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+static u32 at91_pllb_usb_init;
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+
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+unsigned long get_cpu_clk_rate(void)
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+{
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+ return cpu_clk_rate_hz;
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+}
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+
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+unsigned long get_main_clk_rate(void)
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+{
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+ return main_clk_rate_hz;
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+}
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+
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+unsigned long get_mck_clk_rate(void)
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+{
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+ return mck_rate_hz;
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+}
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+
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+unsigned long get_plla_clk_rate(void)
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+{
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+ return plla_rate_hz;
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+}
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+
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+unsigned long get_pllb_clk_rate(void)
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+{
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+ return pllb_rate_hz;
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+}
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+
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+u32 get_pllb_init(void)
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+{
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+ return at91_pllb_usb_init;
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+}
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+
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+static unsigned long at91_css_to_rate(unsigned long css)
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+{
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+ switch (css) {
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+ case AT91_PMC_CSS_SLOW:
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+ return AT91_SLOW_CLOCK;
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+ case AT91_PMC_CSS_MAIN:
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+ return main_clk_rate_hz;
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+ case AT91_PMC_CSS_PLLA:
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+ return plla_rate_hz;
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+ case AT91_PMC_CSS_PLLB:
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+ return pllb_rate_hz;
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+ }
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+
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+ return 0;
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+}
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+
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+#ifdef CONFIG_USB_ATMEL
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+static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
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+{
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+ unsigned i, div = 0, mul = 0, diff = 1 << 30;
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+ unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
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+
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+ /* PLL output max 240 MHz (or 180 MHz per errata) */
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+ if (out_freq > 240000000)
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+ goto fail;
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+
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+ for (i = 1; i < 256; i++) {
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+ int diff1;
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+ unsigned input, mul1;
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+
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+ /*
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+ * PLL input between 1MHz and 32MHz per spec, but lower
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+ * frequences seem necessary in some cases so allow 100K.
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+ * Warning: some newer products need 2MHz min.
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+ */
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+ input = main_freq / i;
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+#if defined(CONFIG_AT91SAM9G20)
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+ if (input < 2000000)
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+ continue;
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+#endif
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+ if (input < 100000)
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+ continue;
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+ if (input > 32000000)
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+ continue;
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+
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+ mul1 = out_freq / input;
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+#if defined(CONFIG_AT91SAM9G20)
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+ if (mul > 63)
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+ continue;
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+#endif
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+ if (mul1 > 2048)
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+ continue;
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+ if (mul1 < 2)
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+ goto fail;
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+
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+ diff1 = out_freq - input * mul1;
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+ if (diff1 < 0)
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+ diff1 = -diff1;
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+ if (diff > diff1) {
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+ diff = diff1;
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+ div = i;
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+ mul = mul1;
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+ if (diff == 0)
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+ break;
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+ }
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+ }
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+ if (i == 256 && diff > (out_freq >> 5))
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+ goto fail;
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+ return ret | ((mul - 1) << 16) | div;
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+fail:
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+ return 0;
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+}
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+
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+static u32 at91_pll_rate(u32 freq, u32 reg)
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+{
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+ unsigned mul, div;
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+
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+ div = reg & 0xff;
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+ mul = (reg >> 16) & 0x7ff;
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+ if (div && mul) {
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+ freq /= div;
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+ freq *= mul + 1;
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+ } else
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+ freq = 0;
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+
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+ return freq;
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+}
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+#endif
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+
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+int at91_clock_init(unsigned long main_clock)
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+{
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+ unsigned freq, mckr;
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+#ifndef AT91_MAIN_CLOCK
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+ unsigned tmp;
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+ /*
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+ * When the bootloader initialized the main oscillator correctly,
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+ * there's no problem using the cycle counter. But if it didn't,
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+ * or when using oscillator bypass mode, we must be told the speed
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+ * of the main clock.
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+ */
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+ if (!main_clock) {
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+ do {
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+ tmp = at91_sys_read(AT91_CKGR_MCFR);
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+ } while (!(tmp & AT91_PMC_MAINRDY));
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+ main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
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+ }
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+#endif
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+ main_clk_rate_hz = main_clock;
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+
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+ /* report if PLLA is more than mildly overclocked */
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+ plla_rate_hz = at91_pll_rate(main_clock, at91_sys_read(AT91_CKGR_PLLAR));
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+
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+#ifdef CONFIG_USB_ATMEL
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+ /*
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+ * USB clock init: choose 48 MHz PLLB value,
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+ * disable 48MHz clock during usb peripheral suspend.
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+ *
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+ * REVISIT: assumes MCK doesn't derive from PLLB!
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+ */
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+ at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
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+ AT91_PMC_USB96M;
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+ pllb_rate_hz = at91_pll_rate(main_clock, at91_pllb_usb_init);
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+#endif
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+
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+ /*
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+ * MCK and CPU derive from one of those primary clocks.
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+ * For now, assume this parentage won't change.
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+ */
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+ mckr = at91_sys_read(AT91_PMC_MCKR);
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+ freq = mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_CSS);
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+ freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */
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+#if defined(CONFIG_AT91RM9200)
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+ mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
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+#elif defined(CONFIG_AT91SAM9G20)
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+ mck_rate_hz = (mckr & AT91_PMC_MDIV) ?
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+ freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
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+ if (mckr & AT91_PMC_PDIV)
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+ freq /= 2; /* processor clock division */
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+#else
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+ mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
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+#endif
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+ cpu_clk_rate_hz = freq;
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+
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+ return 0;
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+}
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+
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