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Merge branch 'master' of git://git.denx.de/u-boot-usb

- dwc3 and cdns3 bug fixes
Tom Rini vor 4 Jahren
Ursprung
Commit
d792b63feb
4 geänderte Dateien mit 19 neuen und 16 gelöschten Zeilen
  1. 2 0
      MAINTAINERS
  2. 1 0
      drivers/usb/cdns3/ep0.c
  3. 8 4
      drivers/usb/dwc3/core.c
  4. 8 12
      drivers/usb/dwc3/core.h

+ 2 - 0
MAINTAINERS

@@ -883,6 +883,8 @@ M:	Marek Vasut <marex@denx.de>
 S:	Maintained
 T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-usb.git
 F:	drivers/usb/
+F:	common/usb.c
+F:	common/usb_kbd.c
 
 USB xHCI
 M:	Bin Meng <bmeng.cn@gmail.com>

+ 1 - 0
drivers/usb/cdns3/ep0.c

@@ -10,6 +10,7 @@
  *          Peter Chen <peter.chen@nxp.com>
  */
 
+#include <cpu_func.h>
 #include <linux/usb/composite.h>
 #include <linux/iopoll.h>
 

+ 8 - 4
drivers/usb/dwc3/core.c

@@ -622,15 +622,19 @@ static void dwc3_uboot_hsphy_mode(struct dwc3_device *dwc3_dev,
 
 	/* Set dwc3 usb2 phy config */
 	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
-	reg |= DWC3_GUSB2PHYCFG_PHYIF;
-	reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
 
 	switch (hsphy_mode) {
 	case USBPHY_INTERFACE_MODE_UTMI:
-		reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT;
+		reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
+			DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
+		reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
+			DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
 		break;
 	case USBPHY_INTERFACE_MODE_UTMIW:
-		reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
+		reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
+			DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
+		reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
+			DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
 		break;
 	default:
 		break;

+ 8 - 12
drivers/usb/dwc3/core.h

@@ -162,18 +162,14 @@
 /* Global USB2 PHY Configuration Register */
 #define DWC3_GUSB2PHYCFG_PHYSOFTRST	(1 << 31)
 #define DWC3_GUSB2PHYCFG_SUSPHY		(1 << 6)
-#define DWC3_GUSB2PHYCFG_PHYIF		BIT(3)
-
-/* Global USB2 PHY Configuration Mask */
-#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK		(0xf << 10)
-
-/* Global USB2 PHY Configuration Offset */
-#define DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET	10
-
-#define DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT	(0x5 << \
-		DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
-#define DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT		(0x9 << \
-		DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
+#define DWC3_GUSB2PHYCFG_PHYIF(n)	((n) << 3)
+#define DWC3_GUSB2PHYCFG_PHYIF_MASK	DWC3_GUSB2PHYCFG_PHYIF(1)
+#define DWC3_GUSB2PHYCFG_USBTRDTIM(n)	((n) << 10)
+#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK	DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
+#define USBTRDTIM_UTMI_8_BIT		9
+#define USBTRDTIM_UTMI_16_BIT		5
+#define UTMI_PHYIF_16_BIT		1
+#define UTMI_PHYIF_8_BIT		0
 
 /* Global USB3 PIPE Control Register */
 #define DWC3_GUSB3PIPECTL_PHYSOFTRST	(1 << 31)