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@@ -162,18 +162,14 @@
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/* Global USB2 PHY Configuration Register */
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#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
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#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
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-#define DWC3_GUSB2PHYCFG_PHYIF BIT(3)
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-
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-/* Global USB2 PHY Configuration Mask */
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-#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK (0xf << 10)
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-
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-/* Global USB2 PHY Configuration Offset */
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-#define DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET 10
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-
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-#define DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT (0x5 << \
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- DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
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-#define DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT (0x9 << \
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- DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
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+#define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3)
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+#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)
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+#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10)
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+#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
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+#define USBTRDTIM_UTMI_8_BIT 9
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+#define USBTRDTIM_UTMI_16_BIT 5
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+#define UTMI_PHYIF_16_BIT 1
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+#define UTMI_PHYIF_8_BIT 0
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/* Global USB3 PIPE Control Register */
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#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
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