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Merge branch '2021-09-30-whitespace-cleanups' into next

- A large number of whitespace cleanups from Wolfgang
Tom Rini 2 years ago
parent
commit
c8988efc88
100 changed files with 237 additions and 299 deletions
  1. 1 1
      Licenses/lgpl-2.0.txt
  2. 3 3
      Makefile
  3. 0 1
      README
  4. 1 1
      arch/arc/lib/libgcc2.h
  5. 1 1
      arch/arm/cpu/arm926ejs/armada100/timer.c
  6. 0 1
      arch/arm/cpu/arm926ejs/cache.c
  7. 0 1
      arch/arm/cpu/armv7/psci-common.c
  8. 10 10
      arch/arm/cpu/armv8/fel_utils.S
  9. 18 18
      arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
  10. 2 2
      arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
  11. 0 2
      arch/arm/cpu/armv8/hisilicon/pinmux.c
  12. 0 1
      arch/arm/cpu/armv8/xen/hypercall.S
  13. 0 1
      arch/arm/dts/sama7g5-pinfunc.h
  14. 1 1
      arch/arm/dts/vf610-pinfunc.h
  15. 1 1
      arch/arm/include/asm/arch-am33xx/cpu.h
  16. 1 1
      arch/arm/include/asm/arch-armada100/mfp.h
  17. 0 1
      arch/arm/include/asm/arch-imxrt/imxrt.h
  18. 11 11
      arch/arm/include/asm/arch-mx25/imx-regs.h
  19. 2 2
      arch/arm/include/asm/arch-mx5/imx-regs.h
  20. 2 2
      arch/arm/include/asm/arch-mx6/mx6_plugin.S
  21. 1 1
      arch/arm/include/asm/arch-mx7/mx7_plugin.S
  22. 1 1
      arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S
  23. 8 8
      arch/arm/include/asm/arch-rockchip/cru_rk3368.h
  24. 0 1
      arch/arm/include/asm/arch-rockchip/f_rockusb.h
  25. 0 1
      arch/arm/include/asm/arch-stm32/stm32f.h
  26. 0 1
      arch/arm/include/asm/arch-stv0991/stv0991_defs.h
  27. 4 4
      arch/arm/include/asm/arch-vf610/iomux-vf610.h
  28. 1 1
      arch/arm/include/asm/macro.h
  29. 3 3
      arch/arm/include/asm/ti-common/davinci_nand.h
  30. 0 1
      arch/arm/include/asm/xen.h
  31. 1 2
      arch/arm/lib/ccn504.S
  32. 5 5
      arch/arm/lib/div64.S
  33. 3 3
      arch/arm/lib/lib1funcs.S
  34. 0 1
      arch/arm/mach-at91/armv7/sama7g5_devices.c
  35. 0 1
      arch/arm/mach-at91/atmel_sfr.c
  36. 12 12
      arch/arm/mach-at91/include/mach/at91_mc.h
  37. 1 1
      arch/arm/mach-at91/include/mach/at91_st.h
  38. 0 1
      arch/arm/mach-bcm283x/msg.c
  39. 18 18
      arch/arm/mach-davinci/include/mach/da8xx-usb.h
  40. 1 1
      arch/arm/mach-davinci/include/mach/davinci_misc.h
  41. 2 2
      arch/arm/mach-imx/Makefile
  42. 0 1
      arch/arm/mach-imx/mx7/soc.c
  43. 3 3
      arch/arm/mach-keystone/include/mach/hardware.h
  44. 0 1
      arch/arm/mach-kirkwood/cpu.c
  45. 0 2
      arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
  46. 0 1
      arch/arm/mach-octeontx/Makefile
  47. 0 1
      arch/arm/mach-octeontx2/Makefile
  48. 1 1
      arch/arm/mach-omap2/clocks-common.c
  49. 1 1
      arch/arm/mach-omap2/omap5/prcm-regs.c
  50. 0 1
      arch/arm/mach-omap2/pipe3-phy.c
  51. 1 1
      arch/arm/mach-orion5x/timer.c
  52. 1 1
      arch/arm/mach-rmobile/pfc-r8a7790.h
  53. 1 1
      arch/arm/mach-rockchip/rk3368/Makefile
  54. 2 2
      arch/arm/mach-s5pc1xx/include/mach/sromc.h
  55. 0 1
      arch/arm/mach-snapdragon/dram.c
  56. 8 8
      arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
  57. 1 1
      arch/arm/mach-sunxi/dram_sun4i.c
  58. 2 2
      arch/arm/mach-sunxi/dram_sun8i_a33.c
  59. 1 1
      arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c
  60. 0 1
      arch/arm/mach-tegra/tegra20/display.c
  61. 0 1
      arch/arm/mach-versatile/timer.c
  62. 2 2
      arch/m68k/cpu/mcf5227x/start.S
  63. 1 1
      arch/m68k/cpu/mcf523x/cpu.c
  64. 1 1
      arch/m68k/cpu/mcf52x2/cpu.c
  65. 0 1
      arch/m68k/cpu/mcf530x/Makefile
  66. 1 1
      arch/m68k/cpu/mcf532x/cpu.c
  67. 1 1
      arch/m68k/cpu/mcf5445x/cpu.c
  68. 3 3
      arch/m68k/cpu/mcf5445x/start.S
  69. 0 1
      arch/m68k/include/asm/immap_5307.h
  70. 1 1
      arch/m68k/include/asm/m5271.h
  71. 0 1
      arch/m68k/include/asm/m5307.h
  72. 1 1
      arch/m68k/lib/muldi3.c
  73. 16 16
      arch/mips/include/asm/mipsregs.h
  74. 0 1
      arch/mips/mach-jz47xx/include/mach/jz4780_dram.h
  75. 3 3
      arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S
  76. 3 3
      arch/nds32/cpu/n1213/ag101/lowlevel_init.S
  77. 1 1
      arch/nds32/cpu/n1213/ag101/watchdog.S
  78. 4 4
      arch/nds32/cpu/n1213/start.S
  79. 0 1
      arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
  80. 0 1
      arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
  81. 4 4
      arch/powerpc/cpu/mpc85xx/start.S
  82. 2 2
      arch/powerpc/include/asm/fsl_lbc.h
  83. 2 2
      arch/powerpc/include/asm/immap_85xx.h
  84. 1 1
      arch/powerpc/include/asm/processor.h
  85. 0 1
      arch/powerpc/lib/ppccache.S
  86. 1 1
      arch/sandbox/include/asm/gpio.h
  87. 0 1
      arch/sh/lib/time.c
  88. 1 1
      arch/x86/cpu/intel_common/car2.S
  89. 2 2
      arch/x86/lib/bios_asm.S
  90. 0 3
      arch/xtensa/include/asm/arch-dc232b/core.h
  91. 0 5
      arch/xtensa/include/asm/arch-dc232b/tie-asm.h
  92. 0 1
      arch/xtensa/include/asm/arch-dc232b/tie.h
  93. 22 26
      arch/xtensa/include/asm/arch-dc233c/core.h
  94. 0 5
      arch/xtensa/include/asm/arch-dc233c/tie-asm.h
  95. 0 1
      arch/xtensa/include/asm/arch-dc233c/tie.h
  96. 27 31
      arch/xtensa/include/asm/arch-de212/core.h
  97. 0 1
      arch/xtensa/include/asm/arch-de212/tie-asm.h
  98. 0 1
      arch/xtensa/include/asm/arch-de212/tie.h
  99. 0 2
      arch/xtensa/include/asm/cacheasm.h
  100. 0 1
      arch/xtensa/include/asm/regs.h

+ 1 - 1
Licenses/lgpl-2.0.txt

@@ -133,7 +133,7 @@ such a program is covered only if its contents constitute a work based
 on the Library (independent of the use of the Library in a tool for
 writing it).  Whether that is true depends on what the Library does
 and what the program that uses the Library does.
-  
+
   1. You may copy and distribute verbatim copies of the Library's
 complete source code as you receive it, in any medium, provided that
 you conspicuously and appropriately publish on each copy an

+ 3 - 3
Makefile

@@ -327,14 +327,14 @@ os_x_before	= $(shell if [ $(DARWIN_MAJOR_VERSION) -le $(1) -a \
 	$(DARWIN_MINOR_VERSION) -le $(2) ] ; then echo "$(3)"; else echo "$(4)"; fi ;)
 
 os_x_after = $(shell if [ $(DARWIN_MAJOR_VERSION) -ge $(1) -a \
-	$(DARWIN_MINOR_VERSION) -ge $(2) ] ; then echo "$(3)"; else echo "$(4)"; fi ;)	
+	$(DARWIN_MINOR_VERSION) -ge $(2) ] ; then echo "$(3)"; else echo "$(4)"; fi ;)
 
 # Snow Leopards build environment has no longer restrictions as described above
 HOSTCC       = $(call os_x_before, 10, 5, "cc", "gcc")
 KBUILD_HOSTCFLAGS  += $(call os_x_before, 10, 4, "-traditional-cpp")
 KBUILD_HOSTLDFLAGS += $(call os_x_before, 10, 5, "-multiply_defined suppress")
 
-# macOS Mojave (10.14.X) 
+# macOS Mojave (10.14.X)
 # Undefined symbols for architecture x86_64: "_PyArg_ParseTuple"
 KBUILD_HOSTLDFLAGS += $(call os_x_after, 10, 14, "-lpython -dynamclib", "")
 endif
@@ -1739,7 +1739,7 @@ endif
 # May be overridden by arch/$(ARCH)/config.mk
 ifdef CONFIG_LTO
 quiet_cmd_u-boot__ ?= LTO     $@
-      cmd_u-boot__ ?= 								\
+      cmd_u-boot__ ?=								\
 		$(CC) -nostdlib -nostartfiles					\
 		$(LTO_FINAL_LDFLAGS) $(c_flags)					\
 		$(KBUILD_LDFLAGS:%=-Wl,%) $(LDFLAGS_u-boot:%=-Wl,%) -o $@	\

+ 0 - 1
README

@@ -300,7 +300,6 @@ board_init_r():
 	- loads U-Boot or (in falcon mode) Linux
 
 
-
 Configuration Options:
 ----------------------
 

+ 1 - 1
arch/arc/lib/libgcc2.h

@@ -35,7 +35,7 @@ typedef		 int HItype	__attribute__ ((mode (HI)));
 typedef unsigned int UHItype	__attribute__ ((mode (HI)));
 #if MIN_UNITS_PER_WORD > 1
 /* These typedefs are usually forbidden on dsp's with UNITS_PER_WORD 1.  */
-typedef 	 int SItype	__attribute__ ((mode (SI)));
+typedef		 int SItype	__attribute__ ((mode (SI)));
 typedef unsigned int USItype	__attribute__ ((mode (SI)));
 #if __SIZEOF_LONG_LONG__ > 4
 /* These typedefs are usually forbidden on archs with UNITS_PER_WORD 2.  */

+ 1 - 1
arch/arm/cpu/arm926ejs/armada100/timer.c

@@ -45,7 +45,7 @@ struct armd1tmr_registers {
 #define TIMER			0	/* Use TIMER 0 */
 /* Each timer has 3 match registers */
 #define MATCH_CMP(x)		((3 * TIMER) + x)
-#define TIMER_LOAD_VAL 		0xffffffff
+#define TIMER_LOAD_VAL		0xffffffff
 #define	COUNT_RD_REQ		0x1
 
 DECLARE_GLOBAL_DATA_PTR;

+ 0 - 1
arch/arm/cpu/arm926ejs/cache.c

@@ -89,4 +89,3 @@ void enable_caches(void)
 	dcache_enable();
 #endif
 }
-

+ 0 - 1
arch/arm/cpu/armv7/psci-common.c

@@ -43,4 +43,3 @@ u32 __secure psci_get_context_id(int cpu)
 {
 	return psci_context_id[cpu];
 }
-

+ 10 - 10
arch/arm/cpu/armv8/fel_utils.S

@@ -64,18 +64,18 @@ ENTRY(return_to_fel)
 
 /* AArch32 code to restore the state from fel_stash and return back to FEL. */
 back_in_32:
-	.word	0xe59f0028 	// ldr	r0, [pc, #40]	; load fel_stash address
-	.word	0xe5901008 	// ldr	r1, [r0, #8]
-	.word	0xe129f001 	// msr	CPSR_fc, r1
+	.word	0xe59f0028	// ldr	r0, [pc, #40]	; load fel_stash address
+	.word	0xe5901008	// ldr	r1, [r0, #8]
+	.word	0xe129f001	// msr	CPSR_fc, r1
 	.word	0xf57ff06f	// isb
-	.word	0xe590d000 	// ldr	sp, [r0]
-	.word	0xe590e004 	// ldr	lr, [r0, #4]
-	.word	0xe5901010 	// ldr	r1, [r0, #16]
-	.word	0xee0c1f10 	// mcr	15, 0, r1, cr12, cr0, {0} ; VBAR
-	.word	0xe590100c 	// ldr	r1, [r0, #12]
-	.word	0xee011f10 	// mcr	15, 0, r1, cr1, cr0, {0}  ; SCTLR
+	.word	0xe590d000	// ldr	sp, [r0]
+	.word	0xe590e004	// ldr	lr, [r0, #4]
+	.word	0xe5901010	// ldr	r1, [r0, #16]
+	.word	0xee0c1f10	// mcr	15, 0, r1, cr12, cr0, {0} ; VBAR
+	.word	0xe590100c	// ldr	r1, [r0, #12]
+	.word	0xee011f10	// mcr	15, 0, r1, cr1, cr0, {0}  ; SCTLR
 	.word	0xf57ff06f	// isb
-	.word	0xe12fff1e 	// bx	lr		; return to FEL
+	.word	0xe12fff1e	// bx	lr		; return to FEL
 fel_stash_addr:
 	.word   0x00000000	// receives fel_stash addr, by AA64 code above
 ENDPROC(return_to_fel)

+ 18 - 18
arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3

@@ -42,22 +42,22 @@ Flash Layout
    pre-silicon platforms (simulator and emulator):
 
 	-------------------------
-	| 	FIT Image	|
+	|	FIT Image	|
 	| (linux + DTB + RFS)	|
 	------------------------- ----> 0x0120_0000
-	| 	Debug Server FW |
+	|	Debug Server FW |
 	------------------------- ----> 0x00C0_0000
-	|	AIOP FW 	|
+	|	AIOP FW		|
 	------------------------- ----> 0x0070_0000
-	|	MC FW 		|
+	|	MC FW		|
 	------------------------- ----> 0x006C_0000
-	| 	MC DPL Blob 	|
+	|	MC DPL Blob	|
 	------------------------- ----> 0x0020_0000
-	| 	BootLoader + Env|
+	|	BootLoader + Env|
 	------------------------- ----> 0x0000_1000
-	|	PBI 		|
+	|	PBI		|
 	------------------------- ----> 0x0000_0080
-	|	RCW 		|
+	|	RCW		|
 	------------------------- ----> 0x0000_0000
 
 	32-MB NOR flash layout for pre-silicon platforms (simulator and emulator)
@@ -70,45 +70,45 @@ Flash Layout
 	----------------------------------------- ----> 0x5_8790_0000	|
 	| FIT Image (linux + DTB + RFS)	(40M)	|			|
 	----------------------------------------- ----> 0x5_8510_0000	|
-	|	PHY firmware (2M)	 	|			|
+	|	PHY firmware (2M)		|			|
 	----------------------------------------- ----> 0x5_84F0_0000	| 64K
 	|	Debug Server FW (2M)		|			| Alt
 	----------------------------------------- ----> 0x5_84D0_0000	| Bank
 	|	AIOP FW (4M)			|			|
 	----------------------------------------- ----> 0x5_8490_0000 (vbank4)
-	|	MC DPC Blob (1M) 		|			|
+	|	MC DPC Blob (1M)		|			|
 	----------------------------------------- ----> 0x5_8480_0000	|
 	|	MC DPL Blob (1M)		|			|
 	----------------------------------------- ----> 0x5_8470_0000	|
-	| 	MC FW (4M)			|			|
+	|	MC FW (4M)			|			|
 	----------------------------------------- ----> 0x5_8430_0000	|
-	|	BootLoader Environment (1M) 	|			|
+	|	BootLoader Environment (1M)	|			|
 	----------------------------------------- ----> 0x5_8420_0000	|
 	|	BootLoader (1M)			|			|
 	----------------------------------------- ----> 0x5_8410_0000	|
-	|	RCW and PBI (1M) 		|			|
+	|	RCW and PBI (1M)		|			|
 	----------------------------------------- ----> 0x5_8400_0000 ---
 	|	.. Unused .. (7M)		|			|
 	----------------------------------------- ----> 0x5_8390_0000	|
 	| FIT Image (linux + DTB + RFS)	(40M)	|			|
 	----------------------------------------- ----> 0x5_8110_0000	|
-	|	PHY firmware (2M)	 	|			|
+	|	PHY firmware (2M)		|			|
 	----------------------------------------- ----> 0x5_80F0_0000	| 64K
 	|	Debug Server FW (2M)		|			| Bank
 	----------------------------------------- ----> 0x5_80D0_0000	|
 	|	AIOP FW (4M)			|			|
 	----------------------------------------- ----> 0x5_8090_0000 (vbank0)
-	|	MC DPC Blob (1M) 		|			|
+	|	MC DPC Blob (1M)		|			|
 	----------------------------------------- ----> 0x5_8080_0000	|
 	|	MC DPL Blob (1M)		|			|
 	----------------------------------------- ----> 0x5_8070_0000	|
-	| 	MC FW (4M)			|			|
+	|	MC FW (4M)			|			|
 	----------------------------------------- ----> 0x5_8030_0000	|
-	|	BootLoader Environment (1M) 	|			|
+	|	BootLoader Environment (1M)	|			|
 	----------------------------------------- ----> 0x5_8020_0000	|
 	|	BootLoader (1M)			|			|
 	----------------------------------------- ----> 0x5_8010_0000	|
-	|	RCW and PBI (1M) 		|			|
+	|	RCW and PBI (1M)		|			|
 	----------------------------------------- ----> 0x5_8000_0000 ---
 
 	128-MB NOR flash layout for QDS and RDB boards

+ 2 - 2
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S

@@ -250,7 +250,7 @@ ENTRY(lowlevel_init)
 	 * b. We use only Region0 whose NSAID write/read is EN
 	 *
 	 * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
-	 * 	 placeholders.
+	 *	 placeholders.
 	 */
 
 .macro tzasc_prog, xreg
@@ -259,7 +259,7 @@ ENTRY(lowlevel_init)
 	mov     x16, #0x10000
 	mul     x14, \xreg, x16
 	add     x14, x14,x12
-	mov 	x1, #0x8
+	mov	x1, #0x8
 	add     x1, x1, x14
 
 	ldr     w0, [x1]		/* Filter 0 Gate Keeper Register */

+ 0 - 2
arch/arm/cpu/armv8/hisilicon/pinmux.c

@@ -181,5 +181,3 @@ int hi6220_pinmux_config(int peripheral)
 
 	return 0;
 }
-
-

+ 0 - 1
arch/arm/cpu/armv8/xen/hypercall.S

@@ -76,4 +76,3 @@ HYPERCALL2(sched_op);
 HYPERCALL2(event_channel_op);
 HYPERCALL2(hvm_op);
 HYPERCALL2(memory_op);
-

+ 0 - 1
arch/arm/dts/sama7g5-pinfunc.h

@@ -921,4 +921,3 @@
 #define PIN_PE7__TIOA4			PINMUX_PIN(PIN_PE7, 3, 3)
 #define PIN_PE7__ISC_D11		PINMUX_PIN(PIN_PE7, 5, 2)
 #define PIN_PE7__G1_TSUCOMP		PINMUX_PIN(PIN_PE7, 7, 1)
-

+ 1 - 1
arch/arm/dts/vf610-pinfunc.h

@@ -424,7 +424,7 @@
 #define VF610_PAD_PTD29__FTM3_CH2		0x104 0x000 ALT4 0x0
 #define VF610_PAD_PTD29__DSPI2_SIN		0x104 0x000 ALT5 0x0
 #define VF610_PAD_PTD29__DEBUG_OUT11		0x104 0x000 ALT7 0x0
-#define VF610_PAD_PTD28__GPIO_66	 	0x108 0x000 ALT0 0x0
+#define VF610_PAD_PTD28__GPIO_66		0x108 0x000 ALT0 0x0
 #define VF610_PAD_PTD28__FB_AD28		0x108 0x000 ALT1 0x0
 #define VF610_PAD_PTD28__NF_IO12		0x108 0x000 ALT2 0x0
 #define VF610_PAD_PTD28__I2C2_SCL		0x108 0x34C ALT3 0x1

+ 1 - 1
arch/arm/include/asm/arch-am33xx/cpu.h

@@ -408,7 +408,7 @@ struct cm_dpll {
 	unsigned int resv1;
 	unsigned int clktimer2clk;	/* offset 0x04 */
 	unsigned int resv2[11];
-	unsigned int clkselmacclk;	/* offset 0x34 */ 
+	unsigned int clkselmacclk;	/* offset 0x34 */
 };
 #endif /* CONFIG_AM43XX */
 

+ 1 - 1
arch/arm/include/asm/arch-armada100/mfp.h

@@ -17,7 +17,7 @@
 /*
  * Frequently used MFP Configuration macros for all ARMADA100 family of SoCs
  *
- * 				    offset, pull,pF, drv,dF, edge,eF ,afn,aF
+ *				    offset, pull,pF, drv,dF, edge,eF ,afn,aF
  */
 /* UART1 */
 #define MFP107_UART1_TXD	(MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST)

+ 0 - 1
arch/arm/include/asm/arch-imxrt/imxrt.h

@@ -8,4 +8,3 @@
 #define _ASM_ARCH_IMXRT_H
 
 #endif /* _ASM_ARCH_IMXRT_H */
-

+ 11 - 11
arch/arm/include/asm/arch-mx25/imx-regs.h

@@ -50,11 +50,11 @@ struct ccm_regs {
 
 /* Enhanced SDRAM Controller (ESDRAMC) registers */
 struct esdramc_regs {
-	u32 ctl0; 	/* control 0 */
-	u32 cfg0; 	/* configuration 0 */
-	u32 ctl1; 	/* control 1 */
-	u32 cfg1; 	/* configuration 1 */
-	u32 misc; 	/* miscellaneous */
+	u32 ctl0;	/* control 0 */
+	u32 cfg0;	/* configuration 0 */
+	u32 ctl1;	/* control 1 */
+	u32 cfg1;	/* configuration 1 */
+	u32 misc;	/* miscellaneous */
 	u32 pad[3];
 	u32 cdly1;	/* Delay Line 1 configuration debug */
 	u32 cdly2;	/* delay line 2 configuration debug */
@@ -66,11 +66,11 @@ struct esdramc_regs {
 
 /* General Purpose Timer (GPT) registers */
 struct gpt_regs {
-	u32 ctrl;   	/* control */
-	u32 pre;    	/* prescaler */
-	u32 stat;   	/* status */
-	u32 intr;   	/* interrupt */
-	u32 cmp[3]; 	/* output compare 1-3 */
+	u32 ctrl;	/* control */
+	u32 pre;	/* prescaler */
+	u32 stat;	/* status */
+	u32 intr;	/* interrupt */
+	u32 cmp[3];	/* output compare 1-3 */
 	u32 capt[2];	/* input capture 1-2 */
 	u32 counter;	/* counter */
 };
@@ -456,7 +456,7 @@ struct epit_regs {
 #define GPT_CTRL_TEN		1		/* Timer enable	*/
 
 /* WDOG enable */
-#define WCR_WDE 		0x04
+#define WCR_WDE			0x04
 #define WSR_UNLOCK1		0x5555
 #define WSR_UNLOCK2		0xAAAA
 

+ 2 - 2
arch/arm/include/asm/arch-mx5/imx-regs.h

@@ -43,7 +43,7 @@
 #define MMC_SDHC1_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00004000)
 #define MMC_SDHC2_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00008000)
 #define UART3_BASE		(SPBA0_BASE_ADDR + 0x0000C000)
-#define CSPI1_BASE_ADDR 	(SPBA0_BASE_ADDR + 0x00010000)
+#define CSPI1_BASE_ADDR		(SPBA0_BASE_ADDR + 0x00010000)
 #define SSI2_BASE_ADDR		(SPBA0_BASE_ADDR + 0x00014000)
 #define MMC_SDHC3_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00020000)
 #define MMC_SDHC4_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00024000)
@@ -97,7 +97,7 @@
 #define IIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00098000)
 #define CSU_BASE_ADDR		(AIPS2_BASE_ADDR + 0x0009C000)
 #define ARM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A0000)
-#define OWIRE_BASE_ADDR 	(AIPS2_BASE_ADDR + 0x000A4000)
+#define OWIRE_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A4000)
 #define FIRI_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A8000)
 #define CSPI2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000AC000)
 #define SDMA_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B0000)

+ 2 - 2
arch/arm/include/asm/arch-mx6/mx6_plugin.S

@@ -7,10 +7,10 @@
 
 #ifdef CONFIG_ROM_UNIFIED_SECTIONS
 #define ROM_API_TABLE_BASE_ADDR_LEGACY		0x180
-#define ROM_VERSION_OFFSET               	0x80
+#define ROM_VERSION_OFFSET			0x80
 #else
 #define ROM_API_TABLE_BASE_ADDR_LEGACY		0xC0
-#define ROM_VERSION_OFFSET               	0x48
+#define ROM_VERSION_OFFSET			0x48
 #endif
 #define ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15	0xC4
 #define ROM_API_TABLE_BASE_ADDR_MX6DL_TO12	0xC4

+ 1 - 1
arch/arm/include/asm/arch-mx7/mx7_plugin.S

@@ -6,7 +6,7 @@
 #include <config.h>
 
 #define ROM_API_TABLE_BASE_ADDR_LEGACY		0x180
-#define ROM_VERSION_OFFSET               	0x80
+#define ROM_VERSION_OFFSET			0x80
 #define ROM_API_HWCNFG_SETUP_OFFSET		0x08
 
 plugin_start:

+ 1 - 1
arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S

@@ -6,7 +6,7 @@
 #include <config.h>
 
 #define ROM_API_TABLE_BASE_ADDR_LEGACY		0x180
-#define ROM_VERSION_OFFSET               	0x80
+#define ROM_VERSION_OFFSET			0x80
 #define ROM_API_HWCNFG_SETUP_OFFSET		0x08
 
 plugin_start:

+ 8 - 8
arch/arm/include/asm/arch-rockchip/cru_rk3368.h

@@ -126,17 +126,17 @@ enum {
 	/* GLB_RST_CON */
 	PMU_GLB_SRST_CTRL_SHIFT		= 2,
 	PMU_GLB_SRST_CTRL_MASK		= GENMASK(3, 2),
-	PMU_RST_BY_FST_GLB_SRST 	= 0,
-	PMU_RST_BY_SND_GLB_SRST 	= 1,
+	PMU_RST_BY_FST_GLB_SRST		= 0,
+	PMU_RST_BY_SND_GLB_SRST		= 1,
 	PMU_RST_DISABLE			= 2,
 	WDT_GLB_SRST_CTRL_SHIFT		= 1,
 	WDT_GLB_SRST_CTRL_MASK		= BIT(1),
-	WDT_TRIGGER_SND_GLB_SRST 	= 0,
-	WDT_TRIGGER_FST_GLB_SRST 	= 1,
-	TSADC_GLB_SRST_CTRL_SHIFT 	= 0,
-	TSADC_GLB_SRST_CTRL_MASK  	= BIT(0),
-	TSADC_TRIGGER_SND_GLB_SRST 	= 0,
-	TSADC_TRIGGER_FST_GLB_SRST 	= 1,
+	WDT_TRIGGER_SND_GLB_SRST	= 0,
+	WDT_TRIGGER_FST_GLB_SRST	= 1,
+	TSADC_GLB_SRST_CTRL_SHIFT	= 0,
+	TSADC_GLB_SRST_CTRL_MASK	= BIT(0),
+	TSADC_TRIGGER_SND_GLB_SRST	= 0,
+	TSADC_TRIGGER_FST_GLB_SRST	= 1,
 
 };
 #endif

+ 0 - 1
arch/arm/include/asm/arch-rockchip/f_rockusb.h

@@ -133,4 +133,3 @@ struct f_rockusb {
 /* init rockusb device, tell rockusb which device you want to read/write*/
 void rockusb_dev_init(char *dev_type, int dev_index);
 #endif /* _F_ROCKUSB_H_ */
-

+ 0 - 1
arch/arm/include/asm/arch-stm32/stm32f.h

@@ -18,4 +18,3 @@
 void stm32_flash_latency_cfg(int latency);
 
 #endif /* _ASM_ARCH_STM32F_H */
-

+ 0 - 1
arch/arm/include/asm/arch-stv0991/stv0991_defs.h

@@ -12,4 +12,3 @@ extern int stv0991_pinmux_config(enum periph_id);
 extern int clock_setup(enum periph_clock);
 
 #endif
-

+ 4 - 4
arch/arm/include/asm/arch-vf610/iomux-vf610.h

@@ -163,13 +163,13 @@ enum {
 	VF610_PAD_PTB24__NF_WE_B		= IOMUX_PAD(0x0178, 0x0178, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
 	VF610_PAD_PTB25__NF_CE0_B		= IOMUX_PAD(0x017c, 0x017c, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
 
-	VF610_PAD_PTB27__NF_RE_B 		= IOMUX_PAD(0x0184, 0x0184, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+	VF610_PAD_PTB27__NF_RE_B		= IOMUX_PAD(0x0184, 0x0184, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
 
-	VF610_PAD_PTC26__NF_RB_B 		= IOMUX_PAD(0x018C, 0x018C, 5, __NA_, 0, VF610_NFC_RB_PAD_CTRL),
+	VF610_PAD_PTC26__NF_RB_B		= IOMUX_PAD(0x018C, 0x018C, 5, __NA_, 0, VF610_NFC_RB_PAD_CTRL),
 
-	VF610_PAD_PTC27__NF_ALE  		= IOMUX_PAD(0x0190, 0x0190, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+	VF610_PAD_PTC27__NF_ALE			= IOMUX_PAD(0x0190, 0x0190, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
 
-	VF610_PAD_PTC28__NF_CLE  		= IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+	VF610_PAD_PTC28__NF_CLE			= IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
 
 	VF610_PAD_PTE0__DCU0_HSYNC		= IOMUX_PAD(0x01a4, 0x01a4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
 	VF610_PAD_PTE1__DCU0_VSYNC		= IOMUX_PAD(0x01a8, 0x01a8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),

+ 1 - 1
arch/arm/include/asm/macro.h

@@ -154,7 +154,7 @@ lr	.req	x30
 	orr	\xreg1, \xreg1, \xreg2
 	cbz	\xreg1, \master_label
 #else
-	b 	\master_label
+	b	\master_label
 #endif
 .endm
 

+ 3 - 3
arch/arm/include/asm/ti-common/davinci_nand.h

@@ -12,9 +12,9 @@
 #include <linux/mtd/rawnand.h>
 #include <asm/arch/hardware.h>
 
-#define NAND_READ_START  	0x00
-#define NAND_READ_END    	0x30
-#define NAND_STATUS      	0x70
+#define NAND_READ_START		0x00
+#define NAND_READ_END		0x30
+#define NAND_STATUS		0x70
 
 #define MASK_CLE		0x10
 #define MASK_ALE		0x08

+ 0 - 1
arch/arm/include/asm/xen.h

@@ -4,4 +4,3 @@
  */
 
 extern unsigned long rom_pointer[];
-

+ 1 - 2
arch/arm/lib/ccn504.S

@@ -12,7 +12,7 @@
 /*************************************************************************
  *
  * void ccn504_add_masters_to_dvm(CCI_MN_BASE, CCI_MN_RNF_NODEID_LIST,
- * 				  CCI_MN_DVM_DOMAIN_CTL_SET);
+ *				  CCI_MN_DVM_DOMAIN_CTL_SET);
  *
  * Add fully-coherent masters to DVM domain
  *
@@ -78,4 +78,3 @@ ENTRY(ccn504_set_aux)
 
 	ret
 ENDPROC(ccn504_set_aux)
-

+ 5 - 5
arch/arm/lib/div64.S

@@ -34,12 +34,12 @@
  *       This is meant to be used by do_div() from include/asm/div64.h only.
  *
  * Input parameters:
- * 	xh-xl	= dividend (clobbered)
- * 	r4	= divisor (preserved)
+ *	xh-xl	= dividend (clobbered)
+ *	r4	= divisor (preserved)
  *
  * Output values:
- * 	yh-yl	= result
- * 	xh	= remainder
+ *	yh-yl	= result
+ *	xh	= remainder
  *
  * Clobbered regs: xl, ip
  */
@@ -85,7 +85,7 @@ UNWIND(.fnstart)
 #endif
 
 	@ The division loop for needed upper bit positions.
- 	@ Break out early if dividend reaches 0.
+	@ Break out early if dividend reaches 0.
 2:	cmp	xh, yl
 	orrcs	yh, yh, ip
 	subscs	xh, xh, yl

+ 3 - 3
arch/arm/lib/lib1funcs.S

@@ -34,7 +34,7 @@
 	mov	\divisor, \divisor, lsl \result
 	mov	\curbit, \curbit, lsl \result
 	mov	\result, #0
-	
+
 #else
 
 	@ Initially shift the divisor left 3 bits if possible,
@@ -48,7 +48,7 @@
 
 	@ Unless the divisor is very big, shift it up in multiples of
 	@ four bits, since this is the amount of unwinding in the main
-	@ division loop.  Continue shifting until the divisor is 
+	@ division loop.  Continue shifting until the divisor is
 	@ larger than the dividend.
 1:	cmp	\divisor, #0x10000000
 	cmplo	\divisor, \dividend
@@ -135,7 +135,7 @@
 
 	@ Unless the divisor is very big, shift it up in multiples of
 	@ four bits, since this is the amount of unwinding in the main
-	@ division loop.  Continue shifting until the divisor is 
+	@ division loop.  Continue shifting until the divisor is
 	@ larger than the dividend.
 1:	cmp	\divisor, #0x10000000
 	cmplo	\divisor, \dividend

+ 0 - 1
arch/arm/mach-at91/armv7/sama7g5_devices.c

@@ -8,4 +8,3 @@ char *get_cpu_name(void)
 {
 	return "SAMA7G5";
 }
-

+ 0 - 1
arch/arm/mach-at91/atmel_sfr.c

@@ -39,4 +39,3 @@ void configure_ddrcfg_input_buffers(bool open)
 	else
 		writel(0, &sfr->ddrcfg);
 }
-

+ 12 - 12
arch/arm/mach-at91/include/mach/at91_mc.h

@@ -16,7 +16,7 @@
 #ifndef __ASSEMBLY__
 
 typedef struct at91_ebi {
-	u32 	csa;		/* 0x00 Chip Select Assignment Register */
+	u32	csa;		/* 0x00 Chip Select Assignment Register */
 	u32	cfgr;		/* 0x04 Configuration Register */
 	u32	reserved[2];
 } at91_ebi_t;
@@ -28,20 +28,20 @@ typedef struct at91_ebi {
 #define AT91_EBI_CSA_CS4A	0x0010
 
 typedef struct at91_sdramc {
-	u32	mr; 	/* 0x00 SDRAMC Mode Register */
-	u32	tr; 	/* 0x04 SDRAMC Refresh Timer Register */
-	u32	cr; 	/* 0x08 SDRAMC Configuration Register */
-	u32	ssr; 	/* 0x0C SDRAMC Self Refresh Register */
-	u32	lpr; 	/* 0x10 SDRAMC Low Power Register */
-	u32	ier; 	/* 0x14 SDRAMC Interrupt Enable Register */
-	u32	idr; 	/* 0x18 SDRAMC Interrupt Disable Register */
-	u32	imr; 	/* 0x1C SDRAMC Interrupt Mask Register */
-	u32	icr; 	/* 0x20 SDRAMC Interrupt Status Register */
+	u32	mr;	/* 0x00 SDRAMC Mode Register */
+	u32	tr;	/* 0x04 SDRAMC Refresh Timer Register */
+	u32	cr;	/* 0x08 SDRAMC Configuration Register */
+	u32	ssr;	/* 0x0C SDRAMC Self Refresh Register */
+	u32	lpr;	/* 0x10 SDRAMC Low Power Register */
+	u32	ier;	/* 0x14 SDRAMC Interrupt Enable Register */
+	u32	idr;	/* 0x18 SDRAMC Interrupt Disable Register */
+	u32	imr;	/* 0x1C SDRAMC Interrupt Mask Register */
+	u32	icr;	/* 0x20 SDRAMC Interrupt Status Register */
 	u32	reserved[3];
 } at91_sdramc_t;
 
 typedef struct at91_smc {
-	u32	csr[8]; 	/* 0x00 SDRAMC Mode Register */
+	u32	csr[8];		/* 0x00 SDRAMC Mode Register */
 } at91_smc_t;
 
 #define AT91_SMC_CSR_RWHOLD(x)		((x & 0x7) << 28)
@@ -60,7 +60,7 @@ typedef struct at91_smc {
 #define AT91_SMC_CSR_NWS(x)		(x & 0x7F)
 
 typedef struct at91_bfc {
-	u32	mr; 	/* 0x00 SDRAMC Mode Register */
+	u32	mr;	/* 0x00 SDRAMC Mode Register */
 } at91_bfc_t;
 
 typedef struct at91_mc {

+ 1 - 1
arch/arm/mach-at91/include/mach/at91_st.h

@@ -24,6 +24,6 @@ typedef struct at91_st {
 
 #define AT91_ST_WDMR_WDV(x)	(x & 0xFFFF)
 #define AT91_ST_WDMR_RSTEN	0x00010000
-#define AT91_ST_WDMR_EXTEN 	0x00020000
+#define AT91_ST_WDMR_EXTEN	0x00020000
 
 #endif

+ 0 - 1
arch/arm/mach-bcm283x/msg.c

@@ -196,4 +196,3 @@ int bcm2711_notify_vl805_reset(void)
 
 	return 0;
 }
-

+ 18 - 18
arch/arm/mach-davinci/include/mach/da8xx-usb.h

@@ -29,22 +29,22 @@
 struct da8xx_usb_regs {
 	dv_reg	revision;
 	dv_reg	control;
-	dv_reg 	status;
-	dv_reg 	emulation;
-	dv_reg 	mode;
-	dv_reg 	autoreq;
-	dv_reg 	srpfixtime;
-	dv_reg 	teardown;
-	dv_reg 	intsrc;
-	dv_reg 	intsrc_set;
-	dv_reg 	intsrc_clr;
-	dv_reg 	intmsk;
-	dv_reg 	intmsk_set;
-	dv_reg 	intmsk_clr;
-	dv_reg 	intsrcmsk;
-	dv_reg 	eoi;
-	dv_reg 	intvector;
-	dv_reg 	grndis_size[4];
+	dv_reg	status;
+	dv_reg	emulation;
+	dv_reg	mode;
+	dv_reg	autoreq;
+	dv_reg	srpfixtime;
+	dv_reg	teardown;
+	dv_reg	intsrc;
+	dv_reg	intsrc_set;
+	dv_reg	intsrc_clr;
+	dv_reg	intmsk;
+	dv_reg	intmsk_set;
+	dv_reg	intmsk_clr;
+	dv_reg	intsrcmsk;
+	dv_reg	eoi;
+	dv_reg	intvector;
+	dv_reg	grndis_size[4];
 };
 
 #define da8xx_usb_regs ((struct da8xx_usb_regs *)DA8XX_USB_OTG_BASE)
@@ -68,13 +68,13 @@ struct da8xx_usb_regs {
 #define CFGCHIP2_OTGMODE	(3 << 13)
 #define CFGCHIP2_NO_OVERRIDE	(0 << 13)
 #define CFGCHIP2_FORCE_HOST	(1 << 13)
-#define CFGCHIP2_FORCE_DEVICE 	(2 << 13)
+#define CFGCHIP2_FORCE_DEVICE	(2 << 13)
 #define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13)
 #define CFGCHIP2_USB1PHYCLKMUX	(1 << 12)
 #define CFGCHIP2_USB2PHYCLKMUX	(1 << 11)
 #define CFGCHIP2_PHYPWRDN	(1 << 10)
 #define CFGCHIP2_OTGPWRDN	(1 << 9)
-#define CFGCHIP2_DATPOL 	(1 << 8)
+#define CFGCHIP2_DATPOL		(1 << 8)
 #define CFGCHIP2_USB1SUSPENDM	(1 << 7)
 #define CFGCHIP2_PHY_PLLON	(1 << 6)	/* override PLL suspend */
 #define CFGCHIP2_SESENDEN	(1 << 5)	/* Vsess_end comparator */

+ 1 - 1
arch/arm/mach-davinci/include/mach/davinci_misc.h

@@ -23,7 +23,7 @@ struct pinmux_config {
 /* pin table definition */
 struct pinmux_resource {
 	const struct pinmux_config	*pins;
-	const int 			n_pins;
+	const int			n_pins;
 };
 
 #define PINMUX_ITEM(item) { \

+ 2 - 2
arch/arm/mach-imx/Makefile

@@ -34,7 +34,7 @@ obj-$(CONFIG_CMD_PRIBLOB) += priblob.o
 obj-$(CONFIG_SPL_BUILD)	+= spl.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx7))
-obj-y 	+= cpu.o
+obj-y	+= cpu.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
 obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
 obj-$(CONFIG_FSL_MFGPROT) += cmd_mfgprot.o
@@ -43,7 +43,7 @@ ifeq ($(SOC),$(filter $(SOC),mx5 mx6 mx7))
 obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx6 mx7))
-obj-y 	+= cache.o init.o
+obj-y	+= cache.o init.o
 obj-$(CONFIG_FEC_MXC) += mac.o
 obj-$(CONFIG_IMX_RDC) += rdc-sema.o
 ifneq ($(CONFIG_SPL_BUILD),y)

+ 0 - 1
arch/arm/mach-imx/mx7/soc.c

@@ -445,4 +445,3 @@ void reset_misc(void)
 #endif
 #endif
 }
-

+ 3 - 3
arch/arm/mach-keystone/include/mach/hardware.h

@@ -148,8 +148,8 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_CIC_HOST_ENABLE_IDX_SET	0x34
 #define KS2_CIC_CHAN_MAP(n)		(0x0400 + (n << 2))
 
-#define KS2_UART0_BASE                	0x02530c00
-#define KS2_UART1_BASE                	0x02531000
+#define KS2_UART0_BASE			0x02530c00
+#define KS2_UART1_BASE			0x02531000
 
 /* Boot Config */
 #define KS2_DEVICE_STATE_CTRL_BASE	0x02620000
@@ -210,7 +210,7 @@ typedef volatile unsigned int   *dv_reg_p;
 #endif
 
 /* AEMIF */
-#define KS2_AEMIF_CNTRL_BASE       	0x21000a00
+#define KS2_AEMIF_CNTRL_BASE		0x21000a00
 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE   KS2_AEMIF_CNTRL_BASE
 
 /* Flag from ks2_debug options to check if DSPs need to stay ON */

+ 0 - 1
arch/arm/mach-kirkwood/cpu.c

@@ -278,4 +278,3 @@ int cpu_eth_init(struct bd_info *bis)
 	return 0;
 }
 #endif
-

+ 0 - 2
arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c

@@ -14,8 +14,6 @@
 #include "sys_env_lib.h"
 #include "ctrl_pex.h"
 
-
-
 /*
  * serdes_seq_db - holds all serdes sequences, their size and the
  * relevant index in the data array initialized in serdes_seq_init

+ 0 - 1
arch/arm/mach-octeontx/Makefile

@@ -6,4 +6,3 @@
 # */
 
 obj-y += lowlevel_init.o clock.o cpu.o
-

+ 0 - 1
arch/arm/mach-octeontx2/Makefile

@@ -6,4 +6,3 @@
 # */
 
 obj-y += lowlevel_init.o clock.o cpu.o
-

+ 1 - 1
arch/arm/mach-omap2/clocks-common.c

@@ -552,7 +552,7 @@ void scale_vcores(struct vcores_data const *vcores)
 		if (pv->value[opp]) {
 			/* Handle non-empty members only */
 			pv->value[opp] = optimize_vcore_voltage(pv, opp);
-     			px = (struct volts *)vcores;
+			px = (struct volts *)vcores;
 			j = 0;
 			while (px < pv) {
 				/*

+ 1 - 1
arch/arm/mach-omap2/omap5/prcm-regs.c

@@ -300,7 +300,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
 	.control_std_fuse_die_id_1		= 0x4A002208,
 	.control_std_fuse_die_id_2		= 0x4A00220C,
 	.control_std_fuse_die_id_3		= 0x4A002210,
-	.control_phy_power_usb 			= 0x4A002370,
+	.control_phy_power_usb			= 0x4A002370,
 	.control_phy_power_sata			= 0x4A002374,
 	.control_padconf_core_base		= 0x4A002800,
 	.control_paconf_global			= 0x4A002DA0,

+ 0 - 1
arch/arm/mach-omap2/pipe3-phy.c

@@ -229,4 +229,3 @@ int phy_pipe3_power_off(struct omap_pipe3 *phy)
 
 	return 0;
 }
-

+ 1 - 1
arch/arm/mach-orion5x/timer.c

@@ -69,7 +69,7 @@ struct orion5x_tmr_registers *orion5x_tmr_regs =
 #define TVR_ARM_TIMER_OFFS		0
 #define TVR_ARM_TIMER_MASK		0xffffffff
 #define TVR_ARM_TIMER_MAX		0xffffffff
-#define TIMER_LOAD_VAL 			0xffffffff
+#define TIMER_LOAD_VAL			0xffffffff
 
 static inline ulong read_timer(void)
 {

+ 1 - 1
arch/arm/mach-rmobile/pfc-r8a7790.h

@@ -82,7 +82,7 @@
 	PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx)
 
 #define CPU_32_PORT0_16(fn, pfx, sfx)				\
-	PORT_10(fn, pfx, sfx), 					\
+	PORT_10(fn, pfx, sfx),					\
 	PORT_1(fn, pfx##10, sfx),PORT_1(fn, pfx##11, sfx),	\
 	PORT_1(fn, pfx##12, sfx), PORT_1(fn, pfx##13, sfx),	\
 	PORT_1(fn, pfx##14, sfx), PORT_1(fn, pfx##15, sfx),	\

+ 1 - 1
arch/arm/mach-rockchip/rk3368/Makefile

@@ -3,4 +3,4 @@
 # Copyright (c) 2016 Andreas Färber
 obj-y		+= clk_rk3368.o
 obj-y		+= rk3368.o
-obj-y 		+= syscon_rk3368.o
+obj-y		+= syscon_rk3368.o

+ 2 - 2
arch/arm/mach-s5pc1xx/include/mach/sromc.h

@@ -4,9 +4,9 @@
  * Naveen Krishna Ch <ch.naveen@samsung.com>
  *
  * Note: This file contains the register description for Memory subsystem
- * 	 (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
+ *	 (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
  *
- * 	 Only SROMC is defined as of now
+ *	 Only SROMC is defined as of now
  */
 
 #ifndef __ASM_ARCH_SROMC_H_

+ 0 - 1
arch/arm/mach-snapdragon/dram.c

@@ -97,4 +97,3 @@ int msm_fixup_memory(void *blob)
 
 	return 0;
 }
-

+ 8 - 8
arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h

@@ -14,8 +14,8 @@
 
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK		BIT(0)
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK	BIT(1)
-#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK 		BIT(2)
-#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK 	BIT(3)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK		BIT(2)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK		BIT(3)
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK		BIT(4)
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK		BIT(5)
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK		BIT(6)
@@ -26,9 +26,9 @@
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK		BIT(11)
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK		BIT(12)
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK		BIT(13)
-#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK    		BIT(16)
-#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK    		BIT(17)
-#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK    		BIT(18)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK		BIT(16)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK		BIT(17)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK		BIT(18)
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\
 	ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\
 	ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\
@@ -50,9 +50,9 @@
 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK	BIT(16)
 #define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK		BIT(24)
 
-#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK    	BIT(0)
-#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK    	BIT(8)
-#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK    		0x00030000
+#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK		BIT(0)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK		BIT(8)
+#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK		0x00030000
 #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK		BIT(24)
 #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB			16
 

+ 1 - 1
arch/arm/mach-sunxi/dram_sun4i.c

@@ -279,7 +279,7 @@ static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
 		reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
 		reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
 		reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11));
-	} else 	{
+	} else {
 		/* any other frequency that is a multiple of 24 */
 		reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
 		reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));

+ 2 - 2
arch/arm/mach-sunxi/dram_sun8i_a33.c

@@ -126,8 +126,8 @@ static void auto_set_timing_para(struct dram_para *para)
 	u32 tdinit3	= (1 * CONFIG_DRAM_CLK) + 1;		/* 1us */
 
 	u8 twtp		= tcwl + 2 + twr;	/* WL + BL / 2 + tWR */
-	u8 twr2rd	= tcwl + 2 + twtr; 	/* WL + BL / 2 + tWTR */
-	u8 trd2wr	= tcl + 2 + 1 - tcwl; 	/* RL + BL / 2 + 2 - WL */
+	u8 twr2rd	= tcwl + 2 + twtr;	/* WL + BL / 2 + tWTR */
+	u8 trd2wr	= tcl + 2 + 1 - tcwl;	/* RL + BL / 2 + 2 - WL */
 
 	/* Set work mode register */
 	mctl_set_cr(para);

+ 1 - 1
arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c

@@ -30,7 +30,7 @@
  * MR1: DLL enabled, output strength RZQ/6, Rtt_norm RZQ/2,
  *	write levelling disabled, TDQS disabled, output buffer enabled
  * MR2: manual full array self refresh, dynamic ODT off,
- * 	CAS write latency (CWL): 8
+ *	CAS write latency (CWL): 8
  */
 static u32 mr_ddr3[7] = {
 	0x00001c70, 0x00000040, 0x00000018, 0x00000000,

+ 0 - 1
arch/arm/mach-tegra/tegra20/display.c

@@ -12,4 +12,3 @@
 #include <asm/arch-tegra/dc.h>
 #include <asm/arch-tegra/clk_rst.h>
 #include <asm/arch-tegra/timer.h>
-

+ 0 - 1
arch/arm/mach-versatile/timer.c

@@ -60,4 +60,3 @@ int timer_init (void)
 
 	return 0;
 }
-

+ 2 - 2
arch/m68k/cpu/mcf5227x/start.S

@@ -37,10 +37,10 @@
 _vectors:
 #if defined(CONFIG_CF_SBF)
 INITSP:	.long	0			/* Initial SP	*/
-INITPC:	.long	ASM_DRAMINIT		/* Initial PC 	*/
+INITPC:	.long	ASM_DRAMINIT		/* Initial PC	*/
 #else
 INITSP:	.long	0			/* Initial SP	*/
-INITPC:	.long	_START			/* Initial PC 	*/
+INITPC:	.long	_START			/* Initial PC	*/
 #endif
 
 vector02_0F:

+ 1 - 1
arch/m68k/cpu/mcf523x/cpu.c

@@ -106,7 +106,7 @@ int watchdog_init(void)
 #if defined(CONFIG_MCFFEC)
 /* Default initializations for MCFFEC controllers.  To override,
  * create a board-specific function called:
- * 	int board_eth_init(struct bd_info *bis)
+ *	int board_eth_init(struct bd_info *bis)
  */
 
 int cpu_eth_init(struct bd_info *bis)

+ 1 - 1
arch/m68k/cpu/mcf52x2/cpu.c

@@ -421,7 +421,7 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 #if defined(CONFIG_MCFFEC)
 /* Default initializations for MCFFEC controllers.  To override,
  * create a board-specific function called:
- * 	int board_eth_init(struct bd_info *bis)
+ *	int board_eth_init(struct bd_info *bis)
  */
 
 int cpu_eth_init(struct bd_info *bis)

+ 0 - 1
arch/m68k/cpu/mcf530x/Makefile

@@ -4,4 +4,3 @@
 
 extra-y	= start.o
 obj-y	= interrupts.o cpu.o speed.o cpu_init.o
-

+ 1 - 1
arch/m68k/cpu/mcf532x/cpu.c

@@ -148,7 +148,7 @@ int watchdog_init(void)
 #if defined(CONFIG_MCFFEC)
 /* Default initializations for MCFFEC controllers.  To override,
  * create a board-specific function called:
- * 	int board_eth_init(struct bd_info *bis)
+ *	int board_eth_init(struct bd_info *bis)
  */
 int cpu_eth_init(struct bd_info *bis)
 {

+ 1 - 1
arch/m68k/cpu/mcf5445x/cpu.c

@@ -110,7 +110,7 @@ int print_cpuinfo(void)
 #if defined(CONFIG_MCFFEC)
 /* Default initializations for MCFFEC controllers.  To override,
  * create a board-specific function called:
- * 	int board_eth_init(struct bd_info *bis)
+ *	int board_eth_init(struct bd_info *bis)
  */
 
 int cpu_eth_init(struct bd_info *bis)

+ 3 - 3
arch/m68k/cpu/mcf5445x/start.S

@@ -44,16 +44,16 @@ _vectors:
 
 INITSP:	.long	0			/* Initial SP	*/
 #ifdef CONFIG_CF_SBF
-INITPC:	.long	ASM_DRAMINIT		/* Initial PC 	*/
+INITPC:	.long	ASM_DRAMINIT		/* Initial PC	*/
 #endif
 #ifdef CONFIG_SYS_NAND_BOOT
-INITPC:	.long	ASM_DRAMINIT_N		/* Initial PC 	*/
+INITPC:	.long	ASM_DRAMINIT_N		/* Initial PC	*/
 #endif
 
 #else
 
 INITSP:	.long	0			/* Initial SP	*/
-INITPC:	.long	_START			/* Initial PC 	*/
+INITPC:	.long	_START			/* Initial PC	*/
 
 #endif
 

+ 0 - 1
arch/m68k/include/asm/immap_5307.h

@@ -114,4 +114,3 @@ typedef struct gpio {
 } gpio_t;
 
 #endif				/* __IMMAP_5307__ */
-

+ 1 - 1
arch/m68k/include/asm/m5271.h

@@ -115,7 +115,7 @@
 #define MCF_GPIO_PAR_TIMER			0x10004C
 
 #define MCF_DSCR_EIM				0x100050
-#define MCF_DCSR_FEC12C 			0x100052
+#define MCF_DCSR_FEC12C				0x100052
 #define MCF_DCSR_UART				0x100053
 #define MCF_DCSR_QSPI				0x100054
 #define MCF_DCSR_TIMER				0x100055

+ 0 - 1
arch/m68k/include/asm/m5307.h

@@ -66,4 +66,3 @@
 #define	MCFSIM_ICR_PRI3		0x03	/* Priority 3 intr */
 
 #endif	/* mcf5307_h */
-

+ 1 - 1
arch/m68k/lib/muldi3.c

@@ -41,7 +41,7 @@
     umul_ppmm (__w.s.high, __w.s.low, u, v);				\
     __w.ll; })
 
-typedef 	 int SItype	__attribute__ ((mode (SI)));
+typedef		 int SItype	__attribute__ ((mode (SI)));
 typedef unsigned int USItype	__attribute__ ((mode (SI)));
 typedef		 int DItype	__attribute__ ((mode (DI)));
 typedef int word_type __attribute__ ((mode (__word__)));

+ 16 - 16
arch/mips/include/asm/mipsregs.h

@@ -2307,8 +2307,8 @@ do {									\
 	"	.set " MIPS_ISA_LEVEL "				\n"	\
 	"	.set dsp					\n"	\
 	"	mflo %0, $ac0					\n"	\
-	"	.set pop					\n" 	\
-	: "=r" (mflo0)); 						\
+	"	.set pop					\n"	\
+	: "=r" (mflo0));						\
 	mflo0;								\
 })
 
@@ -2320,8 +2320,8 @@ do {									\
 	"	.set " MIPS_ISA_LEVEL "				\n"	\
 	"	.set dsp					\n"	\
 	"	mflo %0, $ac1					\n"	\
-	"	.set pop					\n" 	\
-	: "=r" (mflo1)); 						\
+	"	.set pop					\n"	\
+	: "=r" (mflo1));						\
 	mflo1;								\
 })
 
@@ -2333,8 +2333,8 @@ do {									\
 	"	.set " MIPS_ISA_LEVEL "				\n"	\
 	"	.set dsp					\n"	\
 	"	mflo %0, $ac2					\n"	\
-	"	.set pop					\n" 	\
-	: "=r" (mflo2)); 						\
+	"	.set pop					\n"	\
+	: "=r" (mflo2));						\
 	mflo2;								\
 })
 
@@ -2346,8 +2346,8 @@ do {									\
 	"	.set " MIPS_ISA_LEVEL "				\n"	\
 	"	.set dsp					\n"	\
 	"	mflo %0, $ac3					\n"	\
-	"	.set pop					\n" 	\
-	: "=r" (mflo3)); 						\
+	"	.set pop					\n"	\
+	: "=r" (mflo3));						\
 	mflo3;								\
 })
 
@@ -2359,8 +2359,8 @@ do {									\
 	"	.set " MIPS_ISA_LEVEL "				\n"	\
 	"	.set dsp					\n"	\
 	"	mfhi %0, $ac0					\n"	\
-	"	.set pop					\n" 	\
-	: "=r" (mfhi0)); 						\
+	"	.set pop					\n"	\
+	: "=r" (mfhi0));						\
 	mfhi0;								\
 })
 
@@ -2372,8 +2372,8 @@ do {									\
 	"	.set " MIPS_ISA_LEVEL "				\n"	\
 	"	.set dsp					\n"	\
 	"	mfhi %0, $ac1					\n"	\
-	"	.set pop					\n" 	\
-	: "=r" (mfhi1)); 						\
+	"	.set pop					\n"	\
+	: "=r" (mfhi1));						\
 	mfhi1;								\
 })
 
@@ -2385,8 +2385,8 @@ do {									\
 	"	.set " MIPS_ISA_LEVEL "				\n"	\
 	"	.set dsp					\n"	\
 	"	mfhi %0, $ac2					\n"	\
-	"	.set pop					\n" 	\
-	: "=r" (mfhi2)); 						\
+	"	.set pop					\n"	\
+	: "=r" (mfhi2));						\
 	mfhi2;								\
 })
 
@@ -2398,8 +2398,8 @@ do {									\
 	"	.set " MIPS_ISA_LEVEL "				\n"	\
 	"	.set dsp					\n"	\
 	"	mfhi %0, $ac3					\n"	\
-	"	.set pop					\n" 	\
-	: "=r" (mfhi3)); 						\
+	"	.set pop					\n"	\
+	: "=r" (mfhi3));						\
 	mfhi3;								\
 })
 

+ 0 - 1
arch/mips/mach-jz47xx/include/mach/jz4780_dram.h

@@ -454,4 +454,3 @@ void pll_init(void);
 void sdram_init(void);
 
 #endif	/* __JZ4780_DRAM_H__ */
-

+ 3 - 3
arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S

@@ -38,9 +38,9 @@
  * for Orca and Emerald
  */
 #define BOARD_ID_REG		0x104
-#define BOARD_ID_FAMILY_MASK 	0xfff000
-#define BOARD_ID_FAMILY_V5   	0x556000
-#define BOARD_ID_FAMILY_K7   	0x74b000
+#define BOARD_ID_FAMILY_MASK	0xfff000
+#define BOARD_ID_FAMILY_V5	0x556000
+#define BOARD_ID_FAMILY_K7	0x74b000
 
 /*
  * parameters for the static memory controller

+ 3 - 3
arch/nds32/cpu/n1213/ag101/lowlevel_init.S

@@ -38,9 +38,9 @@
  * for Orca and Emerald
  */
 #define BOARD_ID_REG		0x104
-#define BOARD_ID_FAMILY_MASK 	0xfff000
-#define BOARD_ID_FAMILY_V5   	0x556000
-#define BOARD_ID_FAMILY_K7   	0x74b000
+#define BOARD_ID_FAMILY_MASK	0xfff000
+#define BOARD_ID_FAMILY_V5	0x556000
+#define BOARD_ID_FAMILY_K7	0x74b000
 
 /*
  * parameters for the static memory controller

+ 1 - 1
arch/nds32/cpu/n1213/ag101/watchdog.S

@@ -16,7 +16,7 @@ ENTRY(turnoff_watchdog)
 #define WD_ENABLE	0x1
 
 	! Turn off the watchdog, according to Faraday FTWDT010 spec
-	li 	$p0, (CONFIG_FTWDT010_BASE+WD_CR)	! Get the addr of WD CR
+	li	$p0, (CONFIG_FTWDT010_BASE+WD_CR)	! Get the addr of WD CR
 	lwi	$p1, [$p0]				! Get the config of WD
 	andi	$p1, $p1, 0x1f				! Wipe out useless bits
 	li	$r0, ~WD_ENABLE

+ 4 - 4
arch/nds32/cpu/n1213/start.S

@@ -20,7 +20,7 @@
  */
 #define ENA_DCAC		2UL
 #define DIS_DCAC		~ENA_DCAC
-#define ICAC_MEM_KBF_ISET	(0x07)	 	! I Cache sets per way
+#define ICAC_MEM_KBF_ISET	(0x07)		! I Cache sets per way
 #define ICAC_MEM_KBF_IWAY	(0x07<<3)	! I cache ways
 #define ICAC_MEM_KBF_ISZ	(0x07<<6)	! I cache line size
 #define DCAC_MEM_KBF_DSET	(0x07)		! D Cache sets per way
@@ -434,21 +434,21 @@ tlb_fill:
 	SAVE_ALL
 	move	$r0, $sp			! To get the kernel stack
 	li	$r1, 1				! Determine interruption type
-	bal 	do_interruption
+	bal	do_interruption
 
 	.align	5
 tlb_not_present:
 	SAVE_ALL
 	move	$r0, $sp			! To get the kernel stack
 	li	$r1, 2				! Determine interruption type
-	bal 	do_interruption
+	bal	do_interruption
 
 	.align	5
 tlb_misc:
 	SAVE_ALL
 	move	$r0, $sp			! To get the kernel stack
 	li	$r1, 3				! Determine interruption type
-	bal 	do_interruption
+	bal	do_interruption
 
 	.align	5
 tlb_vlpt_miss:

+ 0 - 1
arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c

@@ -399,4 +399,3 @@ const char *serdes_clock_to_string(u32 clock)
 #endif
 	}
 }
-

+ 0 - 1
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c

@@ -885,4 +885,3 @@ const char *serdes_clock_to_string(u32 clock)
 		return "150";
 	}
 }
-

+ 4 - 4
arch/powerpc/cpu/mpc85xx/start.S

@@ -76,7 +76,7 @@
 _start_e500:
 /* Enable debug exception */
 	li	r1,MSR_DE
-	mtmsr 	r1
+	mtmsr	r1
 
 	/*
 	 * If we got an ePAPR device tree pointer passed in as r3, we need that
@@ -1159,9 +1159,9 @@ _start_cont:
 
 	li	r0,0
 
-1: 	subi 	r4,r4,4
-	stw 	r0,0(r4)
-	cmplw 	r4,r3
+1:	subi	r4,r4,4
+	stw	r0,0(r4)
+	cmplw	r4,r3
 	bne	1b
 
 #if CONFIG_VAL(SYS_MALLOC_F_LEN)

+ 2 - 2
arch/powerpc/include/asm/fsl_lbc.h

@@ -294,8 +294,8 @@ void lbc_sdram_init(void);
 #define LBCR_EPAR_SHIFT			16
 #define LBCR_BMT			0x0000FF00
 #define LBCR_BMT_SHIFT			8
-#define LBCR_BMTPS	 		0x0000000F
-#define LBCR_BMTPS_SHIFT 		0
+#define LBCR_BMTPS			0x0000000F
+#define LBCR_BMTPS_SHIFT		0
 
 /* LCRR - Clock Ratio Register
  */

+ 2 - 2
arch/powerpc/include/asm/immap_85xx.h

@@ -1510,7 +1510,7 @@ typedef struct par_io {
  */
 
 typedef struct cpc_corenet {
-	u32 	cpccsr0;	/* Config/status reg */
+	u32	cpccsr0;	/* Config/status reg */
 	u32	res1;
 	u32	cpccfg0;	/* Configuration register */
 	u32	res2;
@@ -1573,7 +1573,7 @@ typedef struct cpc_corenet {
 #define CPC_SRCR0_SRAMSZ_16_WAY	0x00000008
 #define CPC_SRCR0_SRAMSZ_32_WAY	0x0000000a
 #define CPC_SRCR0_SRAMEN	0x00000001
-#define	CPC_ERRDIS_TMHITDIS  	0x00000080	/* multi-way hit disable */
+#define	CPC_ERRDIS_TMHITDIS	0x00000080	/* multi-way hit disable */
 #define CPC_HDBCR0_CDQ_SPEC_DIS	0x08000000
 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS	0x01000000
 #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS	0x00400000

+ 1 - 1
arch/powerpc/include/asm/processor.h

@@ -748,7 +748,7 @@
 #define MAS5	SPRN_MAS5
 #define MAS6	SPRN_MAS6
 #define MAS7	SPRN_MAS7
-#define MAS8 	SPRN_MAS8
+#define MAS8	SPRN_MAS8
 
 #if defined(CONFIG_MPC85xx)
 #define DAR_DEAR DEAR

+ 0 - 1
arch/powerpc/lib/ppccache.S

@@ -104,4 +104,3 @@ _GLOBAL(invalidate_dcache_range)
 	sync				/* wait for dcbi's to get to ram */
 #endif
 	blr
-

+ 1 - 1
arch/sandbox/include/asm/gpio.h

@@ -65,7 +65,7 @@ int sandbox_gpio_get_direction(struct udevice *dev, unsigned int offset);
  *
  * @param dev		device to use
  * @param offset	GPIO offset within bank
- * @param output 	0 to set as input, 1 to set as output
+ * @param output	0 to set as input, 1 to set as output
  * @return -1 on error, 0 if ok
  */
 int sandbox_gpio_set_direction(struct udevice *dev, unsigned int offset,

+ 0 - 1
arch/sh/lib/time.c

@@ -32,4 +32,3 @@ int timer_init(void)
 
 	return 0;
 }
-

+ 1 - 1
arch/x86/cpu/intel_common/car2.S

@@ -88,7 +88,7 @@ clear_var_mtrr:
 	 *  MTRR_PHYS_MASK_HIGH = 0000000FFh  For 40 bit addressing
 	 */
 
-	movl	$0x80000008, %eax 	/* Address sizes leaf */
+	movl	$0x80000008, %eax	/* Address sizes leaf */
 	cpuid
 	sub	$32, %al
 	movzx	%al, %eax

+ 2 - 2
arch/x86/lib/bios_asm.S

@@ -22,8 +22,8 @@
 	.globl __idt_handler
 __idt_handler:
 	pushal
-	movb 	$0, %al /* This instruction gets modified */
-	ljmp 	$0, $__interrupt_handler_16bit
+	movb	$0, %al /* This instruction gets modified */
+	ljmp	$0, $__interrupt_handler_16bit
 	.globl __idt_handler_size
 __idt_handler_size:
 	.long  . - __idt_handler

+ 0 - 3
arch/xtensa/include/asm/arch-dc232b/core.h

@@ -127,8 +127,6 @@
 #define XCHAL_DCACHE_IS_WRITEBACK	1	/* writeback feature */
 
 
-
-
 /****************************************************************************
     Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
  ****************************************************************************/
@@ -419,4 +417,3 @@
 
 
 #endif /* _XTENSA_CORE_CONFIGURATION_H */
-

+ 0 - 5
arch/xtensa/include/asm/arch-dc232b/tie-asm.h

@@ -26,7 +26,6 @@
 #define XTHAL_SAS_ALL	0xFFFF	/* include all default NCP contents */
 
 
-
 /* Macro to save all non-coprocessor (extra) custom TIE and optional state
  * (not including zero-overhead loop registers).
  * Save area ptr (clobbered):  ptr  (1 byte aligned)
@@ -109,12 +108,8 @@
 	.endif
 	.endm	// xchal_ncp_load
 
-
-
 #define XCHAL_NCP_NUM_ATMPS	2
 
-
 #define XCHAL_SA_NUM_ATMPS	2
 
 #endif /*_XTENSA_CORE_TIE_ASM_H*/
-

+ 0 - 1
arch/xtensa/include/asm/arch-dc232b/tie.h

@@ -126,4 +126,3 @@
 #define XCHAL_OP0_FORMAT_LENGTHS	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
 
 #endif /*_XTENSA_CORE_TIE_H*/
-

+ 22 - 26
arch/xtensa/include/asm/arch-dc233c/core.h

@@ -149,13 +149,10 @@
 #define XCHAL_HAVE_PREFETCH		0	/* PREFCTL register */
 
 
-
-
 /****************************************************************************
     Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
  ****************************************************************************/
 
-
 #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
 
 /*----------------------------------------------------------------------
@@ -266,28 +263,28 @@
 						   EXCSAVE/EPS/EPC_n, RFI n) */
 
 /*  Type of each interrupt:  */
-#define XCHAL_INT0_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT1_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT2_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT3_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT4_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT5_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT6_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT7_TYPE 	XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT8_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT9_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT10_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT11_TYPE 	XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT12_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT13_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT14_TYPE 	XTHAL_INTTYPE_NMI
-#define XCHAL_INT15_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT16_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT17_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT18_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT19_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT20_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT21_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT0_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT1_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT2_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT3_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT4_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT5_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT6_TYPE		XTHAL_INTTYPE_TIMER
+#define XCHAL_INT7_TYPE		XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT8_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT9_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT10_TYPE	XTHAL_INTTYPE_TIMER
+#define XCHAL_INT11_TYPE	XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT12_TYPE	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT13_TYPE	XTHAL_INTTYPE_TIMER
+#define XCHAL_INT14_TYPE	XTHAL_INTTYPE_NMI
+#define XCHAL_INT15_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT16_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT17_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT18_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT19_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT20_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT21_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
 
 /*  Masks of interrupts for each type of interrupt:  */
 #define XCHAL_INTTYPE_MASK_UNCONFIGURED	0xFFC00000
@@ -450,4 +447,3 @@
 
 
 #endif /* _XTENSA_CORE_CONFIGURATION_H */
-

+ 0 - 5
arch/xtensa/include/asm/arch-dc233c/tie-asm.h

@@ -31,8 +31,6 @@
 					| ((ccuse) & XTHAL_SAS_ANYCC)  \
 					| ((abi)   & XTHAL_SAS_ANYABI) )
 
-
-
     /*
      *  Macro to save all non-coprocessor (extra) custom TIE and optional state
      *  (not including zero-overhead loop registers).
@@ -164,9 +162,6 @@
 
 #define XCHAL_NCP_NUM_ATMPS	1
 
-
-
 #define XCHAL_SA_NUM_ATMPS	1
 
 #endif /*_XTENSA_CORE_TIE_ASM_H*/
-

+ 0 - 1
arch/xtensa/include/asm/arch-dc233c/tie.h

@@ -126,4 +126,3 @@
 #define XCHAL_OP0_FORMAT_LENGTHS	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
 
 #endif /*_XTENSA_CORE_TIE_H*/
-

+ 27 - 31
arch/xtensa/include/asm/arch-de212/core.h

@@ -89,7 +89,7 @@
 #define XCHAL_HAVE_HIFI3_VFPU		0	/* HiFi3 Audio Engine VFPU option */
 #define XCHAL_HAVE_HIFI2		0	/* HiFi2 Audio Engine pkg */
 #define XCHAL_HAVE_HIFI2EP		0	/* HiFi2EP */
-#define XCHAL_HAVE_HIFI_MINI		0	
+#define XCHAL_HAVE_HIFI_MINI		0
 
 
 #define XCHAL_HAVE_VECTORFPU2005	0	/* vector or user floating-point pkg */
@@ -108,8 +108,8 @@
 #define XCHAL_HAVE_DFP_ACCEL		0	/* double precision FP acceleration pkg */
 #define XCHAL_HAVE_DFP_accel		XCHAL_HAVE_DFP_ACCEL				/* for backward compatibility */
 
-#define XCHAL_HAVE_DFPU_SINGLE_ONLY    0                 	/* DFPU Coprocessor, single precision only */
-#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE  0               	/* DFPU Coprocessor, single and double precision */
+#define XCHAL_HAVE_DFPU_SINGLE_ONLY	0	/* DFPU Coprocessor, single precision only */
+#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE	0	/* DFPU Coprocessor, single and double precision */
 #define XCHAL_HAVE_VECTRA1		0	/* Vectra I  pkg */
 #define XCHAL_HAVE_VECTRALX		0	/* Vectra LX pkg */
 #define XCHAL_HAVE_PDX4		        0	/* PDX4 */
@@ -127,8 +127,8 @@
 #define XCHAL_HAVE_TURBO16		0	/* ConnX Turbo16 pkg */
 #define XCHAL_HAVE_BBP16		0	/* ConnX BBP16 pkg */
 #define XCHAL_HAVE_FLIX3		0	/* basic 3-way FLIX option */
-#define XCHAL_HAVE_GRIVPEP              0   /*  GRIVPEP is General Release of IVPEP */
-#define XCHAL_HAVE_GRIVPEP_HISTOGRAM    0   /* Histogram option on GRIVPEP */
+#define XCHAL_HAVE_GRIVPEP              0	/*  GRIVPEP is General Release of IVPEP */
+#define XCHAL_HAVE_GRIVPEP_HISTOGRAM    0	/* Histogram option on GRIVPEP */
 
 
 /*----------------------------------------------------------------------
@@ -206,13 +206,10 @@
 #define XCHAL_HAVE_DCACHE_DYN_WAYS	0	/* Dcache dynamic way support */
 
 
-
-
 /****************************************************************************
     Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
  ****************************************************************************/
 
-
 #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
 
 /*----------------------------------------------------------------------
@@ -351,28 +348,28 @@
 						   EXCSAVE/EPS/EPC_n, RFI n) */
 
 /*  Type of each interrupt:  */
-#define XCHAL_INT0_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT1_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT2_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT3_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT4_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT5_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT6_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT7_TYPE 	XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT8_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT9_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT10_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT11_TYPE 	XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT12_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT13_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT14_TYPE 	XTHAL_INTTYPE_NMI
-#define XCHAL_INT15_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT16_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT17_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT18_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT19_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT20_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT21_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT0_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT1_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT2_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT3_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT4_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT5_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT6_TYPE		XTHAL_INTTYPE_TIMER
+#define XCHAL_INT7_TYPE		XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT8_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT9_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT10_TYPE	XTHAL_INTTYPE_TIMER
+#define XCHAL_INT11_TYPE	XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT12_TYPE	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT13_TYPE	XTHAL_INTTYPE_TIMER
+#define XCHAL_INT14_TYPE	XTHAL_INTTYPE_NMI
+#define XCHAL_INT15_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT16_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT17_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT18_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT19_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT20_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT21_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
 
 /*  Masks of interrupts for each type of interrupt:  */
 #define XCHAL_INTTYPE_MASK_UNCONFIGURED	0xFFC00000
@@ -569,4 +566,3 @@
 
 
 #endif /* _XTENSA_CORE_CONFIGURATION_H */
-

+ 0 - 1
arch/xtensa/include/asm/arch-de212/tie-asm.h

@@ -146,4 +146,3 @@
 #define XCHAL_SA_NUM_ATMPS	1
 
 #endif /*_XTENSA_CORE_TIE_ASM_H*/
-

+ 0 - 1
arch/xtensa/include/asm/arch-de212/tie.h

@@ -112,4 +112,3 @@
 	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
 
 #endif /*_XTENSA_CORE_TIE_H*/
-

+ 0 - 2
arch/xtensa/include/asm/cacheasm.h

@@ -134,7 +134,6 @@
 	.endm
 
 
-
 	.macro	___flush_invalidate_dcache_range ar as at
 
 #if XCHAL_DCACHE_SIZE
@@ -171,7 +170,6 @@
 	.endm
 
 
-
 	.macro	___flush_invalidate_dcache_page ar as
 
 #if XCHAL_DCACHE_SIZE

+ 0 - 1
arch/xtensa/include/asm/regs.h

@@ -91,4 +91,3 @@
 #define DEBUGCAUSE_ICOUNT_BIT		0	/* ICOUNT would incr. to zero */
 
 #endif /* _XTENSA_SPECREG_H */
-

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