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@@ -89,7 +89,7 @@
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#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
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#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
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#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
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-#define XCHAL_HAVE_HIFI_MINI 0
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+#define XCHAL_HAVE_HIFI_MINI 0
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#define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */
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@@ -108,8 +108,8 @@
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#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */
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#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
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-#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */
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-#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
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+#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */
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+#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
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#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
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#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
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#define XCHAL_HAVE_PDX4 0 /* PDX4 */
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@@ -127,8 +127,8 @@
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#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
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#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
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#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
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-#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */
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-#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
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+#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */
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+#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
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/*----------------------------------------------------------------------
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@@ -206,13 +206,10 @@
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#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
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-
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-
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/****************************************************************************
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Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
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****************************************************************************/
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-
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#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
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/*----------------------------------------------------------------------
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@@ -351,28 +348,28 @@
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EXCSAVE/EPS/EPC_n, RFI n) */
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/* Type of each interrupt: */
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-#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
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-#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
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-#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
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-#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
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-#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
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-#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
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-#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
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-#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
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-#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
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-#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
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-#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
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-#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
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-#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
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-#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
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-#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
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-#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE
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-#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE
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-#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE
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-#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE
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-#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE
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-#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE
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-#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE
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+#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
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+#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
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+#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
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+#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
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+#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
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+#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
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+#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
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+#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
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+#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
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+#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
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+#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
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+#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
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+#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
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+#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
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+#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
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+#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE
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+#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE
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+#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE
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+#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE
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+#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE
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+#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE
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+#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE
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/* Masks of interrupts for each type of interrupt: */
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#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000
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@@ -569,4 +566,3 @@
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#endif /* _XTENSA_CORE_CONFIGURATION_H */
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-
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