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driver:qspi: Switch the QSPI parent clock to pll0

Switch the QSPI parent clock to pll0 to improve the QSPI speed

Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Samin Guo hai 1 ano
pai
achega
bf2eae30d4
Modificáronse 2 ficheiros con 5 adicións e 2 borrados
  1. 4 1
      board/starfive/evb/spl.c
  2. 1 1
      configs/starfive_evb_defconfig

+ 4 - 1
board/starfive/evb/spl.c

@@ -89,7 +89,10 @@ void board_init_f(ulong dummy)
 		CLK_AON_APB_FUNC_SW_MASK,
 		BIT(CLK_AON_APB_FUNC_SW_SHIFT) & CLK_AON_APB_FUNC_SW_MASK);
 
-
+	/* switch qspi clk to pll0 */
+	clrsetbits_le32(SYS_CRG_BASE + CLK_QSPI_REF_OFFSET,
+			CLK_QSPI_REF_SW_MASK,
+			BIT(CLK_QSPI_REF_SW_SHIFT) & CLK_QSPI_REF_SW_MASK);
 
 	/*set GPIO to 1.8v*/
 	setbits_le32(SYS_SYSCON_BASE + 0xC, 0xf);

+ 1 - 1
configs/starfive_evb_defconfig

@@ -65,7 +65,7 @@ CONFIG_SPL_CLK_JH7110=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_SNPS=y
 CONFIG_SF_DEFAULT_MODE=0x0
-CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_SF_DEFAULT_SPEED=100000000
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_PHY_MARVELL=y