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@@ -0,0 +1,507 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * Starfive PLDA PCIe host controller driver
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+ *
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+ * Copyright (c) 2023 Starfive, Inc.
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+ * Author: Mason Huo <mason.huo@starfivetech.com>
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+ *
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+ */
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+
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+#include <common.h>
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+#include <clk.h>
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+#include <dm.h>
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+#include <asm/global_data.h>
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+#include <dm/device_compat.h>
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+#include <dm/pinctrl.h>
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+#include <generic-phy.h>
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+#include <pci.h>
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+#include <power-domain.h>
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+#include <power/regulator.h>
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+#include <regmap.h>
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+#include <reset.h>
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+#include <syscon.h>
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+#include <asm/io.h>
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+#include <asm-generic/gpio.h>
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+#include <linux/delay.h>
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+#include <linux/iopoll.h>
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+#define GEN_SETTINGS 0x80
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+#define PCIE_PCI_IDS 0x9C
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+#define PCIE_WINROM 0xFC
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+#define PMSG_SUPPORT_RX 0x3F0
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+#define PCI_MISC 0xB4
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+
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+#define PLDA_EP_ENABLE 0
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+#define PLDA_RP_ENABLE 1
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+
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+#define IDS_REVISION_ID 0x02
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+#define IDS_PCI_TO_PCI_BRIDGE 0x060400
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+#define IDS_CLASS_CODE_SHIFT 8
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+
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+#define PREF_MEM_WIN_64_SUPPORT BIT(3)
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+#define PMSG_LTR_SUPPORT BIT(2)
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+#define PLDA_FUNCTION_DIS BIT(15)
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+#define PLDA_FUNC_NUM 4
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+#define PLDA_PHY_FUNC_SHIFT 9
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+
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+#define XR3PCI_ATR_AXI4_SLV0 0x800
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+#define XR3PCI_ATR_SRC_ADDR_LOW 0x0
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+#define XR3PCI_ATR_SRC_ADDR_HIGH 0x4
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+#define XR3PCI_ATR_TRSL_ADDR_LOW 0x8
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+#define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc
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+#define XR3PCI_ATR_TRSL_PARAM 0x10
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+#define XR3PCI_ATR_TABLE_OFFSET 0x20
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+#define XR3PCI_ATR_MAX_TABLE_NUM 8
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+
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+#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT 1
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+#define XR3PCI_ATR_SRC_ADDR_MASK 0xfffff000
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+#define XR3PCI_ATR_TRSL_ADDR_MASK 0xfffff000
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+#define XR3_PCI_ECAM_SIZE 28
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+#define XR3PCI_ATR_TRSL_DIR BIT(22)
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+/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
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+#define XR3PCI_ATR_TRSLID_PCIE_MEMORY 0x0
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+#define XR3PCI_ATR_TRSLID_PCIE_CONFIG 0x1
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+
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+#define ECAM_BUS_SHIFT 20
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+#define ECAM_DEV_SHIFT 15
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+#define ECAM_FUNC_SHIFT 12
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+/* Secondary bus number offset in config space */
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+#define PCI_SECONDARY_BUS 0x19
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+
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+/* system control */
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+#define STG_SYSCON_K_RP_NEP_SHIFT 0x8
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+#define STG_SYSCON_K_RP_NEP_MASK 0x100
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+#define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK 0x7FFF00
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+#define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT 0x8
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+#define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK 0x7FFF
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+#define STG_SYSCON_AXI4_SLVL_AWFUNC_SHIFT 0x0
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+#define STG_SYSCON_CLKREQ_SHIFT 0x16
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+#define STG_SYSCON_CLKREQ_MASK 0x400000
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+#define STG_SYSCON_CKREF_SRC_SHIFT 0x12
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+#define STG_SYSCON_CKREF_SRC_MASK 0xC0000
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+
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+struct starfive_pcie {
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+ struct udevice *dev;
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+
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+ void __iomem *reg_base;
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+ void __iomem *cfg_base;
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+
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+ struct regmap *regmap;
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+ u32 stg_arfun;
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+ u32 stg_awfun;
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+ u32 stg_rp_nep;
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+
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+ struct clk_bulk clks;
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+ struct reset_ctl_bulk rsts;
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+
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+ int atr_table_num;
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+ int first_busno;
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+};
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+
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+static int starfive_pcie_addr_valid(pci_dev_t bdf, int first_busno)
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+{
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+ if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0))
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+ return 0;
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+ if ((PCI_BUS(bdf) == first_busno + 1) && (PCI_DEV(bdf) > 0))
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+ return 0;
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+
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+ return 1;
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+}
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+
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+static int starfive_pcie_off_conf(pci_dev_t bdf, uint offset)
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+{
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+ unsigned int bus = PCI_BUS(bdf);
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+ unsigned int dev = PCI_DEV(bdf);
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+ unsigned int func = PCI_FUNC(bdf);
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+
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+ return (bus << ECAM_BUS_SHIFT) | (dev << ECAM_DEV_SHIFT) |
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+ (func << ECAM_FUNC_SHIFT) | (offset & ~0x3);
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+}
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+
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+static bool plda_pcie_hide_rc_bar(pci_dev_t bdf, int offset)
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+{
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+ if ((PCI_BUS(bdf) == 0) &&
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+ (offset == PCI_BASE_ADDRESS_0 || offset == PCI_BASE_ADDRESS_1))
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+ return true;
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+
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+ return false;
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+}
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+
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+static int starfive_pcie_config_read(const struct udevice *udev, pci_dev_t bdf,
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+ uint offset, ulong *valuep,
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+ enum pci_size_t size)
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+{
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+ void __iomem *addr;
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+ ulong value;
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+ struct starfive_pcie *priv = dev_get_priv(udev);
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+ int where = starfive_pcie_off_conf(bdf, offset);
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+
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+ if (!starfive_pcie_addr_valid(bdf, priv->first_busno)) {
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+ pr_debug("Out of range\n");
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+ *valuep = pci_get_ff(size);
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+ return 0;
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+ }
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+
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+ addr = priv->cfg_base;
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+ addr += where;
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+
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+ if (!addr)
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+ return -1;
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+
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+ /* Make sure the LAST TLP is finished, before reading vendor ID. */
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+ if (offset == PCI_VENDOR_ID)
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+ mdelay(20);
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+
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+ value = readl(addr);
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+ *valuep = pci_conv_32_to_size(value, offset, size);
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+
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+ return 0;
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+
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+}
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+
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+int starfive_pcie_config_write(struct udevice *udev, pci_dev_t bdf,
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+ uint offset, ulong value,
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+ enum pci_size_t size)
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+{
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+ void __iomem *addr;
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+ ulong old;
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+ struct starfive_pcie *priv = dev_get_priv(udev);
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+ int where = starfive_pcie_off_conf(bdf, offset);
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+
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+ if (plda_pcie_hide_rc_bar(bdf, offset))
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+ return -1;
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+
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+ if (!starfive_pcie_addr_valid(bdf, priv->first_busno)) {
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+ pr_debug("Out of range\n");
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+ return 0;
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+ }
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+
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+ addr = priv->cfg_base;
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+ addr += where;
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+
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+ if (!addr)
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+ return -1;
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+
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+ old = readl(addr);
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+ value = pci_conv_size_to_32(old, value, offset, size);
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+ writel(value, addr);
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+
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+ return 0;
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+}
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+
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+
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+static void starfive_pcie_set_atr_entry(struct starfive_pcie *priv, phys_addr_t src_addr,
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+ phys_addr_t trsl_addr, size_t window_size,
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+ int trsl_param)
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+{
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+ void __iomem *base =
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+ priv->reg_base + XR3PCI_ATR_AXI4_SLV0;
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+
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+ /* Support AXI4 Slave 0 Address Translation Tables 0-7. */
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+ if (priv->atr_table_num >= XR3PCI_ATR_MAX_TABLE_NUM)
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+ priv->atr_table_num = XR3PCI_ATR_MAX_TABLE_NUM - 1;
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+ base += XR3PCI_ATR_TABLE_OFFSET * priv->atr_table_num;
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+ priv->atr_table_num++;
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+
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+ /* X3PCI_ATR_SRC_ADDR_LOW:
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+ * - bit 0: enable entry,
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+ * - bits 1-6: ATR window size: total size in bytes: 2^(ATR_WSIZE + 1)
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+ * - bits 7-11: reserved
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+ * - bits 12-31: start of source address
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+ */
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+ writel((lower_32_bits(src_addr) & XR3PCI_ATR_SRC_ADDR_MASK) |
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+ (fls(window_size) - 1) << XR3PCI_ATR_SRC_WIN_SIZE_SHIFT | 1,
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+ base + XR3PCI_ATR_SRC_ADDR_LOW);
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+ writel(upper_32_bits(src_addr), base + XR3PCI_ATR_SRC_ADDR_HIGH);
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+ writel((lower_32_bits(trsl_addr) & XR3PCI_ATR_TRSL_ADDR_MASK),
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+ base + XR3PCI_ATR_TRSL_ADDR_LOW);
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+ writel(upper_32_bits(trsl_addr), base + XR3PCI_ATR_TRSL_ADDR_HIGH);
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+ writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM);
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+
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+ dev_info(priv->dev, "ATR entry: 0x%010llx %s 0x%010llx [0x%010llx] (param: 0x%06x)\n",
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+ src_addr, (trsl_param & XR3PCI_ATR_TRSL_DIR) ? "<-" : "->",
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+ trsl_addr, (u64)window_size, trsl_param);
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+}
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+
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+static int starfive_pcie_atr_init(struct starfive_pcie *priv)
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+{
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+ struct udevice *ctlr = pci_get_controller(priv->dev);
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+ struct pci_controller *hose = dev_get_uclass_priv(ctlr);
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+ int i;
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+
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+ /* As the two host bridges in JH7110 soc have the same default
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+ * address translation table, this cause the second root port can't
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+ * access it's host bridge config space correctly.
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+ * To workaround, config the ATR of host bridge config space by SW.
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+ */
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+ starfive_pcie_set_atr_entry(priv,
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+ (phys_addr_t)priv->cfg_base,
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+ 0,
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+ 1 << XR3_PCI_ECAM_SIZE,
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+ XR3PCI_ATR_TRSLID_PCIE_CONFIG);
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+
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+ for (i = 0; i < hose->region_count; i++) {
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+ if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY)
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+ continue;
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+
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+ /* Only support identity mappings. */
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+ if (hose->regions[i].bus_start !=
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+ hose->regions[i].phys_start)
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+ return -EINVAL;
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+
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+ starfive_pcie_set_atr_entry(priv,
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+ hose->regions[i].phys_start,
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+ hose->regions[i].bus_start,
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+ hose->regions[i].size,
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+ XR3PCI_ATR_TRSLID_PCIE_MEMORY);
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+
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+ }
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+
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+ return 0;
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+}
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+
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+static int starfive_pcie_get_syscon(struct udevice *dev)
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+{
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+ struct starfive_pcie *priv = dev_get_priv(dev);
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+ struct udevice *syscon;
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+ struct ofnode_phandle_args syscfg_phandle;
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+ u32 cells[4];
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+ int ret;
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+
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+ /* get corresponding syscon phandle */
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+ ret = dev_read_phandle_with_args(dev, "starfive,stg-syscon", NULL, 0, 0,
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+ &syscfg_phandle);
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+
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+ if (ret < 0) {
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+ dev_err(dev, "Can't get syscfg phandle: %d\n", ret);
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+ return ret;
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+ }
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+
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+ ret = uclass_get_device_by_ofnode(UCLASS_SYSCON, syscfg_phandle.node,
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+ &syscon);
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+ if (ret) {
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+ dev_err(dev, "Unable to find syscon device (%d)\n", ret);
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+ return ret;
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+ }
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+
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+ priv->regmap = syscon_get_regmap(syscon);
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+ if (!priv->regmap) {
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+ dev_err(dev, "Unable to find regmap\n");
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+ return -ENODEV;
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+ }
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+
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+ /* get syscon register offset */
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+ ret = dev_read_u32_array(dev, "starfive,stg-syscon",
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+ cells, ARRAY_SIZE(cells));
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+ if (ret) {
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+ dev_err(dev, "Get syscon register count err %d\n", ret);
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+ return -EINVAL;
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+ }
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+
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+ dev_dbg(dev, "Get syscon values: %x, %x, %x\n",
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+ cells[1], cells[2], cells[3]);
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+ priv->stg_arfun = cells[1];
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+ priv->stg_awfun = cells[2];
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+ priv->stg_rp_nep = cells[3];
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+
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+ return 0;
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+}
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+
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+static int starfive_pcie_parse_dt(struct udevice *dev)
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+{
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+ struct starfive_pcie *priv = dev_get_priv(dev);
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+ int ret;
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+
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+ priv->reg_base = (void *)dev_read_addr_name(dev, "reg");
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+ if (priv->reg_base == (void __iomem *)FDT_ADDR_T_NONE) {
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+ dev_err(dev, "Missing required reg address range\n");
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+ return -EINVAL;
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+ }
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+
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+ priv->cfg_base = (void *)dev_read_addr_name(dev, "config");
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+ if (priv->cfg_base == (void __iomem *)FDT_ADDR_T_NONE) {
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+ dev_err(dev, "Missing required config address range");
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+ return -EINVAL;
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+ }
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+
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+ ret = starfive_pcie_get_syscon(dev);
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+ if (ret) {
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+ dev_err(dev, "Can't get syscon: %d\n", ret);
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+ return ret;
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+ }
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+
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+ ret = reset_get_bulk(dev, &priv->rsts);
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+ if (ret) {
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+ dev_err(dev, "Can't get reset: %d\n", ret);
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+ return ret;
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+ }
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+
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+ ret = clk_get_bulk(dev, &priv->clks);
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+ if (ret) {
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+ dev_err(dev, "Can't get clock: %d\n", ret);
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+ return ret;
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+ }
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+
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+ return 0;
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+}
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+
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+static int starfive_pcie_init_port(struct udevice *dev)
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+{
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+ int ret, i;
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+ unsigned int value;
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+ struct starfive_pcie *priv = dev_get_priv(dev);
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+
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+ ret = clk_enable_bulk(&priv->clks);
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+ if (ret) {
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+ dev_err(dev, "Failed to enable clks (ret=%d)\n", ret);
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+ return ret;
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+ }
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+
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+ ret = reset_deassert_bulk(&priv->rsts);
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+ if (ret) {
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+ dev_err(dev, "Failed to deassert resets (ret=%d)\n", ret);
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+ goto err_deassert_clk;
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+ }
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+
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+ ret = pinctrl_select_state(dev, "power-active");
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+ if (ret) {
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+ dev_err(dev, "Set power-acvtive pinctrl failed: %d\n", ret);
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+ goto err_deassert_reset;
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+ }
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+ ret = pinctrl_select_state(dev, "perst-active");
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+ if (ret) {
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+ dev_err(dev, "Set perst-active pinctrl failed: %d\n", ret);
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+ goto err_release_power_pin;
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+ }
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+
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+ /* Disable physical functions except #0 */
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+ for (i = 1; i < PLDA_FUNC_NUM; i++) {
|
|
|
+ regmap_update_bits(priv->regmap,
|
|
|
+ priv->stg_arfun,
|
|
|
+ STG_SYSCON_AXI4_SLVL_ARFUNC_MASK,
|
|
|
+ (i << PLDA_PHY_FUNC_SHIFT) <<
|
|
|
+ STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT);
|
|
|
+ regmap_update_bits(priv->regmap,
|
|
|
+ priv->stg_awfun,
|
|
|
+ STG_SYSCON_AXI4_SLVL_AWFUNC_MASK,
|
|
|
+ (i << PLDA_PHY_FUNC_SHIFT) <<
|
|
|
+ STG_SYSCON_AXI4_SLVL_AWFUNC_SHIFT);
|
|
|
+
|
|
|
+ value = readl(priv->reg_base + PCI_MISC);
|
|
|
+ value |= PLDA_FUNCTION_DIS;
|
|
|
+ writel(value, priv->reg_base + PCI_MISC);
|
|
|
+ }
|
|
|
+
|
|
|
+ regmap_update_bits(priv->regmap,
|
|
|
+ priv->stg_arfun,
|
|
|
+ STG_SYSCON_AXI4_SLVL_ARFUNC_MASK,
|
|
|
+ 0 << STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT);
|
|
|
+ regmap_update_bits(priv->regmap,
|
|
|
+ priv->stg_awfun,
|
|
|
+ STG_SYSCON_AXI4_SLVL_AWFUNC_MASK,
|
|
|
+ 0 << STG_SYSCON_AXI4_SLVL_AWFUNC_SHIFT);
|
|
|
+
|
|
|
+ /* Enable root port*/
|
|
|
+ value = readl(priv->reg_base + GEN_SETTINGS);
|
|
|
+ value |= PLDA_RP_ENABLE;
|
|
|
+ writel(value, priv->reg_base + GEN_SETTINGS);
|
|
|
+
|
|
|
+ /* PCIe PCI Standard Configuration Identification Settings. */
|
|
|
+ value = (IDS_PCI_TO_PCI_BRIDGE << IDS_CLASS_CODE_SHIFT) | IDS_REVISION_ID;
|
|
|
+ writel(value, priv->reg_base + PCIE_PCI_IDS);
|
|
|
+
|
|
|
+ /* The LTR message forwarding of PCIe Message Reception was set by core
|
|
|
+ * as default, but the forward id & addr are also need to be reset.
|
|
|
+ * If we do not disable LTR message forwarding here, or set a legal
|
|
|
+ * forwarding address, the kernel will get stuck after this driver probe.
|
|
|
+ * To workaround, disable the LTR message forwarding support on
|
|
|
+ * PCIe Message Reception.
|
|
|
+ */
|
|
|
+ value = readl(priv->reg_base + PMSG_SUPPORT_RX);
|
|
|
+ value &= ~PMSG_LTR_SUPPORT;
|
|
|
+ writel(value, priv->reg_base + PMSG_SUPPORT_RX);
|
|
|
+
|
|
|
+ /* Prefetchable memory window 64-bit addressing support */
|
|
|
+ value = readl(priv->reg_base + PCIE_WINROM);
|
|
|
+ value |= PREF_MEM_WIN_64_SUPPORT;
|
|
|
+ writel(value, priv->reg_base + PCIE_WINROM);
|
|
|
+
|
|
|
+ starfive_pcie_atr_init(priv);
|
|
|
+
|
|
|
+ /* Ensure that PERST has been asserted for at least 300 ms */
|
|
|
+ mdelay(300);
|
|
|
+ ret = pinctrl_select_state(dev, "perst-default");
|
|
|
+ if (ret) {
|
|
|
+ dev_err(dev, "Set perst-default pinctrl failed: %d\n", ret);
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+
|
|
|
+err_release_power_pin:
|
|
|
+ pinctrl_select_state(dev, "power-default");
|
|
|
+err_deassert_reset:
|
|
|
+ reset_assert_bulk(&priv->rsts);
|
|
|
+err_deassert_clk:
|
|
|
+ clk_disable_bulk(&priv->clks);
|
|
|
+
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static int starfive_pcie_probe(struct udevice *dev)
|
|
|
+{
|
|
|
+ struct starfive_pcie *priv = dev_get_priv(dev);
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ priv->atr_table_num = 0;
|
|
|
+ priv->dev = dev;
|
|
|
+ priv->first_busno = dev_seq(dev);
|
|
|
+
|
|
|
+ ret = starfive_pcie_parse_dt(dev);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ regmap_update_bits(priv->regmap,
|
|
|
+ priv->stg_rp_nep,
|
|
|
+ STG_SYSCON_K_RP_NEP_MASK,
|
|
|
+ 1 << STG_SYSCON_K_RP_NEP_SHIFT);
|
|
|
+
|
|
|
+ regmap_update_bits(priv->regmap,
|
|
|
+ priv->stg_awfun,
|
|
|
+ STG_SYSCON_CKREF_SRC_MASK,
|
|
|
+ 2 << STG_SYSCON_CKREF_SRC_SHIFT);
|
|
|
+
|
|
|
+ regmap_update_bits(priv->regmap,
|
|
|
+ priv->stg_awfun,
|
|
|
+ STG_SYSCON_CLKREQ_MASK,
|
|
|
+ 1 << STG_SYSCON_CLKREQ_SHIFT);
|
|
|
+
|
|
|
+ ret = starfive_pcie_init_port(dev);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ dev_err(dev, "Starfive PCIe bus probed.\n");
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static const struct dm_pci_ops starfive_pcie_ops = {
|
|
|
+ .read_config = starfive_pcie_config_read,
|
|
|
+ .write_config = starfive_pcie_config_write,
|
|
|
+};
|
|
|
+
|
|
|
+static const struct udevice_id starfive_pcie_ids[] = {
|
|
|
+ { .compatible = "starfive,jh7110-pcie" },
|
|
|
+ { }
|
|
|
+};
|
|
|
+
|
|
|
+U_BOOT_DRIVER(starfive_pcie_drv) = {
|
|
|
+ .name = "starfive_pcie",
|
|
|
+ .id = UCLASS_PCI,
|
|
|
+ .of_match = starfive_pcie_ids,
|
|
|
+ .ops = &starfive_pcie_ops,
|
|
|
+ .probe = starfive_pcie_probe,
|
|
|
+ .priv_auto = sizeof(struct starfive_pcie),
|
|
|
+};
|