pcie_starfive.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Starfive PLDA PCIe host controller driver
  4. *
  5. * Copyright (c) 2023 Starfive, Inc.
  6. * Author: Mason Huo <mason.huo@starfivetech.com>
  7. *
  8. */
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <dm.h>
  12. #include <asm/global_data.h>
  13. #include <dm/device_compat.h>
  14. #include <dm/pinctrl.h>
  15. #include <generic-phy.h>
  16. #include <pci.h>
  17. #include <power-domain.h>
  18. #include <power/regulator.h>
  19. #include <regmap.h>
  20. #include <reset.h>
  21. #include <syscon.h>
  22. #include <asm/io.h>
  23. #include <asm-generic/gpio.h>
  24. #include <linux/delay.h>
  25. #include <linux/iopoll.h>
  26. DECLARE_GLOBAL_DATA_PTR;
  27. #define GEN_SETTINGS 0x80
  28. #define PCIE_PCI_IDS 0x9C
  29. #define PCIE_WINROM 0xFC
  30. #define PMSG_SUPPORT_RX 0x3F0
  31. #define PCI_MISC 0xB4
  32. #define PLDA_EP_ENABLE 0
  33. #define PLDA_RP_ENABLE 1
  34. #define IDS_REVISION_ID 0x02
  35. #define IDS_PCI_TO_PCI_BRIDGE 0x060400
  36. #define IDS_CLASS_CODE_SHIFT 8
  37. #define PREF_MEM_WIN_64_SUPPORT BIT(3)
  38. #define PMSG_LTR_SUPPORT BIT(2)
  39. #define PLDA_FUNCTION_DIS BIT(15)
  40. #define PLDA_FUNC_NUM 4
  41. #define PLDA_PHY_FUNC_SHIFT 9
  42. #define XR3PCI_ATR_AXI4_SLV0 0x800
  43. #define XR3PCI_ATR_SRC_ADDR_LOW 0x0
  44. #define XR3PCI_ATR_SRC_ADDR_HIGH 0x4
  45. #define XR3PCI_ATR_TRSL_ADDR_LOW 0x8
  46. #define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc
  47. #define XR3PCI_ATR_TRSL_PARAM 0x10
  48. #define XR3PCI_ATR_TABLE_OFFSET 0x20
  49. #define XR3PCI_ATR_MAX_TABLE_NUM 8
  50. #define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT 1
  51. #define XR3PCI_ATR_SRC_ADDR_MASK 0xfffff000
  52. #define XR3PCI_ATR_TRSL_ADDR_MASK 0xfffff000
  53. #define XR3_PCI_ECAM_SIZE 28
  54. #define XR3PCI_ATR_TRSL_DIR BIT(22)
  55. /* IDs used in the XR3PCI_ATR_TRSL_PARAM */
  56. #define XR3PCI_ATR_TRSLID_PCIE_MEMORY 0x0
  57. #define XR3PCI_ATR_TRSLID_PCIE_CONFIG 0x1
  58. #define ECAM_BUS_SHIFT 20
  59. #define ECAM_DEV_SHIFT 15
  60. #define ECAM_FUNC_SHIFT 12
  61. /* Secondary bus number offset in config space */
  62. #define PCI_SECONDARY_BUS 0x19
  63. /* system control */
  64. #define STG_SYSCON_K_RP_NEP_SHIFT 0x8
  65. #define STG_SYSCON_K_RP_NEP_MASK 0x100
  66. #define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK 0x7FFF00
  67. #define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT 0x8
  68. #define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK 0x7FFF
  69. #define STG_SYSCON_AXI4_SLVL_AWFUNC_SHIFT 0x0
  70. #define STG_SYSCON_CLKREQ_SHIFT 0x16
  71. #define STG_SYSCON_CLKREQ_MASK 0x400000
  72. #define STG_SYSCON_CKREF_SRC_SHIFT 0x12
  73. #define STG_SYSCON_CKREF_SRC_MASK 0xC0000
  74. struct starfive_pcie {
  75. struct udevice *dev;
  76. void __iomem *reg_base;
  77. void __iomem *cfg_base;
  78. struct regmap *regmap;
  79. u32 stg_arfun;
  80. u32 stg_awfun;
  81. u32 stg_rp_nep;
  82. struct clk_bulk clks;
  83. struct reset_ctl_bulk rsts;
  84. int atr_table_num;
  85. int first_busno;
  86. };
  87. static int starfive_pcie_addr_valid(pci_dev_t bdf, int first_busno)
  88. {
  89. if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0))
  90. return 0;
  91. if ((PCI_BUS(bdf) == first_busno + 1) && (PCI_DEV(bdf) > 0))
  92. return 0;
  93. return 1;
  94. }
  95. static int starfive_pcie_off_conf(pci_dev_t bdf, uint offset)
  96. {
  97. unsigned int bus = PCI_BUS(bdf);
  98. unsigned int dev = PCI_DEV(bdf);
  99. unsigned int func = PCI_FUNC(bdf);
  100. return (bus << ECAM_BUS_SHIFT) | (dev << ECAM_DEV_SHIFT) |
  101. (func << ECAM_FUNC_SHIFT) | (offset & ~0x3);
  102. }
  103. static bool plda_pcie_hide_rc_bar(pci_dev_t bdf, int offset)
  104. {
  105. if ((PCI_BUS(bdf) == 0) &&
  106. (offset == PCI_BASE_ADDRESS_0 || offset == PCI_BASE_ADDRESS_1))
  107. return true;
  108. return false;
  109. }
  110. static int starfive_pcie_config_read(const struct udevice *udev, pci_dev_t bdf,
  111. uint offset, ulong *valuep,
  112. enum pci_size_t size)
  113. {
  114. void __iomem *addr;
  115. ulong value;
  116. struct starfive_pcie *priv = dev_get_priv(udev);
  117. int where = starfive_pcie_off_conf(bdf, offset);
  118. if (!starfive_pcie_addr_valid(bdf, priv->first_busno)) {
  119. pr_debug("Out of range\n");
  120. *valuep = pci_get_ff(size);
  121. return 0;
  122. }
  123. addr = priv->cfg_base;
  124. addr += where;
  125. if (!addr)
  126. return -1;
  127. /* Make sure the LAST TLP is finished, before reading vendor ID. */
  128. if (offset == PCI_VENDOR_ID)
  129. mdelay(20);
  130. value = readl(addr);
  131. *valuep = pci_conv_32_to_size(value, offset, size);
  132. return 0;
  133. }
  134. int starfive_pcie_config_write(struct udevice *udev, pci_dev_t bdf,
  135. uint offset, ulong value,
  136. enum pci_size_t size)
  137. {
  138. void __iomem *addr;
  139. ulong old;
  140. struct starfive_pcie *priv = dev_get_priv(udev);
  141. int where = starfive_pcie_off_conf(bdf, offset);
  142. if (plda_pcie_hide_rc_bar(bdf, offset))
  143. return -1;
  144. if (!starfive_pcie_addr_valid(bdf, priv->first_busno)) {
  145. pr_debug("Out of range\n");
  146. return 0;
  147. }
  148. addr = priv->cfg_base;
  149. addr += where;
  150. if (!addr)
  151. return -1;
  152. old = readl(addr);
  153. value = pci_conv_size_to_32(old, value, offset, size);
  154. writel(value, addr);
  155. return 0;
  156. }
  157. static void starfive_pcie_set_atr_entry(struct starfive_pcie *priv, phys_addr_t src_addr,
  158. phys_addr_t trsl_addr, size_t window_size,
  159. int trsl_param)
  160. {
  161. void __iomem *base =
  162. priv->reg_base + XR3PCI_ATR_AXI4_SLV0;
  163. /* Support AXI4 Slave 0 Address Translation Tables 0-7. */
  164. if (priv->atr_table_num >= XR3PCI_ATR_MAX_TABLE_NUM)
  165. priv->atr_table_num = XR3PCI_ATR_MAX_TABLE_NUM - 1;
  166. base += XR3PCI_ATR_TABLE_OFFSET * priv->atr_table_num;
  167. priv->atr_table_num++;
  168. /* X3PCI_ATR_SRC_ADDR_LOW:
  169. * - bit 0: enable entry,
  170. * - bits 1-6: ATR window size: total size in bytes: 2^(ATR_WSIZE + 1)
  171. * - bits 7-11: reserved
  172. * - bits 12-31: start of source address
  173. */
  174. writel((lower_32_bits(src_addr) & XR3PCI_ATR_SRC_ADDR_MASK) |
  175. (fls(window_size) - 1) << XR3PCI_ATR_SRC_WIN_SIZE_SHIFT | 1,
  176. base + XR3PCI_ATR_SRC_ADDR_LOW);
  177. writel(upper_32_bits(src_addr), base + XR3PCI_ATR_SRC_ADDR_HIGH);
  178. writel((lower_32_bits(trsl_addr) & XR3PCI_ATR_TRSL_ADDR_MASK),
  179. base + XR3PCI_ATR_TRSL_ADDR_LOW);
  180. writel(upper_32_bits(trsl_addr), base + XR3PCI_ATR_TRSL_ADDR_HIGH);
  181. writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM);
  182. dev_info(priv->dev, "ATR entry: 0x%010llx %s 0x%010llx [0x%010llx] (param: 0x%06x)\n",
  183. src_addr, (trsl_param & XR3PCI_ATR_TRSL_DIR) ? "<-" : "->",
  184. trsl_addr, (u64)window_size, trsl_param);
  185. }
  186. static int starfive_pcie_atr_init(struct starfive_pcie *priv)
  187. {
  188. struct udevice *ctlr = pci_get_controller(priv->dev);
  189. struct pci_controller *hose = dev_get_uclass_priv(ctlr);
  190. int i;
  191. /* As the two host bridges in JH7110 soc have the same default
  192. * address translation table, this cause the second root port can't
  193. * access it's host bridge config space correctly.
  194. * To workaround, config the ATR of host bridge config space by SW.
  195. */
  196. starfive_pcie_set_atr_entry(priv,
  197. (phys_addr_t)priv->cfg_base,
  198. 0,
  199. 1 << XR3_PCI_ECAM_SIZE,
  200. XR3PCI_ATR_TRSLID_PCIE_CONFIG);
  201. for (i = 0; i < hose->region_count; i++) {
  202. if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY)
  203. continue;
  204. /* Only support identity mappings. */
  205. if (hose->regions[i].bus_start !=
  206. hose->regions[i].phys_start)
  207. return -EINVAL;
  208. starfive_pcie_set_atr_entry(priv,
  209. hose->regions[i].phys_start,
  210. hose->regions[i].bus_start,
  211. hose->regions[i].size,
  212. XR3PCI_ATR_TRSLID_PCIE_MEMORY);
  213. }
  214. return 0;
  215. }
  216. static int starfive_pcie_get_syscon(struct udevice *dev)
  217. {
  218. struct starfive_pcie *priv = dev_get_priv(dev);
  219. struct udevice *syscon;
  220. struct ofnode_phandle_args syscfg_phandle;
  221. u32 cells[4];
  222. int ret;
  223. /* get corresponding syscon phandle */
  224. ret = dev_read_phandle_with_args(dev, "starfive,stg-syscon", NULL, 0, 0,
  225. &syscfg_phandle);
  226. if (ret < 0) {
  227. dev_err(dev, "Can't get syscfg phandle: %d\n", ret);
  228. return ret;
  229. }
  230. ret = uclass_get_device_by_ofnode(UCLASS_SYSCON, syscfg_phandle.node,
  231. &syscon);
  232. if (ret) {
  233. dev_err(dev, "Unable to find syscon device (%d)\n", ret);
  234. return ret;
  235. }
  236. priv->regmap = syscon_get_regmap(syscon);
  237. if (!priv->regmap) {
  238. dev_err(dev, "Unable to find regmap\n");
  239. return -ENODEV;
  240. }
  241. /* get syscon register offset */
  242. ret = dev_read_u32_array(dev, "starfive,stg-syscon",
  243. cells, ARRAY_SIZE(cells));
  244. if (ret) {
  245. dev_err(dev, "Get syscon register count err %d\n", ret);
  246. return -EINVAL;
  247. }
  248. dev_dbg(dev, "Get syscon values: %x, %x, %x\n",
  249. cells[1], cells[2], cells[3]);
  250. priv->stg_arfun = cells[1];
  251. priv->stg_awfun = cells[2];
  252. priv->stg_rp_nep = cells[3];
  253. return 0;
  254. }
  255. static int starfive_pcie_parse_dt(struct udevice *dev)
  256. {
  257. struct starfive_pcie *priv = dev_get_priv(dev);
  258. int ret;
  259. priv->reg_base = (void *)dev_read_addr_name(dev, "reg");
  260. if (priv->reg_base == (void __iomem *)FDT_ADDR_T_NONE) {
  261. dev_err(dev, "Missing required reg address range\n");
  262. return -EINVAL;
  263. }
  264. priv->cfg_base = (void *)dev_read_addr_name(dev, "config");
  265. if (priv->cfg_base == (void __iomem *)FDT_ADDR_T_NONE) {
  266. dev_err(dev, "Missing required config address range");
  267. return -EINVAL;
  268. }
  269. ret = starfive_pcie_get_syscon(dev);
  270. if (ret) {
  271. dev_err(dev, "Can't get syscon: %d\n", ret);
  272. return ret;
  273. }
  274. ret = reset_get_bulk(dev, &priv->rsts);
  275. if (ret) {
  276. dev_err(dev, "Can't get reset: %d\n", ret);
  277. return ret;
  278. }
  279. ret = clk_get_bulk(dev, &priv->clks);
  280. if (ret) {
  281. dev_err(dev, "Can't get clock: %d\n", ret);
  282. return ret;
  283. }
  284. return 0;
  285. }
  286. static int starfive_pcie_init_port(struct udevice *dev)
  287. {
  288. int ret, i;
  289. unsigned int value;
  290. struct starfive_pcie *priv = dev_get_priv(dev);
  291. ret = clk_enable_bulk(&priv->clks);
  292. if (ret) {
  293. dev_err(dev, "Failed to enable clks (ret=%d)\n", ret);
  294. return ret;
  295. }
  296. ret = reset_deassert_bulk(&priv->rsts);
  297. if (ret) {
  298. dev_err(dev, "Failed to deassert resets (ret=%d)\n", ret);
  299. goto err_deassert_clk;
  300. }
  301. ret = pinctrl_select_state(dev, "power-active");
  302. if (ret) {
  303. dev_err(dev, "Set power-acvtive pinctrl failed: %d\n", ret);
  304. goto err_deassert_reset;
  305. }
  306. ret = pinctrl_select_state(dev, "perst-active");
  307. if (ret) {
  308. dev_err(dev, "Set perst-active pinctrl failed: %d\n", ret);
  309. goto err_release_power_pin;
  310. }
  311. /* Disable physical functions except #0 */
  312. for (i = 1; i < PLDA_FUNC_NUM; i++) {
  313. regmap_update_bits(priv->regmap,
  314. priv->stg_arfun,
  315. STG_SYSCON_AXI4_SLVL_ARFUNC_MASK,
  316. (i << PLDA_PHY_FUNC_SHIFT) <<
  317. STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT);
  318. regmap_update_bits(priv->regmap,
  319. priv->stg_awfun,
  320. STG_SYSCON_AXI4_SLVL_AWFUNC_MASK,
  321. (i << PLDA_PHY_FUNC_SHIFT) <<
  322. STG_SYSCON_AXI4_SLVL_AWFUNC_SHIFT);
  323. value = readl(priv->reg_base + PCI_MISC);
  324. value |= PLDA_FUNCTION_DIS;
  325. writel(value, priv->reg_base + PCI_MISC);
  326. }
  327. regmap_update_bits(priv->regmap,
  328. priv->stg_arfun,
  329. STG_SYSCON_AXI4_SLVL_ARFUNC_MASK,
  330. 0 << STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT);
  331. regmap_update_bits(priv->regmap,
  332. priv->stg_awfun,
  333. STG_SYSCON_AXI4_SLVL_AWFUNC_MASK,
  334. 0 << STG_SYSCON_AXI4_SLVL_AWFUNC_SHIFT);
  335. /* Enable root port*/
  336. value = readl(priv->reg_base + GEN_SETTINGS);
  337. value |= PLDA_RP_ENABLE;
  338. writel(value, priv->reg_base + GEN_SETTINGS);
  339. /* PCIe PCI Standard Configuration Identification Settings. */
  340. value = (IDS_PCI_TO_PCI_BRIDGE << IDS_CLASS_CODE_SHIFT) | IDS_REVISION_ID;
  341. writel(value, priv->reg_base + PCIE_PCI_IDS);
  342. /* The LTR message forwarding of PCIe Message Reception was set by core
  343. * as default, but the forward id & addr are also need to be reset.
  344. * If we do not disable LTR message forwarding here, or set a legal
  345. * forwarding address, the kernel will get stuck after this driver probe.
  346. * To workaround, disable the LTR message forwarding support on
  347. * PCIe Message Reception.
  348. */
  349. value = readl(priv->reg_base + PMSG_SUPPORT_RX);
  350. value &= ~PMSG_LTR_SUPPORT;
  351. writel(value, priv->reg_base + PMSG_SUPPORT_RX);
  352. /* Prefetchable memory window 64-bit addressing support */
  353. value = readl(priv->reg_base + PCIE_WINROM);
  354. value |= PREF_MEM_WIN_64_SUPPORT;
  355. writel(value, priv->reg_base + PCIE_WINROM);
  356. starfive_pcie_atr_init(priv);
  357. /* Ensure that PERST has been asserted for at least 300 ms */
  358. mdelay(300);
  359. ret = pinctrl_select_state(dev, "perst-default");
  360. if (ret) {
  361. dev_err(dev, "Set perst-default pinctrl failed: %d\n", ret);
  362. return ret;
  363. }
  364. return 0;
  365. err_release_power_pin:
  366. pinctrl_select_state(dev, "power-default");
  367. err_deassert_reset:
  368. reset_assert_bulk(&priv->rsts);
  369. err_deassert_clk:
  370. clk_disable_bulk(&priv->clks);
  371. return ret;
  372. }
  373. static int starfive_pcie_probe(struct udevice *dev)
  374. {
  375. struct starfive_pcie *priv = dev_get_priv(dev);
  376. int ret;
  377. priv->atr_table_num = 0;
  378. priv->dev = dev;
  379. priv->first_busno = dev_seq(dev);
  380. ret = starfive_pcie_parse_dt(dev);
  381. if (ret)
  382. return ret;
  383. regmap_update_bits(priv->regmap,
  384. priv->stg_rp_nep,
  385. STG_SYSCON_K_RP_NEP_MASK,
  386. 1 << STG_SYSCON_K_RP_NEP_SHIFT);
  387. regmap_update_bits(priv->regmap,
  388. priv->stg_awfun,
  389. STG_SYSCON_CKREF_SRC_MASK,
  390. 2 << STG_SYSCON_CKREF_SRC_SHIFT);
  391. regmap_update_bits(priv->regmap,
  392. priv->stg_awfun,
  393. STG_SYSCON_CLKREQ_MASK,
  394. 1 << STG_SYSCON_CLKREQ_SHIFT);
  395. ret = starfive_pcie_init_port(dev);
  396. if (ret)
  397. return ret;
  398. dev_err(dev, "Starfive PCIe bus probed.\n");
  399. return 0;
  400. }
  401. static const struct dm_pci_ops starfive_pcie_ops = {
  402. .read_config = starfive_pcie_config_read,
  403. .write_config = starfive_pcie_config_write,
  404. };
  405. static const struct udevice_id starfive_pcie_ids[] = {
  406. { .compatible = "starfive,jh7110-pcie" },
  407. { }
  408. };
  409. U_BOOT_DRIVER(starfive_pcie_drv) = {
  410. .name = "starfive_pcie",
  411. .id = UCLASS_PCI,
  412. .of_match = starfive_pcie_ids,
  413. .ops = &starfive_pcie_ops,
  414. .probe = starfive_pcie_probe,
  415. .priv_auto = sizeof(struct starfive_pcie),
  416. };