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@@ -13,7 +13,6 @@
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#include <init.h>
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#define CSR_U74_FEATURE_DISABLE 0x7c1
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-#define L2_LIM_MEM_END 0x81FFFFFUL
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DECLARE_GLOBAL_DATA_PTR;
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@@ -59,9 +58,6 @@ int spl_soc_init(void)
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void harts_early_init(void)
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{
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- ulong *ptr;
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- u8 *tmp;
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- ulong len, remain;
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/*
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* Feature Disable CSR
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*
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@@ -70,25 +66,4 @@ void harts_early_init(void)
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*/
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if (CONFIG_IS_ENABLED(RISCV_MMODE))
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csr_write(CSR_U74_FEATURE_DISABLE, 0);
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-
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- /* clear L2 LIM memory
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- * set __bss_end to 0x81FFFFF region to zero
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- * The L2 Cache Controller supports ECC. ECC is applied to SRAM.
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- * If it is not cleared, the ECC part is invalid, and an ECC error
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- * will be reported when reading data.
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- */
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- ptr = (ulong *)&__bss_end;
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- len = L2_LIM_MEM_END - (ulong)&__bss_end;
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- remain = len % sizeof(ulong);
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- len /= sizeof(ulong);
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-
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- while (len--)
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- *ptr++ = 0;
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-
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- /* clear the remain bytes */
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- if (remain) {
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- tmp = (u8 *)ptr;
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- while (remain--)
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- *tmp++ = 0;
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- }
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}
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