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@@ -1,8 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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- * Copyright (C) 2015
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- * Gerald Kerma <dreagle@doukki.net>
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- * Tony Dinh <mibodhi@gmail.com>
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+ * Copyright (C) 2015, 2021 Tony Dinh <mibodhi@gmail.com>
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+ * Copyright (C) 2015 Gerald Kerma <dreagle@doukki.net>
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*/
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#include <common.h>
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@@ -81,21 +80,51 @@ int board_init(void)
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return 0;
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}
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+static int fdt_get_phy_addr(const char *path)
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+{
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+ const void *fdt = gd->fdt_blob;
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+ const u32 *reg;
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+ const u32 *val;
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+ int node, phandle, addr;
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+
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+ /* Find the node by its full path */
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+ node = fdt_path_offset(fdt, path);
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+ if (node >= 0) {
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+ /* Look up phy-handle */
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+ val = fdt_getprop(fdt, node, "phy-handle", NULL);
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+ if (val) {
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+ phandle = fdt32_to_cpu(*val);
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+ if (!phandle)
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+ return -1;
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+ /* Follow it to its node */
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+ node = fdt_node_offset_by_phandle(fdt, phandle);
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+ if (node) {
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+ /* Look up reg */
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+ reg = fdt_getprop(fdt, node, "reg", NULL);
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+ if (reg) {
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+ addr = fdt32_to_cpu(*reg);
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+ return addr;
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+ }
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+ }
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+ }
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+ }
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+ return -1;
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+}
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+
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#ifdef CONFIG_RESET_PHY_R
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void reset_phy(void)
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{
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u16 reg;
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u16 phyaddr;
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- char *name = "egiga0";
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+ char *name = "ethernet-controller@72000";
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+ char *eth0_path = "/ocp@f1000000/ethernet-controller@72000/ethernet0-port@0";
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if (miiphy_set_current_dev(name))
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return;
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- /* read PHY dev address */
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- if (miiphy_read(name, 0xee, 0xee, (u16 *) &phyaddr)) {
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- printf("could not read PHY dev address\n");
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+ phyaddr = fdt_get_phy_addr(eth0_path);
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+ if (phyaddr < 0)
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return;
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- }
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/* set RGMII delay */
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miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG);
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@@ -131,5 +160,7 @@ void reset_phy(void)
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/* downshift */
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miiphy_write(name, phyaddr, 0x10, 0x3860);
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miiphy_write(name, phyaddr, 0x0, 0x9140);
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+
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+ printf("MV88E1318 PHY initialized on %s\n", name);
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}
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#endif /* CONFIG_RESET_PHY_R */
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