nsa310s.c 3.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015, 2021 Tony Dinh <mibodhi@gmail.com>
  4. * Copyright (C) 2015 Gerald Kerma <dreagle@doukki.net>
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <miiphy.h>
  9. #include <net.h>
  10. #include <asm/arch/cpu.h>
  11. #include <asm/arch/soc.h>
  12. #include <asm/arch/mpp.h>
  13. #include <asm/global_data.h>
  14. #include <asm/io.h>
  15. #include "nsa310s.h"
  16. DECLARE_GLOBAL_DATA_PTR;
  17. int board_early_init_f(void)
  18. {
  19. /*
  20. * default gpio configuration
  21. * There are maximum 64 gpios controlled through 2 sets of registers
  22. * the below configuration configures mainly initial LED status
  23. */
  24. mvebu_config_gpio(NSA310S_VAL_LOW, NSA310S_VAL_HIGH,
  25. NSA310S_OE_LOW, NSA310S_OE_HIGH);
  26. /* (all LEDs & power off active high) */
  27. /* Multi-Purpose Pins Functionality configuration */
  28. static const u32 kwmpp_config[] = {
  29. MPP0_NF_IO2,
  30. MPP1_NF_IO3,
  31. MPP2_NF_IO4,
  32. MPP3_NF_IO5,
  33. MPP4_NF_IO6,
  34. MPP5_NF_IO7,
  35. MPP6_SYSRST_OUTn,
  36. MPP7_GPO,
  37. MPP8_TW_SDA,
  38. MPP9_TW_SCK,
  39. MPP10_UART0_TXD,
  40. MPP11_UART0_RXD,
  41. MPP12_GPO,
  42. MPP13_GPIO,
  43. MPP14_GPIO,
  44. MPP15_GPIO,
  45. MPP16_GPIO,
  46. MPP17_GPIO,
  47. MPP18_NF_IO0,
  48. MPP19_NF_IO1,
  49. MPP20_GPIO,
  50. MPP21_GPIO,
  51. MPP22_GPIO,
  52. MPP23_GPIO,
  53. MPP24_GPIO,
  54. MPP25_GPIO,
  55. MPP26_GPIO,
  56. MPP27_GPIO,
  57. MPP28_GPIO,
  58. MPP29_GPIO,
  59. MPP30_GPIO,
  60. MPP31_GPIO,
  61. MPP32_GPIO,
  62. MPP33_GPIO,
  63. MPP34_GPIO,
  64. MPP35_GPIO,
  65. 0
  66. };
  67. kirkwood_mpp_conf(kwmpp_config, NULL);
  68. return 0;
  69. }
  70. int board_init(void)
  71. {
  72. /* address of boot parameters */
  73. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  74. return 0;
  75. }
  76. static int fdt_get_phy_addr(const char *path)
  77. {
  78. const void *fdt = gd->fdt_blob;
  79. const u32 *reg;
  80. const u32 *val;
  81. int node, phandle, addr;
  82. /* Find the node by its full path */
  83. node = fdt_path_offset(fdt, path);
  84. if (node >= 0) {
  85. /* Look up phy-handle */
  86. val = fdt_getprop(fdt, node, "phy-handle", NULL);
  87. if (val) {
  88. phandle = fdt32_to_cpu(*val);
  89. if (!phandle)
  90. return -1;
  91. /* Follow it to its node */
  92. node = fdt_node_offset_by_phandle(fdt, phandle);
  93. if (node) {
  94. /* Look up reg */
  95. reg = fdt_getprop(fdt, node, "reg", NULL);
  96. if (reg) {
  97. addr = fdt32_to_cpu(*reg);
  98. return addr;
  99. }
  100. }
  101. }
  102. }
  103. return -1;
  104. }
  105. #ifdef CONFIG_RESET_PHY_R
  106. void reset_phy(void)
  107. {
  108. u16 reg;
  109. u16 phyaddr;
  110. char *name = "ethernet-controller@72000";
  111. char *eth0_path = "/ocp@f1000000/ethernet-controller@72000/ethernet0-port@0";
  112. if (miiphy_set_current_dev(name))
  113. return;
  114. phyaddr = fdt_get_phy_addr(eth0_path);
  115. if (phyaddr < 0)
  116. return;
  117. /* set RGMII delay */
  118. miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG);
  119. miiphy_read(name, phyaddr, MV88E1318_MAC_CTRL_REG, &reg);
  120. reg |= (MV88E1318_RGMII_RX_CTRL | MV88E1318_RGMII_TX_CTRL);
  121. miiphy_write(name, phyaddr, MV88E1318_MAC_CTRL_REG, reg);
  122. miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
  123. /* reset PHY */
  124. if (miiphy_reset(name, phyaddr))
  125. return;
  126. /*
  127. * ZyXEL NSA310S uses the 88E1310S Alaska (interface identical to 88E1318)
  128. * and has an MCU attached to the LED[2] via tristate interrupt
  129. */
  130. /* switch to LED register page */
  131. miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_LED_PG);
  132. /* read out LED polarity register */
  133. miiphy_read(name, phyaddr, MV88E1318_LED_POL_REG, &reg);
  134. /* clear 4, set 5 - LED2 low, tri-state */
  135. reg &= ~(MV88E1318_LED2_4);
  136. reg |= (MV88E1318_LED2_5);
  137. /* write back LED polarity register */
  138. miiphy_write(name, phyaddr, MV88E1318_LED_POL_REG, reg);
  139. /* jump back to page 0, per the PHY chip documenation. */
  140. miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
  141. /* set PHY back to auto-negotiation mode */
  142. miiphy_write(name, phyaddr, 0x4, 0x1e1);
  143. miiphy_write(name, phyaddr, 0x9, 0x300);
  144. /* downshift */
  145. miiphy_write(name, phyaddr, 0x10, 0x3860);
  146. miiphy_write(name, phyaddr, 0x0, 0x9140);
  147. printf("MV88E1318 PHY initialized on %s\n", name);
  148. }
  149. #endif /* CONFIG_RESET_PHY_R */