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@@ -15,6 +15,56 @@
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#address-cells = <2>;
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#size-cells = <2>;
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+ chosen {
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+ opensbi-domains {
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+ compatible = "opensbi,domain,config";
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+
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+ rpmsg_shmem: rpmsg_shmem {
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+ compatible = "opensbi,domain,memregion";
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+ base = <0x0 0x6e400000>;
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+ order = <22>;
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+ };
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+
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+ rtcode: rtcode {
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+ compatible = "opensbi,domain,memregion";
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+ base = <0x0 0x6e800000>;
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+ order = <23>;
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+ };
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+
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+ rtheap: rtheap {
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+ compatible = "opensbi,domain,memregion";
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+ base = <0x0 0x6f000000>;
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+ order = <24>;
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+ };
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+
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+ allmem: allmem {
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+ compatible = "opensbi,domain,memregion";
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+ base = <0x0 0x0>;
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+ order = <64>;
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+ };
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+
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+ udomain: u-domain {
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+ compatible = "opensbi,domain,instance";
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+ possible-harts = <&cpu0 &cpu1 &cpu2 &cpu3>;
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+ regions = <&rpmsg_shmem 0x3f>, <&rtcode 0x0>, <&rtheap 0x0>, <&allmem 0x3f>;
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+ next-addr = <0x0 0x40200000>;
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+ boot-hart = <&cpu1>;
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+ system-reset-allowed;
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+ system-suspend-allowed;
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+ };
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+
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+ rtdomain: rt-domain {
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+ compatible = "opensbi,domain,instance";
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+ possible-harts = <&cpu4>;
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+ regions = <&rpmsg_shmem 0x3f>, <&rtcode 0x3f>, <&rtheap 0x3f>, <&allmem 0x3f>;
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+ boot-hart = <&cpu4>;
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+ next-arg1 = <0x0 0x0>;
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+ next-addr = <0x0 0x6e800000>;
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+ next-mode = <0x1>;
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+ };
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+ };
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+ };
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+
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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@@ -37,6 +87,7 @@
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next-level-cache = <&cachectrl>;
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riscv,isa = "rv64imacu_zba_zbb";
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tlb-split;
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+ opensbi-domain = <&udomain>;
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status = "disabled";
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cpu0intctrl: interrupt-controller {
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@@ -64,6 +115,7 @@
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next-level-cache = <&cachectrl>;
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riscv,isa = "rv64imafdcbsux_zba_zbb";
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tlb-split;
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+ opensbi-domain = <&udomain>;
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status = "okay";
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cpu1intctrl: interrupt-controller {
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@@ -91,6 +143,7 @@
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next-level-cache = <&cachectrl>;
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riscv,isa = "rv64imafdcbsux_zba_zbb";
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tlb-split;
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+ opensbi-domain = <&udomain>;
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status = "okay";
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cpu2intctrl: interrupt-controller {
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@@ -118,6 +171,7 @@
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next-level-cache = <&cachectrl>;
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riscv,isa = "rv64imafdcbsux_zba_zbb";
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tlb-split;
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+ opensbi-domain = <&udomain>;
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status = "okay";
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cpu3intctrl: interrupt-controller {
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@@ -145,6 +199,7 @@
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next-level-cache = <&cachectrl>;
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riscv,isa = "rv64imafdcbsux_zba_zbb";
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tlb-split;
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+ opensbi-domain = <&rtdomain>;
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status = "okay";
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cpu4intctrl: interrupt-controller {
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