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@@ -0,0 +1,75 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Copyright (C) 2021 SiFive
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+ */
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+
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+#include <common.h>
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+#include <cache.h>
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+#include <dm.h>
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+#include <asm/io.h>
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+#include <dm/device.h>
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+#include <linux/bitfield.h>
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+
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+#define SIFIVE_CCACHE_CONFIG 0x000
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+#define SIFIVE_CCACHE_CONFIG_WAYS GENMASK(15, 8)
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+
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+#define SIFIVE_CCACHE_WAY_ENABLE 0x008
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+
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+struct sifive_ccache {
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+ void __iomem *base;
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+};
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+
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+static int sifive_ccache_enable(struct udevice *dev)
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+{
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+ struct sifive_ccache *priv = dev_get_priv(dev);
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+ u32 config;
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+ u32 ways;
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+
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+ /* Enable all ways of composable cache */
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+ config = readl(priv->base + SIFIVE_CCACHE_CONFIG);
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+ ways = FIELD_GET(SIFIVE_CCACHE_CONFIG_WAYS, config);
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+
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+ writel(ways - 1, priv->base + SIFIVE_CCACHE_WAY_ENABLE);
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+
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+ return 0;
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+}
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+
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+static int sifive_ccache_get_info(struct udevice *dev, struct cache_info *info)
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+{
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+ struct sifive_ccache *priv = dev_get_priv(dev);
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+
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+ info->base = (phys_addr_t)priv->base;
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+
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+ return 0;
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+}
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+
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+static const struct cache_ops sifive_ccache_ops = {
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+ .enable = sifive_ccache_enable,
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+ .get_info = sifive_ccache_get_info,
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+};
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+
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+static int sifive_ccache_probe(struct udevice *dev)
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+{
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+ struct sifive_ccache *priv = dev_get_priv(dev);
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+
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+ priv->base = dev_read_addr_ptr(dev);
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+ if (!priv->base)
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+ return -EINVAL;
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+
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+ return 0;
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+}
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+
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+static const struct udevice_id sifive_ccache_ids[] = {
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+ { .compatible = "sifive,fu540-c000-ccache" },
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+ { .compatible = "sifive,fu740-c000-ccache" },
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+ {}
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+};
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+
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+U_BOOT_DRIVER(sifive_ccache) = {
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+ .name = "sifive_ccache",
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+ .id = UCLASS_CACHE,
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+ .of_match = sifive_ccache_ids,
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+ .probe = sifive_ccache_probe,
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+ .priv_auto = sizeof(struct sifive_ccache),
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+ .ops = &sifive_ccache_ops,
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+};
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