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@@ -147,6 +147,9 @@ void sdram_init(void)
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile fsl_lbc_t *lbc = &immap->im_lbc;
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uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
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+ const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
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+ LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
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+ LSDMR_WRC3 | LSDMR_CL3;
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puts("\n SDRAM on Local Bus: ");
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print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
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@@ -156,22 +159,27 @@ void sdram_init(void)
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*/
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/* setup mtrpt, lsrt and lbcr for LB bus */
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- lbc->lbcr = CONFIG_SYS_LBC_LBCR;
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- lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
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- lbc->lsrt = CONFIG_SYS_LBC_LSRT;
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+ lbc->lbcr = 0x00000000;
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+ /* LB refresh timer prescal, 266MHz/32 */
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+ lbc->mrtpr = 0x20000000;
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+ /* LB sdram refresh timer, about 6us */
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+ lbc->lsrt = 0x32000000;
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asm("sync");
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/*
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* Configure the SDRAM controller Machine Mode Register.
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*/
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- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
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+ /* 0x40636733; normal operation */
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+ lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
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- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
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+ /* 0x68636733; precharge all the banks */
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+ lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
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asm("sync");
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*sdram_addr = 0xff;
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udelay(100);
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- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
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+ /* 0x48636733; auto refresh */
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+ lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
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asm("sync");
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/*1 times*/
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*sdram_addr = 0xff;
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@@ -199,12 +207,13 @@ void sdram_init(void)
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udelay(100);
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/* 0x58636733; mode register write operation */
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- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
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+ lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
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asm("sync");
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*sdram_addr = 0xff;
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udelay(100);
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- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
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+ /* 0x40636733; normal operation */
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+ lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
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asm("sync");
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*sdram_addr = 0xff;
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udelay(100);
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