Browse Source

mpc83xx: Get rid of CONFIG_SYS_DDR_SDRAM_BASE

CONFIG_SYS_DDR_SDRAM_BASE is set to the same value as
CONFIG_SYS_SDRAM_BASE on all existing boards. Just use
CONFIG_SYS_SDRAM_BASE instead.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Mario Six 5 years ago
parent
commit
133ec60284
44 changed files with 35 additions and 61 deletions
  1. 1 1
      arch/powerpc/cpu/mpc83xx/spd_sdram.c
  2. 2 2
      board/freescale/mpc8308rdb/sdram.c
  3. 4 4
      board/freescale/mpc8313erdb/sdram.c
  4. 1 1
      board/freescale/mpc8315erdb/sdram.c
  5. 4 4
      board/freescale/mpc8349emds/mpc8349emds.c
  6. 4 4
      board/freescale/mpc8349itx/mpc8349itx.c
  7. 1 1
      board/freescale/mpc837xemds/mpc837xemds.c
  8. 1 1
      board/freescale/mpc837xerdb/mpc837xerdb.c
  9. 2 2
      board/gdsys/mpc8308/sdram.c
  10. 1 1
      board/ids/ids8313/ids8313.c
  11. 2 2
      board/mpc8308_p1m/sdram.c
  12. 4 4
      board/sbc8349/sbc8349.c
  13. 4 4
      board/ve8313/ve8313.c
  14. 4 0
      drivers/ddr/fsl/main.c
  15. 0 1
      include/configs/MPC8308RDB.h
  16. 0 1
      include/configs/MPC8313ERDB_NAND.h
  17. 0 1
      include/configs/MPC8313ERDB_NOR.h
  18. 0 1
      include/configs/MPC8315ERDB.h
  19. 0 1
      include/configs/MPC8323ERDB.h
  20. 0 1
      include/configs/MPC832XEMDS.h
  21. 0 1
      include/configs/MPC8349EMDS.h
  22. 0 1
      include/configs/MPC8349EMDS_SDRAM.h
  23. 0 1
      include/configs/MPC8349ITX.h
  24. 0 1
      include/configs/MPC837XEMDS.h
  25. 0 1
      include/configs/MPC837XERDB.h
  26. 0 1
      include/configs/TQM834x.h
  27. 0 1
      include/configs/caddy2.h
  28. 0 1
      include/configs/hrcon.h
  29. 0 1
      include/configs/ids8313.h
  30. 0 1
      include/configs/kmcoge5ne.h
  31. 0 1
      include/configs/kmeter1.h
  32. 0 1
      include/configs/kmopti2.h
  33. 0 1
      include/configs/kmsupx5.h
  34. 0 1
      include/configs/kmtegr1.h
  35. 0 1
      include/configs/kmtepr2.h
  36. 0 1
      include/configs/kmvect1.h
  37. 0 1
      include/configs/mpc8308_p1m.h
  38. 0 1
      include/configs/sbc8349.h
  39. 0 1
      include/configs/strider.h
  40. 0 1
      include/configs/suvd3.h
  41. 0 1
      include/configs/tuge1.h
  42. 0 1
      include/configs/tuxx1.h
  43. 0 1
      include/configs/ve8313.h
  44. 0 1
      include/configs/vme8349.h

+ 1 - 1
arch/powerpc/cpu/mpc83xx/spd_sdram.c

@@ -281,7 +281,7 @@ long int spd_sdram()
 	/*
 	 * Set up LAWBAR for all of DDR.
 	 */
-	ecm->bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+	ecm->bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
 	ecm->ar  = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
 	debug("DDR:bar=0x%08x\n", ecm->bar);
 	debug("DDR:ar=0x%08x\n", ecm->ar);

+ 2 - 2
board/freescale/mpc8308rdb/sdram.c

@@ -33,7 +33,7 @@ static long fixed_sdram(void)
 	u32 msize_log2 = __ilog2(msize);
 
 	out_be32(&im->sysconf.ddrlaw[0].bar,
-			CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000);
+			CONFIG_SYS_SDRAM_BASE  & 0xfffff000);
 	out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
 	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
 
@@ -61,7 +61,7 @@ static long fixed_sdram(void)
 	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
 	sync();
 
-	return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
+	return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
 }
 
 int dram_init(void)

+ 4 - 4
board/freescale/mpc8313erdb/sdram.c

@@ -47,7 +47,7 @@ static long fixed_sdram(void)
 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 	u32 msize_log2 = __ilog2(msize);
 
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
 	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
 	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
 
@@ -57,12 +57,12 @@ static long fixed_sdram(void)
 	 */
 	__udelay(50000);
 
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
 #warning Chip select bounds is only configurable in 16MB increments
 #endif
 	im->ddr.csbnds[0].csbnds =
-		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
-		(((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
+		((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+		(((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
 			CSBNDS_EA);
 	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
 

+ 1 - 1
board/freescale/mpc8315erdb/sdram.c

@@ -44,7 +44,7 @@ static long fixed_sdram(void)
 	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
 	u32 msize_log2 = __ilog2(msize);
 
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000;
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE  & 0xfffff000;
 	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
 	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
 

+ 4 - 4
board/freescale/mpc8349emds/mpc8349emds.c

@@ -91,7 +91,7 @@ int fixed_sdram(void)
 	u32 ddr_size = msize << 20;	/* DDR size in bytes */
 	u32 ddr_size_log2 = __ilog2(ddr_size);
 
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
 	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 
 #if (CONFIG_SYS_DDR_SIZE != 256)
@@ -112,12 +112,12 @@ int fixed_sdram(void)
 	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
 #else
 
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
 #warning Chip select bounds is only configurable in 16MB increments
 #endif
 	im->ddr.csbnds[2].csbnds =
-		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
-		(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+		((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+		(((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
 				CSBNDS_EA_SHIFT) & CSBNDS_EA);
 	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
 

+ 4 - 4
board/freescale/mpc8349itx/mpc8349itx.c

@@ -37,14 +37,14 @@ int fixed_sdram(void)
 
 	im->sysconf.ddrlaw[0].ar =
 	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
 
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
 #warning Chip select bounds is only configurable in 16MB increments
 #endif
 	im->ddr.csbnds[0].csbnds =
-		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
-		(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+		((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+		(((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
 				CSBNDS_EA_SHIFT) & CSBNDS_EA);
 	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
 

+ 1 - 1
board/freescale/mpc837xemds/mpc837xemds.c

@@ -252,7 +252,7 @@ int fixed_sdram(void)
 	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
 	u32 msize_log2 = __ilog2(msize);
 
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
 	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
 
 #if (CONFIG_SYS_DDR_SIZE != 512)

+ 1 - 1
board/freescale/mpc837xerdb/mpc837xerdb.c

@@ -95,7 +95,7 @@ int fixed_sdram(void)
 	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
 	u32 msize_log2 = __ilog2(msize);
 
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
 	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
 
 	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;

+ 2 - 2
board/gdsys/mpc8308/sdram.c

@@ -34,7 +34,7 @@ static long fixed_sdram(void)
 	u32 msize_log2 = __ilog2(msize);
 
 	out_be32(&im->sysconf.ddrlaw[0].bar,
-		 CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000);
+		 CONFIG_SYS_SDRAM_BASE  & 0xfffff000);
 	out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
 	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
 
@@ -62,7 +62,7 @@ static long fixed_sdram(void)
 	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
 	sync();
 
-	return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
+	return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
 }
 
 int dram_init(void)

+ 1 - 1
board/ids/ids8313/ids8313.c

@@ -57,7 +57,7 @@ int fixed_sdram(unsigned long config)
 	u32 msize_log2 = __ilog2(msize);
 
 	out_be32(&im->sysconf.ddrlaw[0].bar,
-		 (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
+		 (CONFIG_SYS_SDRAM_BASE & 0xfffff000));
 	out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
 	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
 	sync();

+ 2 - 2
board/mpc8308_p1m/sdram.c

@@ -29,7 +29,7 @@ static long fixed_sdram(void)
 	u32 msize_log2 = __ilog2(msize);
 
 	out_be32(&im->sysconf.ddrlaw[0].bar,
-			CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000);
+			CONFIG_SYS_SDRAM_BASE  & 0xfffff000);
 	out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
 	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
 
@@ -57,7 +57,7 @@ static long fixed_sdram(void)
 	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
 	sync();
 
-	return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
+	return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
 }
 
 int dram_init(void)

+ 4 - 4
board/sbc8349/sbc8349.c

@@ -79,19 +79,19 @@ int fixed_sdram(void)
 	u32 ddr_size = msize << 20;	/* DDR size in bytes */
 	u32 ddr_size_log2 = __ilog2(msize);
 
-	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
 	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 
 #if (CONFIG_SYS_DDR_SIZE != 256)
 #warning Currently any ddr size other than 256 is not supported
 #endif
 
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
 #warning Chip select bounds is only configurable in 16MB increments
 #endif
 	im->ddr.csbnds[2].csbnds =
-		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
-		(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+		((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+		(((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
 				CSBNDS_EA_SHIFT) & CSBNDS_EA);
 	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
 

+ 4 - 4
board/ve8313/ve8313.c

@@ -38,7 +38,7 @@ static long fixed_sdram(void)
 	u32 msize_log2 = __ilog2(msize);
 
 	out_be32(&im->sysconf.ddrlaw[0].bar,
-		(CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
+		(CONFIG_SYS_SDRAM_BASE & 0xfffff000));
 	out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1)));
 	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
 
@@ -48,12 +48,12 @@ static long fixed_sdram(void)
 	 */
 	__udelay(50000);
 
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
 #warning Chip select bounds is only configurable in 16MB increments
 #endif
 	out_be32(&im->ddr.csbnds[0].csbnds,
-		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
-		(((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
+		((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+		(((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
 			CSBNDS_EA));
 	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
 

+ 4 - 0
drivers/ddr/fsl/main.c

@@ -23,8 +23,12 @@
  * 0x80_8000_0000 ~ 0xff_ffff_ffff
  */
 #ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
+#ifdef CONFIG_MPC83xx
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE
+#else
 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
 #endif
+#endif
 
 #ifdef CONFIG_PPC
 #include <asm/fsl_law.h>

+ 0 - 1
include/configs/MPC8308RDB.h

@@ -37,7 +37,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
 				| DDRCDR_PZ_LOZ \

+ 0 - 1
include/configs/MPC8313ERDB_NAND.h

@@ -87,7 +87,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 
 /*
  * Manually set up DDR parameters, as this board does not

+ 0 - 1
include/configs/MPC8313ERDB_NOR.h

@@ -59,7 +59,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 
 /*
  * Manually set up DDR parameters, as this board does not

+ 0 - 1
include/configs/MPC8315ERDB.h

@@ -35,7 +35,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
 				| DDRCDR_PZ_LOZ \

+ 0 - 1
include/configs/MPC8323ERDB.h

@@ -24,7 +24,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE	0x00000000	/* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 
 #undef CONFIG_SPD_EEPROM
 #if defined(CONFIG_SPD_EEPROM)

+ 0 - 1
include/configs/MPC832XEMDS.h

@@ -21,7 +21,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE	0x00000000	/* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDRCDR	0x73000002	/* DDR II voltage is 1.8V */
 
 #undef CONFIG_SPD_EEPROM

+ 0 - 1
include/configs/MPC8349EMDS.h

@@ -53,7 +53,6 @@
 #undef CONFIG_DDR_32BIT
 
 #define CONFIG_SYS_SDRAM_BASE	0x00000000	/* DDR is system memory*/
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN \
 					| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 #undef  CONFIG_DDR_2T_TIMING

+ 0 - 1
include/configs/MPC8349EMDS_SDRAM.h

@@ -53,7 +53,6 @@
 #undef CONFIG_DDR_32BIT
 
 #define CONFIG_SYS_SDRAM_BASE	0x00000000	/* DDR is system memory*/
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN \
 					| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 #undef  CONFIG_DDR_2T_TIMING

+ 0 - 1
include/configs/MPC8349ITX.h

@@ -143,7 +143,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_83XX_DDR_USES_CS0
 #define CONFIG_SYS_MEMTEST_START	0x1000	/* memtest region */
 #define CONFIG_SYS_MEMTEST_END		0x2000

+ 0 - 1
include/configs/MPC837XEMDS.h

@@ -36,7 +36,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_83XX_DDR_USES_CS0
 #define CONFIG_SYS_DDRCDR_VALUE		(DDRCDR_DHC_EN \

+ 0 - 1
include/configs/MPC837XERDB.h

@@ -59,7 +59,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	0x03000000
 #define CONFIG_SYS_83XX_DDR_USES_CS0
 

+ 0 - 1
include/configs/TQM834x.h

@@ -25,7 +25,6 @@
  */
 				/* DDR is system memory*/
 #define CONFIG_SYS_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 #define DDR_CASLAT_25		/* CASLAT set to 2.5 */
 #undef CONFIG_DDR_ECC		/* only for ECC DDR module */
 #undef CONFIG_SPD_EEPROM	/* do not use SPD EEPROM for DDR setup */

+ 0 - 1
include/configs/caddy2.h

@@ -52,7 +52,6 @@
 #undef CONFIG_DDR_32BIT
 
 #define CONFIG_SYS_SDRAM_BASE		0x00000000	/* DDR is sys memory*/
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN \
 					| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 #define CONFIG_DDR_2T_TIMING

+ 0 - 1
include/configs/hrcon.h

@@ -25,7 +25,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
 				| DDRCDR_PZ_LOZ \

+ 0 - 1
include/configs/ids8313.h

@@ -52,7 +52,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 
 /*
  * Manually set up DDR parameters,

+ 0 - 1
include/configs/kmcoge5ne.h

@@ -46,7 +46,6 @@
 #define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2	(CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
 					DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

+ 0 - 1
include/configs/kmeter1.h

@@ -31,7 +31,6 @@
 #define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2	(CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
 					DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

+ 0 - 1
include/configs/kmopti2.h

@@ -51,7 +51,6 @@
 #define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2	(CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
 					DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

+ 0 - 1
include/configs/kmsupx5.h

@@ -51,7 +51,6 @@
 #define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2	(CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
 					DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

+ 0 - 1
include/configs/kmtegr1.h

@@ -58,7 +58,6 @@
 #define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2	(CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
 					DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

+ 0 - 1
include/configs/kmtepr2.h

@@ -51,7 +51,6 @@
 #define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2	(CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
 					DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

+ 0 - 1
include/configs/kmvect1.h

@@ -50,7 +50,6 @@
 #define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2	(CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
 					DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

+ 0 - 1
include/configs/mpc8308_p1m.h

@@ -40,7 +40,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
 				| DDRCDR_PZ_LOZ \

+ 0 - 1
include/configs/sbc8349.h

@@ -47,7 +47,6 @@
 #undef CONFIG_DDR_32BIT
 
 #define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
 				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 #define CONFIG_DDR_2T_TIMING

+ 0 - 1
include/configs/strider.h

@@ -25,7 +25,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
 				| DDRCDR_PZ_LOZ \

+ 0 - 1
include/configs/suvd3.h

@@ -48,7 +48,6 @@
 #define CONFIG_SYS_SDRAM_BASE	0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2	(CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
 					DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

+ 0 - 1
include/configs/tuge1.h

@@ -51,7 +51,6 @@
 #define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2	(CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
 					DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

+ 0 - 1
include/configs/tuxx1.h

@@ -51,7 +51,6 @@
 #define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE2	(CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
 
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
 					DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 

+ 0 - 1
include/configs/ve8313.h

@@ -35,7 +35,6 @@
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory*/
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 
 /*
  * Manually set up DDR parameters, as this board does not

+ 0 - 1
include/configs/vme8349.h

@@ -52,7 +52,6 @@
 #undef CONFIG_DDR_32BIT
 
 #define CONFIG_SYS_SDRAM_BASE		0x00000000	/* DDR is sys memory*/
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN \
 					| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 #define CONFIG_DDR_2T_TIMING