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@@ -788,6 +788,96 @@ u32 mxc_get_clock(enum mxc_clock clk)
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return 0;
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}
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+#ifdef CONFIG_DWC_ETH_QOS
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+int set_clk_eqos(enum enet_freq type)
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+{
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+ u32 target;
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+ u32 enet1_ref;
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+
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+ switch (type) {
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+ case ENET_125MHZ:
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+ enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
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+ break;
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+ case ENET_50MHZ:
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+ enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
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+ break;
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+ case ENET_25MHZ:
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+ enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
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+ break;
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+ default:
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+ return -EINVAL;
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+ }
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+
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+ /* disable the clock first */
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+ clock_enable(CCGR_QOS_ETHENET, 0);
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+ clock_enable(CCGR_SDMA2, 0);
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+
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+ /* set enet axi clock 266Mhz */
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+ target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
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+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
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+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
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+ clock_set_target_val(ENET_AXI_CLK_ROOT, target);
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+
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+ target = CLK_ROOT_ON | enet1_ref |
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+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
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+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
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+ clock_set_target_val(ENET_QOS_CLK_ROOT, target);
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+
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+ target = CLK_ROOT_ON |
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+ ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
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+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
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+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
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+ clock_set_target_val(ENET_QOS_TIMER_CLK_ROOT, target);
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+
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+ /* enable clock */
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+ clock_enable(CCGR_QOS_ETHENET, 1);
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+ clock_enable(CCGR_SDMA2, 1);
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+
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+ return 0;
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+}
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+
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+int imx_eqos_txclk_set_rate(u32 rate)
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+{
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+ u32 val;
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+ u32 eqos_post_div;
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+
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+ /* disable the clock first */
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+ clock_enable(CCGR_QOS_ETHENET, 0);
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+ clock_enable(CCGR_SDMA2, 0);
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+
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+ switch (rate) {
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+ case 125000000:
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+ eqos_post_div = 1;
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+ break;
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+ case 25000000:
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+ eqos_post_div = 125000000 / 25000000;
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+ break;
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+ case 2500000:
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+ eqos_post_div = 125000000 / 2500000;
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+ break;
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+ default:
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+ return -EINVAL;
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+ }
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+
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+ clock_get_target_val(ENET_QOS_CLK_ROOT, &val);
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+ val &= ~(CLK_ROOT_PRE_DIV_MASK | CLK_ROOT_POST_DIV_MASK);
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+ val |= CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
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+ CLK_ROOT_POST_DIV(eqos_post_div - 1);
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+ clock_set_target_val(ENET_QOS_CLK_ROOT, val);
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+
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+ /* enable clock */
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+ clock_enable(CCGR_QOS_ETHENET, 1);
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+ clock_enable(CCGR_SDMA2, 1);
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+
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+ return 0;
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+}
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+
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+u32 imx_get_eqos_csr_clk(void)
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+{
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+ return get_root_clk(ENET_AXI_CLK_ROOT);
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+}
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+#endif
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+
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#ifdef CONFIG_FEC_MXC
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int set_clk_enet(enum enet_freq type)
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{
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