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@@ -317,6 +317,72 @@ void init_wdog_clk(void)
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clock_enable(CCGR_WDOG3, 1);
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}
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+void init_clk_usdhc(u32 index)
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+{
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+ /*
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+ * set usdhc clock root
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+ * sys pll1 400M
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+ */
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+ switch (index) {
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+ case 0:
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+ clock_enable(CCGR_USDHC1, 0);
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+ clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
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+ CLK_ROOT_SOURCE_SEL(1));
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+ clock_enable(CCGR_USDHC1, 1);
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+ return;
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+ case 1:
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+ clock_enable(CCGR_USDHC2, 0);
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+ clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
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+ CLK_ROOT_SOURCE_SEL(1));
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+ clock_enable(CCGR_USDHC2, 1);
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+ return;
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+ case 2:
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+ clock_enable(CCGR_USDHC3, 0);
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+ clock_set_target_val(USDHC3_CLK_ROOT, CLK_ROOT_ON |
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+ CLK_ROOT_SOURCE_SEL(1));
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+ clock_enable(CCGR_USDHC3, 1);
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+ return;
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+ default:
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+ printf("Invalid usdhc index\n");
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+ return;
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+ }
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+}
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+
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+void init_clk_ecspi(u32 index)
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+{
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+ switch (index) {
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+ case 0:
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+ clock_enable(CCGR_ECSPI1, 0);
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+ clock_set_target_val(ECSPI1_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
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+ clock_enable(CCGR_ECSPI1, 1);
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+ return;
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+ case 1:
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+ clock_enable(CCGR_ECSPI2, 0);
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+ clock_set_target_val(ECSPI2_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
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+ clock_enable(CCGR_ECSPI2, 1);
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+ case 2:
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+ clock_enable(CCGR_ECSPI3, 0);
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+ clock_set_target_val(ECSPI3_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(0));
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+ clock_enable(CCGR_ECSPI3, 1);
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+ return;
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+ default:
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+ printf("Invalid ecspi index\n");
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+ return;
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+ }
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+}
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+
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+void init_nand_clk(void)
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+{
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+ /*
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+ * set rawnand root
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+ * sys pll1 400M
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+ */
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+ clock_enable(CCGR_RAWNAND, 0);
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+ clock_set_target_val(NAND_CLK_ROOT, CLK_ROOT_ON |
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+ CLK_ROOT_SOURCE_SEL(3) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4)); /* 100M */
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+ clock_enable(CCGR_RAWNAND, 1);
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+}
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+
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int clock_init(void)
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{
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u32 val_cfg0;
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