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@@ -4,8 +4,8 @@
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* Author: yanhong <yanhong.wang@starfivetech.com>
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*
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*/
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-#include <asm/arch/jh7110-regs.h>
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#include <common.h>
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+#include <asm/arch/clk.h>
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#include <clk-uclass.h>
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#include <clk.h>
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#include <dt-bindings/clock/starfive-jh7110-clkgen.h>
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@@ -17,7 +17,6 @@
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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-#define getbits_le32(addr,mask) ((in_le32(addr)&(mask)) >> __ffs(mask))
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#define STARFIVE_CLK_ENABLE_SHIFT 31 /*[31]*/
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#define STARFIVE_CLK_INVERT_SHIFT 30 /*[30]*/
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#define STARFIVE_CLK_MUX_SHIFT 24 /*[29:24]*/
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@@ -303,48 +302,26 @@ static struct clk *starfive_clk_gate_divider(void __iomem *reg,
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offset, 0, 1, width);
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}
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-static int jh7110_get_pll0_freq(void)
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-{
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- u32 dacpd, dsmpd;
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- u32 prediv, fbdiv, postdiv1;
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- u32 refclk = 24;
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- u32 pll0_freq = 0;
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-
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- dacpd = getbits_le32(SYS_SYSCON_BASE+SYS_SYSCON_24, PLL0_DACPD_MASK);
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- dsmpd = getbits_le32(SYS_SYSCON_BASE+SYS_SYSCON_24, PLL0_DSMPD_MASK);
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- fbdiv = getbits_le32(SYS_SYSCON_BASE+SYS_SYSCON_28, PLL0_FBDIV_MASK);
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- prediv = getbits_le32(SYS_SYSCON_BASE+SYS_SYSCON_36, PLL0_PREDIV_MASK);
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- postdiv1 = 1 << getbits_le32(SYS_SYSCON_BASE+SYS_SYSCON_32, PLL0_POSTDIV1_MASK);
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-
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- debug("dacpd:%d, dsmpd:%d, prediv:%d, fbdiv:%d, postdiv1:%d\n",
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- dacpd, dsmpd, prediv, fbdiv, postdiv1);
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- if (dacpd == 1 && dsmpd == 1)
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- pll0_freq = (refclk * fbdiv) / (prediv * postdiv1);
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- else if ((dacpd == 0 && dsmpd == 0))
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- pll0_freq = 1000;
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- else {
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- debug("Unkwnon pll mode.\n");
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- return -EINVAL;
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- }
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-
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- printf("FREQ: %d MHz\n",pll0_freq);
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- return pll0_freq;
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-}
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-
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static int jh7110_clk_init(struct udevice *dev)
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{
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struct jh7110_clk_priv *priv = dev_get_priv(dev);
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- u32 pll0_freq = jh7110_get_pll0_freq();
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+ struct starfive_pll_freq conf;
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+ u64 pll;
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+ pll = starfive_jh7110_pll_get_rate(PLL0, &conf);
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clk_dm(JH7110_PLL0_OUT,
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starfive_clk_fix_factor(priv->sys,
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- "pll0_out", "osc", pll0_freq, 24));
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+ "pll0_out", "osc", conf.fbdiv, conf.prediv * conf.postdiv1));
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+
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+ pll = starfive_jh7110_pll_get_rate(PLL1, &conf);
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clk_dm(JH7110_PLL1_OUT,
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starfive_clk_fix_factor(priv->sys,
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- "pll1_out", "osc", 1066, 24));
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+ "pll1_out", "osc", conf.fbdiv, conf.prediv * conf.postdiv1));
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+
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+ pll = starfive_jh7110_pll_get_rate(PLL2, &conf);
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clk_dm(JH7110_PLL2_OUT,
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starfive_clk_fix_factor(priv->sys,
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- "pll2_out", "osc", 12288, 240));
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+ "pll2_out", "osc", conf.fbdiv, conf.prediv * conf.postdiv1));
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/*root*/
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clk_dm(JH7110_CPU_ROOT,
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starfive_clk_mux(priv->sys, "cpu_root",
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