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@@ -11,138 +11,13 @@
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#include <asm/io.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/jh7110-regs.h>
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+#include <asm/arch/clk.h>
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#include <image.h>
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-#include <linux/bitops.h>
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#include <log.h>
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-#include <linux/delay.h>
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#include <spl.h>
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#define MODE_SELECT_REG 0x1702002c
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-struct starfive_pll0_freq {
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- u32 freq;
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- u32 prediv;
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- u32 fbdiv;
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- u32 postdiv1;
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- u32 dacpd; /* Both daxpd and dsmpd set 1 while integer multiple mode */
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- u32 dsmpd; /* Both daxpd and dsmpd set 0 while fraction multiple mode */
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-};
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-
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-enum starfive_cpu_freq {
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- CPU_FREQ_375 = 0,
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- CPU_FREQ_500,
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- CPU_FREQ_625,
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- CPU_FREQ_750,
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- CPU_FREQ_875,
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- CPU_FREQ_1000,
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- CPU_FREQ_1250,
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- CPU_FREQ_1375,
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- CPU_FREQ_1500,
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- CPU_FREQ_1625,
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- CPU_FREQ_1750,
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- CPU_FREQ_1800,
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- CPU_FREQ_MAX = CPU_FREQ_1800
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-};
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-
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-struct starfive_pll0_freq jh7110_pll0_freq[] = {
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- {
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- .freq = CPU_FREQ_375,
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- .prediv = 8,
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- .fbdiv = 125,
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- .postdiv1 = 1,
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- .dacpd = 1,
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- .dsmpd = 1
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- },
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- {
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- .freq = CPU_FREQ_500,
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- .prediv = 6,
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- .fbdiv = 125,
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- .postdiv1 = 1,
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- .dacpd = 1,
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- .dsmpd = 1
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- },
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- {
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- .freq = CPU_FREQ_625,
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- .prediv = 24,
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- .fbdiv = 625,
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- .postdiv1 = 1,
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- .dacpd = 1,
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- .dsmpd = 1
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- },
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- {
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- .freq = CPU_FREQ_750,
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- .prediv = 4,
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- .fbdiv = 125,
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- .postdiv1 = 1,
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- .dacpd = 1,
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- .dsmpd = 1
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- },
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- {
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- .freq = CPU_FREQ_875,
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- .prediv = 24,
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- .fbdiv = 875,
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- .postdiv1 = 1,
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- .dacpd = 1,
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- .dsmpd = 1
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- },
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- {
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- .freq = CPU_FREQ_1000,
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- .prediv = 3,
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- .fbdiv = 125,
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- .postdiv1 = 1,
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- .dacpd = 1,
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- .dsmpd = 1
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- },
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- {
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- .freq = CPU_FREQ_1250,
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- .prediv = 12,
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- .fbdiv = 625,
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- .postdiv1 = 1,
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- .dacpd = 1,
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- .dsmpd = 1
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- },
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- {
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- .freq = CPU_FREQ_1375,
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- .prediv = 24,
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- .fbdiv = 1375,
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- .postdiv1 = 1,
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- .dacpd = 1,
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- .dsmpd = 1
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- },
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- {
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- .freq = CPU_FREQ_1500,
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- .prediv = 2,
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- .fbdiv = 125,
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- .postdiv1 = 1,
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- .dacpd = 1,
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- .dsmpd = 1
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- },
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- {
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- .freq = CPU_FREQ_1625,
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- .prediv = 24,
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- .fbdiv = 1625,
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- .postdiv1 = 1,
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- .dacpd = 1,
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- .dsmpd = 1
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- },
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- {
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- .freq = CPU_FREQ_1750,
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- .prediv = 12,
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- .fbdiv = 875,
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- .postdiv1 = 1,
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- .dacpd = 1,
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- .dsmpd = 1
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- },
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- {
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- .freq = CPU_FREQ_1800,
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- .prediv = 3,
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- .fbdiv = 225,
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- .postdiv1 = 1,
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- .dacpd = 1,
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- .dsmpd = 1
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- },
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-};
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-
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int spl_board_init_f(void)
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{
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int ret;
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@@ -182,42 +57,15 @@ struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
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return (struct image_header *)(STARFIVE_SPL_BOOT_LOAD_ADDR);
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}
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-static int spl_cpu_set_rate(enum starfive_cpu_freq rate)
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-{
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- struct starfive_pll0_freq *cpu_freq;
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- int i;
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-
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- if (rate < 0 || rate > CPU_FREQ_MAX) {
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- debug("invalid input value=%d\n", rate);
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- return -EINVAL;
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- }
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-
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- for (i = 0; i<CPU_FREQ_MAX; i++) {
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- if (jh7110_pll0_freq[i].freq == rate) {
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- cpu_freq = &jh7110_pll0_freq[i];
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- break;
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- }
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- }
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-
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- clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24, PLL0_DACPD_MASK,
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- (cpu_freq->dacpd << PLL0_DACPD_SHIFT) & PLL0_DACPD_MASK);
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- clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24, PLL0_DSMPD_MASK,
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- (cpu_freq->dsmpd << PLL0_DSMPD_SHIFT) & PLL0_DSMPD_MASK);
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- clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_36, PLL0_PREDIV_MASK,
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- (cpu_freq->prediv << PLL0_PREDIV_SHIFT) & PLL0_PREDIV_MASK);
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- clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_28, PLL0_FBDIV_MASK,
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- (cpu_freq->fbdiv << PLL0_FBDIV_SHIFT) & PLL0_FBDIV_MASK);
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- clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_32, PLL0_POSTDIV1_MASK,
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- ((cpu_freq->postdiv1 >> 1) << PLL0_POSTDIV1_SHIFT) & PLL0_POSTDIV1_MASK);
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- return 0;
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-}
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-
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void board_init_f(ulong dummy)
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{
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int ret;
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/* Adjust cpu frequency, the default is 1.25GHz */
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- spl_cpu_set_rate(CPU_FREQ_1250);
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+ starfive_jh7110_pll_set_rate(PLL0, 1250000000);
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+
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+ /*change pll2 to 1188MHz*/
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+ starfive_jh7110_pll_set_rate(PLL2, 1188000000);
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/*DDR control depend clk init*/
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clrsetbits_le32(SYS_CRG_BASE, CLK_CPU_ROOT_SW_MASK,
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@@ -227,6 +75,11 @@ void board_init_f(ulong dummy)
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CLK_BUS_ROOT_SW_MASK,
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BIT(CLK_BUS_ROOT_SW_SHIFT) & CLK_BUS_ROOT_SW_MASK);
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+ /*Set clk_perh_root clk default mux sel to pll2*/
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+ clrsetbits_le32(SYS_CRG_BASE + CLK_PERH_ROOT_OFFSET,
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+ CLK_PERH_ROOT_MASK,
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+ BIT(CLK_PERH_ROOT_SHIFT) & CLK_PERH_ROOT_MASK);
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+
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clrsetbits_le32(SYS_CRG_BASE + CLK_NOC_BUS_STG_AXI_OFFSET,
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CLK_NOC_BUS_STG_AXI_EN_MASK,
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BIT(CLK_NOC_BUS_STG_AXI_EN_SHIFT)
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@@ -236,18 +89,11 @@ void board_init_f(ulong dummy)
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CLK_AON_APB_FUNC_SW_MASK,
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BIT(CLK_AON_APB_FUNC_SW_SHIFT) & CLK_AON_APB_FUNC_SW_MASK);
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- clrsetbits_le32(SYS_CRG_BASE + CLK_QSPI_REF_OFFSET,
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- CLK_QSPI_REF_SW_MASK,
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- (0 << CLK_QSPI_REF_SW_SHIFT) & CLK_QSPI_REF_SW_MASK);
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+
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/*set GPIO to 1.8v*/
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setbits_le32(SYS_SYSCON_BASE + 0xC, 0xf);
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- /*set sdio0 sdcard clk default div to 4*/
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- clrsetbits_le32(SYS_CRG_BASE + CLK_SDIO0_SDCARD_OFFSET,
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- CLK_SDIO0_SDCARD_MASK,
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- (4 << CLK_SDIO0_SDCARD_SHIFT) & CLK_SDIO0_SDCARD_MASK);
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-
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/* reset emmc */
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SYS_IOMUX_DOEN(22, LOW);
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SYS_IOMUX_DOUT(22, 19);
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