vdec.c 78 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (c) 2022, Chips&Media
  4. * All rights reserved.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. *
  9. * 1. Redistributions of source code must retain the above copyright notice, this
  10. * list of conditions and the following disclaimer.
  11. * 2. Redistributions in binary form must reproduce the above copyright notice,
  12. * this list of conditions and the following disclaimer in the documentation
  13. * and/or other materials provided with the distribution.
  14. *
  15. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  16. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  17. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
  19. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  21. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  22. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  23. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  24. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25. *
  26. * Copyright (C) 2022 StarFive Technology Co., Ltd.
  27. */
  28. #include <linux/kernel.h>
  29. #include <linux/mm.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/ioport.h>
  32. #include <linux/module.h>
  33. #include <linux/mutex.h>
  34. #include <linux/platform_device.h>
  35. #include <linux/dma-mapping.h>
  36. #include <linux/of.h>
  37. #include <linux/pm_runtime.h>
  38. #include <linux/wait.h>
  39. #include <linux/list.h>
  40. #include <linux/clk.h>
  41. #include <linux/delay.h>
  42. #include <linux/uaccess.h>
  43. #include <linux/cdev.h>
  44. #include <linux/slab.h>
  45. #include <linux/of_address.h>
  46. #include <linux/sched.h>
  47. #include <linux/sched/signal.h>
  48. #include <linux/version.h>
  49. #include <linux/kfifo.h>
  50. #include <linux/kthread.h>
  51. #include <linux/reset.h>
  52. #include <asm/io.h>
  53. #include "../../../vpuapi/vpuconfig.h"
  54. #include "vpu.h"
  55. extern void sifive_ccache_flush_range(phys_addr_t start, size_t len);
  56. extern void sifive_ccache_flush_entire(void);
  57. //#define ENABLE_DEBUG_MSG
  58. #ifdef ENABLE_DEBUG_MSG
  59. #define DPRINTK(args...) printk(KERN_INFO args);
  60. #else
  61. #define DPRINTK(args...)
  62. #endif
  63. /* definitions to be changed as customer configuration */
  64. /* if you want to have clock gating scheme frame by frame */
  65. /* #define VPU_SUPPORT_CLOCK_CONTROL */
  66. /* if the driver want to use interrupt service from kernel ISR */
  67. #define VPU_SUPPORT_ISR
  68. #ifdef VPU_SUPPORT_ISR
  69. /* if the driver want to disable and enable IRQ whenever interrupt asserted. */
  70. //#define VPU_IRQ_CONTROL
  71. #endif
  72. //#define CONFIG_USE_PLL_DYNAMIC_FREQ
  73. #define VPU_SUPPORT_CLOCK_CONTROL
  74. /* if clktree is work,try this...*/
  75. #define STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  76. /* if the platform driver knows the name of this driver */
  77. /* VPU_PLATFORM_DEVICE_NAME */
  78. #define VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  79. /* if this driver knows the dedicated video memory address */
  80. //#define VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  81. #define VPU_PLATFORM_DEVICE_NAME "vdec"
  82. #define VPU_CLK_NAME "vcodec"
  83. #define VPU_DEV_NAME "vdec"
  84. /* if the platform driver knows this driver */
  85. /* the definition of VPU_REG_BASE_ADDR and VPU_REG_SIZE are not meaningful */
  86. #define VPU_REG_BASE_ADDR 0x118F0000
  87. #define VPU_REG_SIZE (0x4000*MAX_NUM_VPU_CORE)
  88. #ifdef VPU_SUPPORT_ISR
  89. #define VPU_IRQ_NUM (23)
  90. #endif
  91. /* this definition is only for chipsnmedia FPGA board env */
  92. /* so for SOC env of customers can be ignored */
  93. #ifndef VM_RESERVED /*for kernel up to 3.7.0 version*/
  94. #define VM_RESERVED (VM_DONTEXPAND | VM_DONTDUMP)
  95. #endif
  96. struct device *vpu_dev;
  97. typedef struct vpu_drv_context_t {
  98. struct fasync_struct *async_queue;
  99. #ifdef SUPPORT_MULTI_INST_INTR
  100. unsigned long interrupt_reason[MAX_NUM_INSTANCE];
  101. #else
  102. unsigned long interrupt_reason;
  103. #endif
  104. u32 open_count; /*!<< device reference count. Not instance count */
  105. } vpu_drv_context_t;
  106. /* To track the allocated memory buffer */
  107. typedef struct vpudrv_buffer_pool_t {
  108. struct list_head list;
  109. struct vpudrv_buffer_t vb;
  110. struct file *filp;
  111. } vpudrv_buffer_pool_t;
  112. /* To track the instance index and buffer in instance pool */
  113. typedef struct vpudrv_instanace_list_t {
  114. struct list_head list;
  115. unsigned long inst_idx;
  116. unsigned long core_idx;
  117. struct file *filp;
  118. } vpudrv_instanace_list_t;
  119. typedef struct vpudrv_instance_pool_t {
  120. unsigned char codecInstPool[MAX_NUM_INSTANCE][MAX_INST_HANDLE_SIZE];
  121. } vpudrv_instance_pool_t;
  122. #ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  123. typedef struct vpu_clkgen_t {
  124. void __iomem *en_ctrl;
  125. uint32_t rst_mask;
  126. } vpu_clkgen_t;
  127. #endif
  128. struct clk_bulk_data vpu_clks[] = {
  129. { .id = "apb_clk" },
  130. { .id = "axi_clk" },
  131. { .id = "bpu_clk" },
  132. { .id = "vce_clk" },
  133. { .id = "noc_bus" },
  134. };
  135. typedef struct vpu_clk_t {
  136. #ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  137. void __iomem *clkgen;
  138. void __iomem *rst_ctrl;
  139. void __iomem *rst_status;
  140. void __iomem *noc_bus;
  141. uint32_t en_shift;
  142. uint32_t en_mask;
  143. vpu_clkgen_t apb_clk;
  144. vpu_clkgen_t axi_clk;
  145. vpu_clkgen_t bpu_clk;
  146. vpu_clkgen_t vce_clk;
  147. vpu_clkgen_t aximem_128b;
  148. #else
  149. struct clk_bulk_data *clks;
  150. struct reset_control *resets;
  151. int nr_clks;
  152. #endif
  153. struct device *dev;
  154. bool noc_ctrl;
  155. } vpu_clk_t;
  156. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  157. #include "vmm.h"
  158. static video_mm_t s_vmem;
  159. static vpudrv_buffer_t s_video_memory = {0};
  160. #endif /*VPU_SUPPORT_RESERVED_VIDEO_MEMORY*/
  161. static int vpu_hw_reset(void);
  162. static void vpu_clk_disable(vpu_clk_t *clk);
  163. static int vpu_clk_enable(vpu_clk_t *clk);
  164. static vpu_clk_t *vpu_clk_get(struct platform_device *pdev);
  165. static void vpu_clk_put(vpu_clk_t *clk);
  166. static int vpu_pmu_enable(struct device *dev);
  167. static void vpu_pmu_disable(struct device *dev);
  168. /* end customer definition */
  169. static vpudrv_buffer_t s_instance_pool = {0};
  170. static vpudrv_buffer_t s_common_memory = {0};
  171. static vpu_drv_context_t s_vpu_drv_context;
  172. static dev_t s_vpu_devt;
  173. static int s_vpu_major;
  174. static struct cdev s_vpu_cdev;
  175. static struct class *s_vpu_class;
  176. static vpu_clk_t *s_vpu_clk;
  177. static int s_vpu_open_ref_count;
  178. #ifdef VPU_SUPPORT_ISR
  179. static int s_vpu_irq = VPU_IRQ_NUM;
  180. #endif
  181. static vpudrv_buffer_t s_vpu_register = {0};
  182. #ifdef SUPPORT_MULTI_INST_INTR
  183. static int s_interrupt_flag[MAX_NUM_INSTANCE];
  184. static wait_queue_head_t s_interrupt_wait_q[MAX_NUM_INSTANCE];
  185. typedef struct kfifo kfifo_t;
  186. static kfifo_t s_interrupt_pending_q[MAX_NUM_INSTANCE];
  187. static spinlock_t s_kfifo_lock = __SPIN_LOCK_UNLOCKED(s_kfifo_lock);
  188. #else
  189. static int s_interrupt_flag;
  190. static wait_queue_head_t s_interrupt_wait_q;
  191. #endif
  192. static spinlock_t s_vpu_lock = __SPIN_LOCK_UNLOCKED(s_vpu_lock);
  193. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
  194. static DECLARE_MUTEX(s_vpu_sem);
  195. #else
  196. static DEFINE_SEMAPHORE(s_vpu_sem);
  197. #endif
  198. static struct list_head s_vbp_head = LIST_HEAD_INIT(s_vbp_head);
  199. static struct list_head s_inst_list_head = LIST_HEAD_INIT(s_inst_list_head);
  200. static vpu_bit_firmware_info_t s_bit_firmware_info[MAX_NUM_VPU_CORE];
  201. //#ifdef CONFIG_PM
  202. /* implement to power management functions */
  203. #define BIT_BASE 0x0000
  204. #define BIT_CODE_RUN (BIT_BASE + 0x000)
  205. #define BIT_CODE_DOWN (BIT_BASE + 0x004)
  206. #define BIT_INT_CLEAR (BIT_BASE + 0x00C)
  207. #define BIT_INT_STS (BIT_BASE + 0x010)
  208. #define BIT_CODE_RESET (BIT_BASE + 0x014)
  209. #define BIT_INT_REASON (BIT_BASE + 0x174)
  210. #define BIT_BUSY_FLAG (BIT_BASE + 0x160)
  211. #define BIT_RUN_COMMAND (BIT_BASE + 0x164)
  212. #define BIT_RUN_INDEX (BIT_BASE + 0x168)
  213. #define BIT_RUN_COD_STD (BIT_BASE + 0x16C)
  214. /* WAVE5 registers */
  215. #define W5_REG_BASE 0x0000
  216. #define W5_VPU_BUSY_STATUS (W5_REG_BASE + 0x0070)
  217. #define W5_VPU_INT_REASON_CLEAR (W5_REG_BASE + 0x0034)
  218. #define W5_VPU_VINT_CLEAR (W5_REG_BASE + 0x003C)
  219. #define W5_VPU_VPU_INT_STS (W5_REG_BASE + 0x0044)
  220. #define W5_VPU_INT_REASON (W5_REG_BASE + 0x004c)
  221. #define W5_RET_FAIL_REASON (W5_REG_BASE + 0x010C)
  222. #ifdef SUPPORT_MULTI_INST_INTR
  223. #define W5_RET_BS_EMPTY_INST (W5_REG_BASE + 0x01E4)
  224. #define W5_RET_QUEUE_CMD_DONE_INST (W5_REG_BASE + 0x01E8)
  225. #define W5_RET_SEQ_DONE_INSTANCE_INFO (W5_REG_BASE + 0x01FC)
  226. typedef enum {
  227. INT_WAVE5_INIT_VPU = 0,
  228. INT_WAVE5_WAKEUP_VPU = 1,
  229. INT_WAVE5_SLEEP_VPU = 2,
  230. INT_WAVE5_CREATE_INSTANCE = 3,
  231. INT_WAVE5_FLUSH_INSTANCE = 4,
  232. INT_WAVE5_DESTORY_INSTANCE = 5,
  233. INT_WAVE5_INIT_SEQ = 6,
  234. INT_WAVE5_SET_FRAMEBUF = 7,
  235. INT_WAVE5_DEC_PIC = 8,
  236. INT_WAVE5_ENC_PIC = 8,
  237. INT_WAVE5_ENC_SET_PARAM = 9,
  238. #ifdef SUPPORT_SOURCE_RELEASE_INTERRUPT
  239. INT_WAVE5_ENC_SRC_RELEASE = 10,
  240. #endif
  241. INT_WAVE5_ENC_LOW_LATENCY = 13,
  242. INT_WAVE5_DEC_QUERY = 14,
  243. INT_WAVE5_BSBUF_EMPTY = 15,
  244. INT_WAVE5_BSBUF_FULL = 15,
  245. } Wave5InterruptBit;
  246. #endif
  247. /* WAVE5 INIT, WAKEUP */
  248. #define W5_PO_CONF (W5_REG_BASE + 0x0000)
  249. #define W5_VPU_VINT_ENABLE (W5_REG_BASE + 0x0048)
  250. #define W5_VPU_RESET_REQ (W5_REG_BASE + 0x0050)
  251. #define W5_VPU_RESET_STATUS (W5_REG_BASE + 0x0054)
  252. #define W5_VPU_REMAP_CTRL (W5_REG_BASE + 0x0060)
  253. #define W5_VPU_REMAP_VADDR (W5_REG_BASE + 0x0064)
  254. #define W5_VPU_REMAP_PADDR (W5_REG_BASE + 0x0068)
  255. #define W5_VPU_REMAP_CORE_START (W5_REG_BASE + 0x006C)
  256. #define W5_REMAP_CODE_INDEX 0
  257. /* WAVE5 registers */
  258. #define W5_ADDR_CODE_BASE (W5_REG_BASE + 0x0110)
  259. #define W5_CODE_SIZE (W5_REG_BASE + 0x0114)
  260. #define W5_CODE_PARAM (W5_REG_BASE + 0x0118)
  261. #define W5_INIT_VPU_TIME_OUT_CNT (W5_REG_BASE + 0x0130)
  262. #define W5_HW_OPTION (W5_REG_BASE + 0x012C)
  263. #define W5_RET_SUCCESS (W5_REG_BASE + 0x0108)
  264. #define W5_COMMAND (W5_REG_BASE + 0x0100)
  265. #define W5_VPU_HOST_INT_REQ (W5_REG_BASE + 0x0038)
  266. /* Product register */
  267. #define VPU_PRODUCT_CODE_REGISTER (BIT_BASE + 0x1044)
  268. #if defined(VPU_SUPPORT_PLATFORM_DRIVER_REGISTER) && defined(CONFIG_PM)
  269. static u32 s_vpu_reg_store[MAX_NUM_VPU_CORE][64];
  270. #endif
  271. //#endif //CONFIG_PM
  272. #define ReadVpuRegister(addr) *(volatile unsigned int *)(s_vpu_register.virt_addr + s_bit_firmware_info[core].reg_base_offset + addr)
  273. #define WriteVpuRegister(addr, val) *(volatile unsigned int *)(s_vpu_register.virt_addr + s_bit_firmware_info[core].reg_base_offset + addr) = (unsigned int)val
  274. #define WriteVpu(addr, val) *(volatile unsigned int *)(addr) = (unsigned int)val;
  275. #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_USE_PLL_DYNAMIC_FREQ)
  276. #include <linux/fs.h>
  277. #include <linux/file.h>
  278. struct freq_ctrl {
  279. struct device *dev;
  280. struct file *governor;
  281. struct file *maxfreq;
  282. struct file *parameters_off;
  283. const char *scaling_governor;
  284. const char *scaling_maxfreq;
  285. const char *scaling_parameters_off;
  286. const char *fixed_freq;
  287. char re_cpu_gov[16];
  288. char re_max_freq[16];
  289. struct mutex mutex_lock;
  290. int count;
  291. };
  292. static struct freq_ctrl *vpu_freq_ctrl;
  293. static int vpu_freq_open(struct freq_ctrl *vpu_freq_ctrl)
  294. {
  295. vpu_freq_ctrl->governor = filp_open(
  296. vpu_freq_ctrl->scaling_governor, O_RDWR, 0);
  297. if (IS_ERR(vpu_freq_ctrl->governor))
  298. goto out;
  299. vpu_freq_ctrl->maxfreq = filp_open(
  300. vpu_freq_ctrl->scaling_maxfreq, O_RDWR, 0);
  301. if (IS_ERR(vpu_freq_ctrl->maxfreq))
  302. goto out;
  303. vpu_freq_ctrl->parameters_off = filp_open(
  304. vpu_freq_ctrl->scaling_parameters_off, O_RDWR, 0);
  305. if (IS_ERR(vpu_freq_ctrl->parameters_off))
  306. goto out;
  307. return 0;
  308. out:
  309. dev_err(vpu_freq_ctrl->dev, "failed open scaling_governor.\n");
  310. return -ENXIO;
  311. }
  312. static int vpu_freq_close(void)
  313. {
  314. if (!vpu_freq_ctrl)
  315. return -ENODEV;
  316. mutex_destroy(&vpu_freq_ctrl->mutex_lock);
  317. if (vpu_freq_ctrl->governor && vpu_freq_ctrl->maxfreq
  318. && vpu_freq_ctrl->parameters_off) {
  319. fput(vpu_freq_ctrl->governor);
  320. fput(vpu_freq_ctrl->maxfreq);
  321. fput(vpu_freq_ctrl->parameters_off);
  322. vpu_freq_ctrl->governor = NULL;
  323. vpu_freq_ctrl->maxfreq = NULL;
  324. vpu_freq_ctrl->parameters_off = NULL;
  325. }
  326. return 0;
  327. }
  328. static int vpu_freq_save_env(void)
  329. {
  330. const char *fixed_freq = vpu_freq_ctrl->fixed_freq;
  331. const char *governor_mode = "performance";
  332. size_t rv;
  333. if (!vpu_freq_ctrl)
  334. return -ENODEV;
  335. mutex_lock(&vpu_freq_ctrl->mutex_lock);
  336. if (vpu_freq_ctrl->count == 0) {
  337. /*save env*/
  338. kernel_read(vpu_freq_ctrl->governor, vpu_freq_ctrl->re_cpu_gov,
  339. sizeof(vpu_freq_ctrl->re_cpu_gov), NULL);
  340. kernel_read(vpu_freq_ctrl->maxfreq, vpu_freq_ctrl->re_max_freq,
  341. sizeof(vpu_freq_ctrl->re_max_freq), NULL);
  342. /*setenv*/
  343. rv = kernel_write(vpu_freq_ctrl->maxfreq, fixed_freq,
  344. strlen(fixed_freq), NULL);
  345. rv = kernel_write(vpu_freq_ctrl->governor, governor_mode,
  346. strlen(governor_mode), NULL);
  347. rv = kernel_write(vpu_freq_ctrl->parameters_off, "1", 1, NULL);
  348. }
  349. vpu_freq_ctrl->count++;
  350. mutex_unlock(&vpu_freq_ctrl->mutex_lock);
  351. return 0;
  352. }
  353. static int vpu_freq_put_env(void)
  354. {
  355. size_t rv;
  356. if (!vpu_freq_ctrl)
  357. return -ENODEV;
  358. mutex_lock(&vpu_freq_ctrl->mutex_lock);
  359. vpu_freq_ctrl->count--;
  360. if (vpu_freq_ctrl->count == 0) {
  361. rv = kernel_write(vpu_freq_ctrl->governor, vpu_freq_ctrl->re_cpu_gov,
  362. strlen(vpu_freq_ctrl->re_cpu_gov), NULL);
  363. rv = kernel_write(vpu_freq_ctrl->maxfreq, vpu_freq_ctrl->re_max_freq,
  364. strlen(vpu_freq_ctrl->re_max_freq), NULL);
  365. rv = kernel_write(vpu_freq_ctrl->parameters_off, "0", 1, NULL);
  366. }
  367. mutex_unlock(&vpu_freq_ctrl->mutex_lock);
  368. return 0;
  369. }
  370. static int vpu_freq_init(struct device *dev)
  371. {
  372. int ret;
  373. const char *of_str;
  374. vpu_freq_ctrl = devm_kzalloc(dev, sizeof(*vpu_freq_ctrl), GFP_KERNEL);
  375. if (!vpu_freq_ctrl)
  376. return -ENOMEM;
  377. vpu_freq_ctrl->scaling_governor = "/sys/devices/system/cpu/cpufreq/policy0/scaling_governor";
  378. vpu_freq_ctrl->scaling_maxfreq = "/sys/devices/system/cpu/cpufreq/policy0/scaling_max_freq";
  379. vpu_freq_ctrl->scaling_parameters_off = "/sys/module/cpufreq/parameters/off";
  380. vpu_freq_ctrl->dev = dev;
  381. ret = vpu_freq_open(vpu_freq_ctrl);
  382. if (ret) {
  383. devm_kfree(dev, vpu_freq_ctrl);
  384. vpu_freq_ctrl = NULL;
  385. return ret;
  386. }
  387. if (!device_property_read_string(dev, "vdec,runtime-cpufreq", &of_str))
  388. vpu_freq_ctrl->fixed_freq = of_str;
  389. else
  390. vpu_freq_ctrl->fixed_freq = "1250000";
  391. vpu_freq_ctrl->count = 0;
  392. mutex_init(&vpu_freq_ctrl->mutex_lock);
  393. dev_dbg(dev, "fixed_freq:%s\n", vpu_freq_ctrl->fixed_freq);
  394. return 0;
  395. }
  396. #endif
  397. static void starfive_flush_dcache(phys_addr_t start, size_t len)
  398. {
  399. #ifdef ARCH_HAS_SYNC_DMA_FOR_DEVICE
  400. dma_sync_single_for_device(vpu_dev, start, len, DMA_FROM_DEVICE);
  401. #else
  402. if (len >= 0x80000)
  403. sifive_ccache_flush_entire();
  404. else
  405. sifive_ccache_flush_range(start, len);
  406. #endif
  407. }
  408. static int vpu_alloc_dma_buffer(vpudrv_buffer_t *vb)
  409. {
  410. if (!vb)
  411. return -1;
  412. DPRINTK("[VPUDRV] vpu_alloc_dma_buffer \n");
  413. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  414. vb->phys_addr = (unsigned long)vmem_alloc(&s_vmem, vb->size, 0);
  415. if ((unsigned long)vb->phys_addr == (unsigned long)-1) {
  416. printk(KERN_ERR "[VPUDRV] Physical memory allocation error size=%d\n", vb->size);
  417. return -1;
  418. }
  419. vb->base = (unsigned long)(s_video_memory.base + (vb->phys_addr - s_video_memory.phys_addr));
  420. #else
  421. vb->base = (unsigned long)dma_alloc_coherent(vpu_dev, PAGE_ALIGN(vb->size), (dma_addr_t *) (&vb->phys_addr), GFP_DMA | GFP_KERNEL);
  422. if ((void *)(vb->base) == NULL) {
  423. printk(KERN_ERR "[VPUDRV] Physical memory allocation error size=%d\n", vb->size);
  424. return -1;
  425. }
  426. starfive_flush_dcache(vb->phys_addr,PAGE_ALIGN(vb->size));
  427. #endif
  428. return 0;
  429. }
  430. static void vpu_free_dma_buffer(vpudrv_buffer_t *vb)
  431. {
  432. if (!vb)
  433. return;
  434. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  435. if (vb->base)
  436. vmem_free(&s_vmem, vb->phys_addr, 0);
  437. #else
  438. if (vb->base)
  439. dma_free_coherent(vpu_dev, PAGE_ALIGN(vb->size), (void *)vb->base, vb->phys_addr);
  440. #endif
  441. }
  442. static int vpu_free_instances(struct file *filp)
  443. {
  444. vpudrv_instanace_list_t *vil, *n;
  445. vpudrv_instance_pool_t *vip;
  446. void *vip_base;
  447. int instance_pool_size_per_core;
  448. #if !defined(PTHREAD_MUTEX_ROBUST_NP)
  449. void *vdi_mutexes_base;
  450. const int PTHREAD_MUTEX_T_DESTROY_VALUE = 0xdead10cc;
  451. #endif
  452. DPRINTK("[VPUDRV] vpu_free_instances\n");
  453. instance_pool_size_per_core = (s_instance_pool.size/MAX_NUM_VPU_CORE); /* s_instance_pool.size assigned to the size of all core once call VDI_IOCTL_GET_INSTANCE_POOL by user. */
  454. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  455. {
  456. if (vil->filp == filp) {
  457. vip_base = (void *)(s_instance_pool.base + (instance_pool_size_per_core*vil->core_idx));
  458. DPRINTK("[VPUDRV] vpu_free_instances detect instance crash instIdx=%d, coreIdx=%d, vip_base=%p, instance_pool_size_per_core=%d\n", (int)vil->inst_idx, (int)vil->core_idx, vip_base, (int)instance_pool_size_per_core);
  459. vip = (vpudrv_instance_pool_t *)vip_base;
  460. if (vip) {
  461. memset(&vip->codecInstPool[vil->inst_idx], 0x00, 4); /* only first 4 byte is key point(inUse of CodecInst in vpuapi) to free the corresponding instance. */
  462. #if !defined(PTHREAD_MUTEX_ROBUST_NP)
  463. #define PTHREAD_MUTEX_T_HANDLE_SIZE 4
  464. vdi_mutexes_base = (vip_base + (instance_pool_size_per_core - PTHREAD_MUTEX_T_HANDLE_SIZE*4));
  465. DPRINTK("[VPUDRV] vpu_free_instances : force to destroy vdi_mutexes_base=%p in userspace \n", vdi_mutexes_base);
  466. if (vdi_mutexes_base) {
  467. int i;
  468. for (i = 0; i < 4; i++) {
  469. memcpy(vdi_mutexes_base, &PTHREAD_MUTEX_T_DESTROY_VALUE, PTHREAD_MUTEX_T_HANDLE_SIZE);
  470. vdi_mutexes_base += PTHREAD_MUTEX_T_HANDLE_SIZE;
  471. }
  472. }
  473. #endif
  474. }
  475. s_vpu_open_ref_count--;
  476. list_del(&vil->list);
  477. kfree(vil);
  478. }
  479. }
  480. return 1;
  481. }
  482. static int vpu_free_buffers(struct file *filp)
  483. {
  484. vpudrv_buffer_pool_t *pool, *n;
  485. vpudrv_buffer_t vb;
  486. DPRINTK("[VPUDRV] vpu_free_buffers\n");
  487. list_for_each_entry_safe(pool, n, &s_vbp_head, list)
  488. {
  489. if (pool->filp == filp) {
  490. vb = pool->vb;
  491. if (vb.base) {
  492. vpu_free_dma_buffer(&vb);
  493. list_del(&pool->list);
  494. kfree(pool);
  495. }
  496. }
  497. }
  498. return 0;
  499. }
  500. #ifdef SUPPORT_MULTI_INST_INTR
  501. static inline u32 get_inst_idx(u32 reg_val)
  502. {
  503. u32 inst_idx;
  504. int i;
  505. for (i=0; i < MAX_NUM_INSTANCE; i++)
  506. {
  507. if(((reg_val >> i)&0x01) == 1)
  508. break;
  509. }
  510. inst_idx = i;
  511. return inst_idx;
  512. }
  513. static s32 get_vpu_inst_idx(vpu_drv_context_t *dev, u32 *reason, u32 empty_inst, u32 done_inst, u32 seq_inst)
  514. {
  515. s32 inst_idx;
  516. u32 reg_val;
  517. u32 int_reason;
  518. int_reason = *reason;
  519. DPRINTK("[VPUDRV][+]%s, int_reason=0x%x, empty_inst=0x%x, done_inst=0x%x\n", __func__, int_reason, empty_inst, done_inst);
  520. //printk(KERN_ERR "[VPUDRV][+]%s, int_reason=0x%x, empty_inst=0x%x, done_inst=0x%x\n", __func__, int_reason, empty_inst, done_inst);
  521. if (int_reason & (1 << INT_WAVE5_BSBUF_EMPTY))
  522. {
  523. reg_val = (empty_inst & 0xffff);
  524. inst_idx = get_inst_idx(reg_val);
  525. *reason = (1 << INT_WAVE5_BSBUF_EMPTY);
  526. DPRINTK("[VPUDRV] %s, W5_RET_BS_EMPTY_INST reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  527. goto GET_VPU_INST_IDX_HANDLED;
  528. }
  529. if (int_reason & (1 << INT_WAVE5_INIT_SEQ))
  530. {
  531. reg_val = (seq_inst & 0xffff);
  532. inst_idx = get_inst_idx(reg_val);
  533. *reason = (1 << INT_WAVE5_INIT_SEQ);
  534. DPRINTK("[VPUDRV] %s, RET_SEQ_DONE_INSTANCE_INFO INIT_SEQ reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  535. goto GET_VPU_INST_IDX_HANDLED;
  536. }
  537. if (int_reason & (1 << INT_WAVE5_DEC_PIC))
  538. {
  539. reg_val = (done_inst & 0xffff);
  540. inst_idx = get_inst_idx(reg_val);
  541. *reason = (1 << INT_WAVE5_DEC_PIC);
  542. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST DEC_PIC reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  543. if (int_reason & (1 << INT_WAVE5_ENC_LOW_LATENCY))
  544. {
  545. u32 ll_inst_idx;
  546. reg_val = (done_inst >> 16);
  547. ll_inst_idx = get_inst_idx(reg_val);
  548. if (ll_inst_idx == inst_idx)
  549. *reason = ((1 << INT_WAVE5_DEC_PIC) | (1 << INT_WAVE5_ENC_LOW_LATENCY));
  550. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST DEC_PIC and ENC_LOW_LATENCY reg_val=0x%x, inst_idx=%d, ll_inst_idx=%d\n", __func__, reg_val, inst_idx, ll_inst_idx);
  551. }
  552. goto GET_VPU_INST_IDX_HANDLED;
  553. }
  554. if (int_reason & (1 << INT_WAVE5_ENC_SET_PARAM))
  555. {
  556. reg_val = (seq_inst & 0xffff);
  557. inst_idx = get_inst_idx(reg_val);
  558. *reason = (1 << INT_WAVE5_ENC_SET_PARAM);
  559. DPRINTK("[VPUDRV] %s, RET_SEQ_DONE_INSTANCE_INFO ENC_SET_PARAM reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  560. goto GET_VPU_INST_IDX_HANDLED;
  561. }
  562. #ifdef SUPPORT_SOURCE_RELEASE_INTERRUPT
  563. if (int_reason & (1 << INT_WAVE5_ENC_SRC_RELEASE))
  564. {
  565. reg_val = (done_inst & 0xffff);
  566. inst_idx = get_inst_idx(reg_val);
  567. *reason = (1 << INT_WAVE5_ENC_SRC_RELEASE);
  568. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST ENC_SET_PARAM reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  569. goto GET_VPU_INST_IDX_HANDLED;
  570. }
  571. #endif
  572. if (int_reason & (1 << INT_WAVE5_ENC_LOW_LATENCY))
  573. {
  574. reg_val = (done_inst >> 16);
  575. inst_idx = get_inst_idx(reg_val);
  576. *reason = (1 << INT_WAVE5_ENC_LOW_LATENCY);
  577. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST ENC_LOW_LATENCY reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  578. goto GET_VPU_INST_IDX_HANDLED;
  579. }
  580. inst_idx = -1;
  581. *reason = 0;
  582. DPRINTK("[VPUDRV] %s, UNKNOWN INTERRUPT REASON: %08x\n", __func__, int_reason);
  583. GET_VPU_INST_IDX_HANDLED:
  584. DPRINTK("[VPUDRV][-]%s, inst_idx=%d. *reason=0x%x\n", __func__, inst_idx, *reason);
  585. return inst_idx;
  586. }
  587. #endif
  588. static irqreturn_t vpu_irq_handler(int irq, void *dev_id)
  589. {
  590. vpu_drv_context_t *dev = (vpu_drv_context_t *)dev_id;
  591. /* this can be removed. it also work in VPU_WaitInterrupt of API function */
  592. int core;
  593. int product_code;
  594. #ifdef SUPPORT_MULTI_INST_INTR
  595. u32 intr_reason;
  596. s32 intr_inst_index;
  597. #endif
  598. DPRINTK("[VPUDRV][+]%s\n", __func__);
  599. #ifdef VPU_IRQ_CONTROL
  600. disable_irq_nosync(s_vpu_irq);
  601. #endif
  602. #ifdef SUPPORT_MULTI_INST_INTR
  603. intr_inst_index = 0;
  604. intr_reason = 0;
  605. #endif
  606. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  607. if (s_bit_firmware_info[core].size == 0) {/* it means that we didn't get an information the current core from API layer. No core activated.*/
  608. printk(KERN_ERR "[VPUDRV] : s_bit_firmware_info[core].size is zero\n");
  609. continue;
  610. }
  611. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  612. if (PRODUCT_CODE_W_SERIES(product_code)) {
  613. if (ReadVpuRegister(W5_VPU_VPU_INT_STS)) {
  614. #ifdef SUPPORT_MULTI_INST_INTR
  615. u32 empty_inst;
  616. u32 done_inst;
  617. u32 seq_inst;
  618. u32 i, reason, reason_clr;
  619. reason = ReadVpuRegister(W5_VPU_INT_REASON);
  620. empty_inst = ReadVpuRegister(W5_RET_BS_EMPTY_INST);
  621. done_inst = ReadVpuRegister(W5_RET_QUEUE_CMD_DONE_INST);
  622. seq_inst = ReadVpuRegister(W5_RET_SEQ_DONE_INSTANCE_INFO);
  623. reason_clr = reason;
  624. DPRINTK("[VPUDRV] vpu_irq_handler reason=0x%x, empty_inst=0x%x, done_inst=0x%x, seq_inst=0x%x \n", reason, empty_inst, done_inst, seq_inst);
  625. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  626. if (0 == empty_inst && 0 == done_inst && 0 == seq_inst) break;
  627. intr_reason = reason;
  628. intr_inst_index = get_vpu_inst_idx(dev, &intr_reason, empty_inst, done_inst, seq_inst);
  629. DPRINTK("[VPUDRV] > instance_index: %d, intr_reason: %08x empty_inst: %08x done_inst: %08x seq_inst: %08x\n", intr_inst_index, intr_reason, empty_inst, done_inst, seq_inst);
  630. if (intr_inst_index >= 0 && intr_inst_index < MAX_NUM_INSTANCE) {
  631. if (intr_reason == (1 << INT_WAVE5_BSBUF_EMPTY)) {
  632. empty_inst = empty_inst & ~(1 << intr_inst_index);
  633. WriteVpuRegister(W5_RET_BS_EMPTY_INST, empty_inst);
  634. if (0 == empty_inst) {
  635. reason &= ~(1<<INT_WAVE5_BSBUF_EMPTY);
  636. }
  637. DPRINTK("[VPUDRV] %s, W5_RET_BS_EMPTY_INST Clear empty_inst=0x%x, intr_inst_index=%d\n", __func__, empty_inst, intr_inst_index);
  638. }
  639. if (intr_reason == (1 << INT_WAVE5_DEC_PIC))
  640. {
  641. done_inst = done_inst & ~(1 << intr_inst_index);
  642. WriteVpuRegister(W5_RET_QUEUE_CMD_DONE_INST, done_inst);
  643. if (0 == done_inst) {
  644. reason &= ~(1<<INT_WAVE5_DEC_PIC);
  645. }
  646. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  647. }
  648. if ((intr_reason == (1 << INT_WAVE5_INIT_SEQ)) || (intr_reason == (1 << INT_WAVE5_ENC_SET_PARAM)))
  649. {
  650. seq_inst = seq_inst & ~(1 << intr_inst_index);
  651. WriteVpuRegister(W5_RET_SEQ_DONE_INSTANCE_INFO, seq_inst);
  652. if (0 == seq_inst) {
  653. reason &= ~(1<<INT_WAVE5_INIT_SEQ | 1<<INT_WAVE5_ENC_SET_PARAM);
  654. }
  655. DPRINTK("[VPUDRV] %s, W5_RET_SEQ_DONE_INSTANCE_INFO Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  656. }
  657. if ((intr_reason == (1 << INT_WAVE5_ENC_LOW_LATENCY)))
  658. {
  659. done_inst = (done_inst >> 16);
  660. done_inst = done_inst & ~(1 << intr_inst_index);
  661. done_inst = (done_inst << 16);
  662. WriteVpuRegister(W5_RET_QUEUE_CMD_DONE_INST, done_inst);
  663. if (0 == done_inst) {
  664. reason &= ~(1 << INT_WAVE5_ENC_LOW_LATENCY);
  665. }
  666. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST INT_WAVE5_ENC_LOW_LATENCY Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  667. }
  668. if (!kfifo_is_full(&s_interrupt_pending_q[intr_inst_index])) {
  669. if (intr_reason == ((1 << INT_WAVE5_ENC_PIC) | (1 << INT_WAVE5_ENC_LOW_LATENCY))) {
  670. u32 ll_intr_reason = (1 << INT_WAVE5_ENC_PIC);
  671. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &ll_intr_reason, sizeof(u32), &s_kfifo_lock);
  672. }
  673. else
  674. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason, sizeof(u32), &s_kfifo_lock);
  675. }
  676. else {
  677. printk(KERN_ERR "[VPUDRV] : kfifo_is_full kfifo_count=%d \n", kfifo_len(&s_interrupt_pending_q[intr_inst_index]));
  678. }
  679. }
  680. else {
  681. printk(KERN_ERR "[VPUDRV] : intr_inst_index is wrong intr_inst_index=%d \n", intr_inst_index);
  682. }
  683. }
  684. if (0 != reason)
  685. printk(KERN_ERR "INTERRUPT REASON REMAINED: %08x\n", reason);
  686. WriteVpuRegister(W5_VPU_INT_REASON_CLEAR, reason_clr);
  687. #else
  688. dev->interrupt_reason = ReadVpuRegister(W5_VPU_INT_REASON);
  689. WriteVpuRegister(W5_VPU_INT_REASON_CLEAR, dev->interrupt_reason);
  690. #endif
  691. WriteVpuRegister(W5_VPU_VINT_CLEAR, 0x1);
  692. }
  693. }
  694. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  695. if (ReadVpuRegister(BIT_INT_STS)) {
  696. #ifdef SUPPORT_MULTI_INST_INTR
  697. intr_reason = ReadVpuRegister(BIT_INT_REASON);
  698. intr_inst_index = 0; // in case of coda seriese. treats intr_inst_index is already 0
  699. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason, sizeof(u32), &s_kfifo_lock);
  700. #else
  701. dev->interrupt_reason = ReadVpuRegister(BIT_INT_REASON);
  702. #endif
  703. WriteVpuRegister(BIT_INT_CLEAR, 0x1);
  704. }
  705. }
  706. else {
  707. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  708. continue;
  709. }
  710. #ifdef SUPPORT_MULTI_INST_INTR
  711. DPRINTK("[VPUDRV] product: 0x%08x intr_reason: 0x%08x\n\n", product_code, intr_reason);
  712. #else
  713. DPRINTK("[VPUDRV] product: 0x%08x intr_reason: 0x%08x\n", product_code, dev->interrupt_reason);
  714. #endif
  715. }
  716. if (dev->async_queue)
  717. kill_fasync(&dev->async_queue, SIGIO, POLL_IN); /* notify the interrupt to user space */
  718. #ifdef SUPPORT_MULTI_INST_INTR
  719. if (intr_inst_index >= 0 && intr_inst_index < MAX_NUM_INSTANCE) {
  720. s_interrupt_flag[intr_inst_index]= 1;
  721. wake_up_interruptible(&s_interrupt_wait_q[intr_inst_index]);
  722. }
  723. #else
  724. s_interrupt_flag = 1;
  725. wake_up_interruptible(&s_interrupt_wait_q);
  726. #endif
  727. DPRINTK("[VPUDRV][-]%s\n", __func__);
  728. return IRQ_HANDLED;
  729. }
  730. static int vpu_open(struct inode *inode, struct file *filp)
  731. {
  732. DPRINTK("[VPUDRV][+] %s\n", __func__);
  733. pm_runtime_get_sync(s_vpu_clk->dev);
  734. spin_lock(&s_vpu_lock);
  735. s_vpu_drv_context.open_count++;
  736. filp->private_data = (void *)(&s_vpu_drv_context);
  737. spin_unlock(&s_vpu_lock);
  738. DPRINTK("[VPUDRV][-] %s\n", __func__);
  739. return 0;
  740. }
  741. /*static int vpu_ioctl(struct inode *inode, struct file *filp, u_int cmd, u_long arg) // for kernel 2.6.9 of C&M*/
  742. static long vpu_ioctl(struct file *filp, u_int cmd, u_long arg)
  743. {
  744. int ret = 0;
  745. struct vpu_drv_context_t *dev = (struct vpu_drv_context_t *)filp->private_data;
  746. switch (cmd) {
  747. case VDI_IOCTL_GET_PHYSICAL_MEMORY:
  748. {
  749. vpudrv_buffer_pool_t *vbp = NULL;
  750. void *user_address = NULL;
  751. struct task_struct *my_struct = NULL;
  752. struct mm_struct *mm = NULL;
  753. unsigned long address = 0;
  754. pgd_t *pgd = NULL;
  755. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  756. vbp = kzalloc(sizeof(*vbp), GFP_KERNEL);
  757. if (!vbp) {
  758. up(&s_vpu_sem);
  759. return -ENOMEM;
  760. }
  761. ret = copy_from_user(&(vbp->vb), (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  762. if (ret) {
  763. kfree(vbp);
  764. up(&s_vpu_sem);
  765. return -EFAULT;
  766. }
  767. user_address = (void *)vbp->vb.virt_addr;
  768. my_struct = get_current();
  769. mm = my_struct->mm;
  770. address = (unsigned long)user_address;
  771. pgd = pgd_offset(mm, address);
  772. if (!pgd_none(*pgd) && !pgd_bad(*pgd)) {
  773. p4d_t *p4d = p4d_offset(pgd, address);
  774. pud_t *pud = pud_offset(p4d, address);
  775. if (!pud_none(*pud) && !pud_bad(*pud)) {
  776. pmd_t *pmd = pmd_offset(pud, address);
  777. if (!pmd_none(*pmd) && !pmd_bad(*pmd)) {
  778. pte_t *pte = pte_offset_map(pmd, address);
  779. if (!pte_none(*pte)) {
  780. struct page *pg = pte_page(*pte);
  781. unsigned long phys = page_to_phys(pg);
  782. unsigned long virt = (unsigned long)phys_to_virt(phys);
  783. printk("attach phy address = %lx, virt = %lx\r\n", phys, virt);
  784. vbp->vb.phys_addr = phys;
  785. vbp->vb.base = virt;
  786. }
  787. pte_unmap(pte);
  788. }
  789. }
  790. }
  791. ret = copy_to_user((void __user *)arg, &(vbp->vb), sizeof(vpudrv_buffer_t));
  792. if (ret) {
  793. kfree(vbp);
  794. ret = -EFAULT;
  795. up(&s_vpu_sem);
  796. break;
  797. }
  798. vbp->filp = filp;
  799. spin_lock(&s_vpu_lock);
  800. list_add(&vbp->list, &s_vbp_head);
  801. spin_unlock(&s_vpu_lock);
  802. up(&s_vpu_sem);
  803. }
  804. }
  805. break;
  806. case VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY:
  807. {
  808. vpudrv_buffer_pool_t *vbp;
  809. DPRINTK("[VPUDRV][+]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  810. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  811. vbp = kzalloc(sizeof(*vbp), GFP_KERNEL);
  812. if (!vbp) {
  813. up(&s_vpu_sem);
  814. return -ENOMEM;
  815. }
  816. ret = copy_from_user(&(vbp->vb), (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  817. if (ret) {
  818. kfree(vbp);
  819. up(&s_vpu_sem);
  820. return -EFAULT;
  821. }
  822. ret = vpu_alloc_dma_buffer(&(vbp->vb));
  823. if (ret == -1) {
  824. ret = -ENOMEM;
  825. kfree(vbp);
  826. up(&s_vpu_sem);
  827. break;
  828. }
  829. ret = copy_to_user((void __user *)arg, &(vbp->vb), sizeof(vpudrv_buffer_t));
  830. if (ret) {
  831. kfree(vbp);
  832. ret = -EFAULT;
  833. up(&s_vpu_sem);
  834. break;
  835. }
  836. vbp->filp = filp;
  837. spin_lock(&s_vpu_lock);
  838. list_add(&vbp->list, &s_vbp_head);
  839. spin_unlock(&s_vpu_lock);
  840. up(&s_vpu_sem);
  841. }
  842. DPRINTK("[VPUDRV][-]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  843. }
  844. break;
  845. case VDI_IOCTL_FREE_PHYSICALMEMORY:
  846. {
  847. vpudrv_buffer_pool_t *vbp, *n;
  848. vpudrv_buffer_t vb;
  849. DPRINTK("[VPUDRV][+]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  850. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  851. ret = copy_from_user(&vb, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  852. if (ret) {
  853. up(&s_vpu_sem);
  854. return -EACCES;
  855. }
  856. if (vb.base)
  857. vpu_free_dma_buffer(&vb);
  858. spin_lock(&s_vpu_lock);
  859. list_for_each_entry_safe(vbp, n, &s_vbp_head, list)
  860. {
  861. if (vbp->vb.base == vb.base) {
  862. list_del(&vbp->list);
  863. kfree(vbp);
  864. break;
  865. }
  866. }
  867. spin_unlock(&s_vpu_lock);
  868. up(&s_vpu_sem);
  869. }
  870. DPRINTK("[VPUDRV][-]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  871. }
  872. break;
  873. case VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO:
  874. {
  875. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  876. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO\n");
  877. if (s_video_memory.base != 0) {
  878. ret = copy_to_user((void __user *)arg, &s_video_memory, sizeof(vpudrv_buffer_t));
  879. if (ret != 0)
  880. ret = -EFAULT;
  881. } else {
  882. ret = -EFAULT;
  883. }
  884. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO\n");
  885. #endif
  886. }
  887. break;
  888. case VDI_IOCTL_WAIT_INTERRUPT:
  889. {
  890. vpudrv_intr_info_t info;
  891. #ifdef SUPPORT_MULTI_INST_INTR
  892. u32 intr_inst_index;
  893. u32 intr_reason_in_q;
  894. u32 interrupt_flag_in_q;
  895. #endif
  896. DPRINTK("[VPUDRV][+]VDI_IOCTL_WAIT_INTERRUPT\n");
  897. ret = copy_from_user(&info, (vpudrv_intr_info_t *)arg, sizeof(vpudrv_intr_info_t));
  898. if (ret != 0)
  899. {
  900. return -EFAULT;
  901. }
  902. #ifdef SUPPORT_MULTI_INST_INTR
  903. intr_inst_index = info.intr_inst_index;
  904. intr_reason_in_q = 0;
  905. interrupt_flag_in_q = kfifo_out_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason_in_q, sizeof(u32), &s_kfifo_lock);
  906. if (interrupt_flag_in_q > 0)
  907. {
  908. dev->interrupt_reason[intr_inst_index] = intr_reason_in_q;
  909. DPRINTK("[VPUDRV] Interrupt Remain : intr_inst_index=%d, intr_reason_in_q=0x%x, interrupt_flag_in_q=%d\n", intr_inst_index, intr_reason_in_q, interrupt_flag_in_q);
  910. goto INTERRUPT_REMAIN_IN_QUEUE;
  911. }
  912. #endif
  913. #ifdef SUPPORT_MULTI_INST_INTR
  914. #ifdef SUPPORT_TIMEOUT_RESOLUTION
  915. kt = ktime_set(0, info.timeout*1000*1000);
  916. ret = wait_event_interruptible_hrtimeout(s_interrupt_wait_q[intr_inst_index], s_interrupt_flag[intr_inst_index] != 0, kt);
  917. #else
  918. ret = wait_event_interruptible_timeout(s_interrupt_wait_q[intr_inst_index], s_interrupt_flag[intr_inst_index] != 0, msecs_to_jiffies(info.timeout));
  919. #endif
  920. #else
  921. ret = wait_event_interruptible_timeout(s_interrupt_wait_q, s_interrupt_flag != 0, msecs_to_jiffies(info.timeout));
  922. #endif
  923. #ifdef SUPPORT_TIMEOUT_RESOLUTION
  924. if (ret == -ETIME) {
  925. //DPRINTK("[VPUDRV][-]VDI_IOCTL_WAIT_INTERRUPT timeout = %d \n", info.timeout);
  926. break;
  927. }
  928. #endif
  929. if (!ret) {
  930. ret = -ETIME;
  931. break;
  932. }
  933. if (signal_pending(current)) {
  934. ret = -ERESTARTSYS;
  935. break;
  936. }
  937. #ifdef SUPPORT_MULTI_INST_INTR
  938. intr_reason_in_q = 0;
  939. interrupt_flag_in_q = kfifo_out_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason_in_q, sizeof(u32), &s_kfifo_lock);
  940. if (interrupt_flag_in_q > 0) {
  941. dev->interrupt_reason[intr_inst_index] = intr_reason_in_q;
  942. }
  943. else {
  944. dev->interrupt_reason[intr_inst_index] = 0;
  945. }
  946. #endif
  947. #ifdef SUPPORT_MULTI_INST_INTR
  948. DPRINTK("[VPUDRV] inst_index(%d), s_interrupt_flag(%d), reason(0x%08lx)\n", intr_inst_index, s_interrupt_flag[intr_inst_index], dev->interrupt_reason[intr_inst_index]);
  949. #else
  950. DPRINTK("[VPUDRV] s_interrupt_flag(%d), reason(0x%08lx)\n", s_interrupt_flag, dev->interrupt_reason);
  951. #endif
  952. #ifdef SUPPORT_MULTI_INST_INTR
  953. INTERRUPT_REMAIN_IN_QUEUE:
  954. info.intr_reason = dev->interrupt_reason[intr_inst_index];
  955. s_interrupt_flag[intr_inst_index] = 0;
  956. dev->interrupt_reason[intr_inst_index] = 0;
  957. #else
  958. info.intr_reason = dev->interrupt_reason;
  959. s_interrupt_flag = 0;
  960. dev->interrupt_reason = 0;
  961. #endif
  962. #ifdef VPU_IRQ_CONTROL
  963. enable_irq(s_vpu_irq);
  964. #endif
  965. ret = copy_to_user((void __user *)arg, &info, sizeof(vpudrv_intr_info_t));
  966. DPRINTK("[VPUDRV][-]VDI_IOCTL_WAIT_INTERRUPT\n");
  967. if (ret != 0)
  968. {
  969. return -EFAULT;
  970. }
  971. }
  972. break;
  973. case VDI_IOCTL_SET_CLOCK_GATE:
  974. {
  975. u32 clkgate;
  976. DPRINTK("[VPUDRV][+]VDI_IOCTL_SET_CLOCK_GATE\n");
  977. if (get_user(clkgate, (u32 __user *) arg))
  978. return -EFAULT;
  979. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  980. if (clkgate)
  981. vpu_clk_enable(s_vpu_clk);
  982. else
  983. vpu_clk_disable(s_vpu_clk);
  984. #endif
  985. DPRINTK("[VPUDRV][-]VDI_IOCTL_SET_CLOCK_GATE\n");
  986. }
  987. break;
  988. case VDI_IOCTL_GET_INSTANCE_POOL:
  989. {
  990. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_INSTANCE_POOL\n");
  991. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  992. if (s_instance_pool.base != 0) {
  993. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(vpudrv_buffer_t));
  994. if (ret != 0)
  995. ret = -EFAULT;
  996. } else {
  997. ret = copy_from_user(&s_instance_pool, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  998. if (ret == 0) {
  999. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1000. s_instance_pool.size = PAGE_ALIGN(s_instance_pool.size);
  1001. s_instance_pool.base = (unsigned long)vmalloc(s_instance_pool.size);
  1002. s_instance_pool.phys_addr = s_instance_pool.base;
  1003. if (s_instance_pool.base != 0)
  1004. #else
  1005. if (vpu_alloc_dma_buffer(&s_instance_pool) != -1)
  1006. #endif
  1007. {
  1008. memset((void *)s_instance_pool.base, 0x0, s_instance_pool.size); /*clearing memory*/
  1009. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(vpudrv_buffer_t));
  1010. if (ret == 0) {
  1011. /* success to get memory for instance pool */
  1012. up(&s_vpu_sem);
  1013. break;
  1014. }
  1015. }
  1016. }
  1017. ret = -EFAULT;
  1018. }
  1019. up(&s_vpu_sem);
  1020. }
  1021. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_INSTANCE_POOL\n");
  1022. }
  1023. break;
  1024. case VDI_IOCTL_GET_COMMON_MEMORY:
  1025. {
  1026. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_COMMON_MEMORY\n");
  1027. if (s_common_memory.base != 0) {
  1028. ret = copy_to_user((void __user *)arg, &s_common_memory, sizeof(vpudrv_buffer_t));
  1029. if (ret != 0)
  1030. ret = -EFAULT;
  1031. } else {
  1032. ret = copy_from_user(&s_common_memory, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  1033. if (ret == 0) {
  1034. if (vpu_alloc_dma_buffer(&s_common_memory) != -1) {
  1035. ret = copy_to_user((void __user *)arg, &s_common_memory, sizeof(vpudrv_buffer_t));
  1036. if (ret == 0) {
  1037. /* success to get memory for common memory */
  1038. break;
  1039. }
  1040. }
  1041. }
  1042. ret = -EFAULT;
  1043. }
  1044. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_COMMON_MEMORY\n");
  1045. }
  1046. break;
  1047. case VDI_IOCTL_OPEN_INSTANCE:
  1048. {
  1049. vpudrv_inst_info_t inst_info;
  1050. vpudrv_instanace_list_t *vil, *n;
  1051. vil = kzalloc(sizeof(*vil), GFP_KERNEL);
  1052. if (!vil)
  1053. return -ENOMEM;
  1054. if (copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t)))
  1055. return -EFAULT;
  1056. vil->inst_idx = inst_info.inst_idx;
  1057. vil->core_idx = inst_info.core_idx;
  1058. vil->filp = filp;
  1059. spin_lock(&s_vpu_lock);
  1060. list_add(&vil->list, &s_inst_list_head);
  1061. inst_info.inst_open_count = 0; /* counting the current open instance number */
  1062. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  1063. {
  1064. if (vil->core_idx == inst_info.core_idx)
  1065. inst_info.inst_open_count++;
  1066. }
  1067. #ifdef SUPPORT_MULTI_INST_INTR
  1068. kfifo_reset(&s_interrupt_pending_q[inst_info.inst_idx]);
  1069. #endif
  1070. spin_unlock(&s_vpu_lock);
  1071. s_vpu_open_ref_count++; /* flag just for that vpu is in opened or closed */
  1072. if (copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t))) {
  1073. kfree(vil);
  1074. return -EFAULT;
  1075. }
  1076. DPRINTK("[VPUDRV] VDI_IOCTL_OPEN_INSTANCE core_idx=%d, inst_idx=%d, s_vpu_open_ref_count=%d, inst_open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, s_vpu_open_ref_count, inst_info.inst_open_count);
  1077. }
  1078. break;
  1079. case VDI_IOCTL_CLOSE_INSTANCE:
  1080. {
  1081. vpudrv_inst_info_t inst_info;
  1082. vpudrv_instanace_list_t *vil, *n;
  1083. u32 found = 0;
  1084. DPRINTK("[VPUDRV][+]VDI_IOCTL_CLOSE_INSTANCE\n");
  1085. if (copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t)))
  1086. return -EFAULT;
  1087. spin_lock(&s_vpu_lock);
  1088. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  1089. {
  1090. if (vil->inst_idx == inst_info.inst_idx && vil->core_idx == inst_info.core_idx) {
  1091. list_del(&vil->list);
  1092. kfree(vil);
  1093. found = 1;
  1094. break;
  1095. }
  1096. }
  1097. if (0 == found) {
  1098. spin_unlock(&s_vpu_lock);
  1099. return -EINVAL;
  1100. }
  1101. inst_info.inst_open_count = 0; /* counting the current open instance number */
  1102. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  1103. {
  1104. if (vil->core_idx == inst_info.core_idx)
  1105. inst_info.inst_open_count++;
  1106. }
  1107. #ifdef SUPPORT_MULTI_INST_INTR
  1108. kfifo_reset(&s_interrupt_pending_q[inst_info.inst_idx]);
  1109. #endif
  1110. spin_unlock(&s_vpu_lock);
  1111. s_vpu_open_ref_count--; /* flag just for that vpu is in opened or closed */
  1112. if (copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t)))
  1113. return -EFAULT;
  1114. DPRINTK("[VPUDRV] VDI_IOCTL_CLOSE_INSTANCE core_idx=%d, inst_idx=%d, s_vpu_open_ref_count=%d, inst_open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, s_vpu_open_ref_count, inst_info.inst_open_count);
  1115. }
  1116. break;
  1117. case VDI_IOCTL_GET_INSTANCE_NUM:
  1118. {
  1119. vpudrv_inst_info_t inst_info;
  1120. vpudrv_instanace_list_t *vil, *n;
  1121. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_INSTANCE_NUM\n");
  1122. ret = copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t));
  1123. if (ret != 0)
  1124. break;
  1125. spin_lock(&s_vpu_lock);
  1126. inst_info.inst_open_count = 0;
  1127. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  1128. {
  1129. if (vil->core_idx == inst_info.core_idx)
  1130. inst_info.inst_open_count++;
  1131. }
  1132. spin_unlock(&s_vpu_lock);
  1133. ret = copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t));
  1134. DPRINTK("[VPUDRV] VDI_IOCTL_GET_INSTANCE_NUM core_idx=%d, inst_idx=%d, open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, inst_info.inst_open_count);
  1135. }
  1136. break;
  1137. case VDI_IOCTL_RESET:
  1138. {
  1139. vpu_hw_reset();
  1140. }
  1141. break;
  1142. case VDI_IOCTL_GET_REGISTER_INFO:
  1143. {
  1144. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_REGISTER_INFO\n");
  1145. ret = copy_to_user((void __user *)arg, &s_vpu_register, sizeof(vpudrv_buffer_t));
  1146. if (ret != 0)
  1147. ret = -EFAULT;
  1148. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_REGISTER_INFO s_vpu_register.phys_addr==0x%lx, s_vpu_register.virt_addr=0x%lx, s_vpu_register.size=%d\n", s_vpu_register.phys_addr , s_vpu_register.virt_addr, s_vpu_register.size);
  1149. }
  1150. break;
  1151. case VDI_IOCTL_FLUSH_DCACHE:
  1152. {
  1153. vpudrv_flush_cache_t cache_info;
  1154. ret = copy_from_user(&cache_info, (vpudrv_flush_cache_t *)arg, sizeof(vpudrv_flush_cache_t));
  1155. if (ret != 0)
  1156. ret = -EFAULT;
  1157. if(cache_info.flag)
  1158. starfive_flush_dcache(cache_info.start,cache_info.size);
  1159. }
  1160. break;
  1161. case VDI_IOCTL_CPUFREQ_SAVEENV:
  1162. {
  1163. #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_USE_PLL_DYNAMIC_FREQ)
  1164. vpu_freq_save_env();
  1165. #endif
  1166. }
  1167. break;
  1168. case VDI_IOCTL_CPUFREQ_PUTENV:
  1169. {
  1170. #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_USE_PLL_DYNAMIC_FREQ)
  1171. vpu_freq_put_env();
  1172. #endif
  1173. }
  1174. break;
  1175. default:
  1176. {
  1177. printk(KERN_ERR "[VPUDRV] No such IOCTL, cmd is %d\n", cmd);
  1178. }
  1179. break;
  1180. }
  1181. return ret;
  1182. }
  1183. static ssize_t vpu_read(struct file *filp, char __user *buf, size_t len, loff_t *ppos)
  1184. {
  1185. return -1;
  1186. }
  1187. static ssize_t vpu_write(struct file *filp, const char __user *buf, size_t len, loff_t *ppos)
  1188. {
  1189. /* DPRINTK("[VPUDRV] vpu_write len=%d\n", (int)len); */
  1190. if (!buf) {
  1191. printk(KERN_ERR "[VPUDRV] vpu_write buf = NULL error \n");
  1192. return -EFAULT;
  1193. }
  1194. if (len == sizeof(vpu_bit_firmware_info_t)) {
  1195. vpu_bit_firmware_info_t *bit_firmware_info;
  1196. bit_firmware_info = kmalloc(sizeof(vpu_bit_firmware_info_t), GFP_KERNEL);
  1197. if (!bit_firmware_info) {
  1198. printk(KERN_ERR "[VPUDRV] vpu_write bit_firmware_info allocation error \n");
  1199. return -EFAULT;
  1200. }
  1201. if (copy_from_user(bit_firmware_info, buf, len)) {
  1202. printk(KERN_ERR "[VPUDRV] vpu_write copy_from_user error for bit_firmware_info\n");
  1203. return -EFAULT;
  1204. }
  1205. if (bit_firmware_info->size == sizeof(vpu_bit_firmware_info_t)) {
  1206. DPRINTK("[VPUDRV] vpu_write set bit_firmware_info coreIdx=0x%x, reg_base_offset=0x%x size=0x%x, bit_code[0]=0x%x\n",
  1207. bit_firmware_info->core_idx, (int)bit_firmware_info->reg_base_offset, bit_firmware_info->size, bit_firmware_info->bit_code[0]);
  1208. if (bit_firmware_info->core_idx > MAX_NUM_VPU_CORE) {
  1209. printk(KERN_ERR "[VPUDRV] vpu_write coreIdx[%d] is exceeded than MAX_NUM_VPU_CORE[%d]\n", bit_firmware_info->core_idx, MAX_NUM_VPU_CORE);
  1210. return -ENODEV;
  1211. }
  1212. memcpy((void *)&s_bit_firmware_info[bit_firmware_info->core_idx], bit_firmware_info, sizeof(vpu_bit_firmware_info_t));
  1213. kfree(bit_firmware_info);
  1214. return len;
  1215. }
  1216. kfree(bit_firmware_info);
  1217. }
  1218. return -1;
  1219. }
  1220. static int vpu_release(struct inode *inode, struct file *filp)
  1221. {
  1222. int ret = 0;
  1223. u32 open_count;
  1224. #ifdef SUPPORT_MULTI_INST_INTR
  1225. int i;
  1226. #endif
  1227. DPRINTK("[VPUDRV] vpu_release\n");
  1228. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  1229. /* found and free the not handled buffer by user applications */
  1230. vpu_free_buffers(filp);
  1231. /* found and free the not closed instance by user applications */
  1232. vpu_free_instances(filp);
  1233. spin_lock(&s_vpu_lock);
  1234. s_vpu_drv_context.open_count--;
  1235. open_count = s_vpu_drv_context.open_count;
  1236. spin_unlock(&s_vpu_lock);
  1237. if (open_count == 0) {
  1238. #ifdef SUPPORT_MULTI_INST_INTR
  1239. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1240. kfifo_reset(&s_interrupt_pending_q[i]);
  1241. }
  1242. #endif
  1243. if (s_instance_pool.base) {
  1244. DPRINTK("[VPUDRV] free instance pool\n");
  1245. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1246. vfree((const void *)s_instance_pool.base);
  1247. #else
  1248. vpu_free_dma_buffer(&s_instance_pool);
  1249. #endif
  1250. s_instance_pool.base = 0;
  1251. }
  1252. }
  1253. }
  1254. up(&s_vpu_sem);
  1255. pm_runtime_put_sync(s_vpu_clk->dev);
  1256. return 0;
  1257. }
  1258. static int vpu_fasync(int fd, struct file *filp, int mode)
  1259. {
  1260. struct vpu_drv_context_t *dev = (struct vpu_drv_context_t *)filp->private_data;
  1261. return fasync_helper(fd, filp, mode, &dev->async_queue);
  1262. }
  1263. static int vpu_map_to_register(struct file *fp, struct vm_area_struct *vm)
  1264. {
  1265. unsigned long pfn;
  1266. vm->vm_flags |= VM_IO | VM_RESERVED;
  1267. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  1268. pfn = s_vpu_register.phys_addr >> PAGE_SHIFT;
  1269. return remap_pfn_range(vm, vm->vm_start, pfn, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1270. }
  1271. static int vpu_map_to_physical_memory(struct file *fp, struct vm_area_struct *vm)
  1272. {
  1273. vm->vm_flags |= VM_IO | VM_RESERVED;
  1274. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  1275. return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1276. }
  1277. static int vpu_map_to_instance_pool_memory(struct file *fp, struct vm_area_struct *vm)
  1278. {
  1279. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1280. int ret;
  1281. long length = vm->vm_end - vm->vm_start;
  1282. unsigned long start = vm->vm_start;
  1283. char *vmalloc_area_ptr = (char *)s_instance_pool.base;
  1284. unsigned long pfn;
  1285. vm->vm_flags |= VM_RESERVED;
  1286. /* loop over all pages, map it page individually */
  1287. while (length > 0)
  1288. {
  1289. pfn = vmalloc_to_pfn(vmalloc_area_ptr);
  1290. if ((ret = remap_pfn_range(vm, start, pfn, PAGE_SIZE, PAGE_SHARED)) < 0) {
  1291. return ret;
  1292. }
  1293. start += PAGE_SIZE;
  1294. vmalloc_area_ptr += PAGE_SIZE;
  1295. length -= PAGE_SIZE;
  1296. }
  1297. return 0;
  1298. #else
  1299. vm->vm_flags |= VM_RESERVED;
  1300. return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1301. #endif
  1302. }
  1303. /*!
  1304. * @brief memory map interface for vpu file operation
  1305. * @return 0 on success or negative error code on error
  1306. */
  1307. static int vpu_mmap(struct file *fp, struct vm_area_struct *vm)
  1308. {
  1309. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1310. if (vm->vm_pgoff == 0)
  1311. return vpu_map_to_instance_pool_memory(fp, vm);
  1312. if (vm->vm_pgoff == (s_vpu_register.phys_addr>>PAGE_SHIFT))
  1313. return vpu_map_to_register(fp, vm);
  1314. return vpu_map_to_physical_memory(fp, vm);
  1315. #else
  1316. if (vm->vm_pgoff) {
  1317. if (vm->vm_pgoff == (s_instance_pool.phys_addr>>PAGE_SHIFT))
  1318. return vpu_map_to_instance_pool_memory(fp, vm);
  1319. return vpu_map_to_physical_memory(fp, vm);
  1320. } else {
  1321. return vpu_map_to_register(fp, vm);
  1322. }
  1323. #endif
  1324. }
  1325. struct file_operations vpu_fops = {
  1326. .owner = THIS_MODULE,
  1327. .open = vpu_open,
  1328. .read = vpu_read,
  1329. .write = vpu_write,
  1330. /*.ioctl = vpu_ioctl, // for kernel 2.6.9 of C&M*/
  1331. .unlocked_ioctl = vpu_ioctl,
  1332. .release = vpu_release,
  1333. .fasync = vpu_fasync,
  1334. .mmap = vpu_mmap,
  1335. };
  1336. static int vpu_probe(struct platform_device *pdev)
  1337. {
  1338. int err = 0;
  1339. struct resource *res = NULL;
  1340. struct device *devices;
  1341. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1342. struct resource res_cma;
  1343. struct device_node *node;
  1344. #endif
  1345. int irq = -1;
  1346. DPRINTK("[VPUDRV] vpu_probe\n");
  1347. if(pdev){
  1348. vpu_dev = &pdev->dev;
  1349. vpu_dev->coherent_dma_mask = 0xffffffff;;
  1350. dev_info(vpu_dev,"device init.\n");
  1351. }
  1352. if (pdev)
  1353. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1354. if (res) {/* if platform driver is implemented */
  1355. s_vpu_register.phys_addr = res->start;
  1356. s_vpu_register.virt_addr = (unsigned long)ioremap_nocache(res->start, res->end - res->start);
  1357. s_vpu_register.size = res->end - res->start;
  1358. DPRINTK("[VPUDRV] : vpu base address get from platform driver physical base addr==0x%lx, virtual base=0x%lx\n", s_vpu_register.phys_addr , s_vpu_register.virt_addr);
  1359. } else {
  1360. s_vpu_register.phys_addr = VPU_REG_BASE_ADDR;
  1361. s_vpu_register.virt_addr = (unsigned long)ioremap_nocache(s_vpu_register.phys_addr, VPU_REG_SIZE);
  1362. s_vpu_register.size = VPU_REG_SIZE;
  1363. DPRINTK("[VPUDRV] : vpu base address get from defined value physical base addr==0x%lx, virtual base=0x%lx\n", s_vpu_register.phys_addr, s_vpu_register.virt_addr);
  1364. }
  1365. /* get the major number of the character device */
  1366. if ((alloc_chrdev_region(&s_vpu_devt, 0, 1, VPU_DEV_NAME)) < 0) {
  1367. err = -EBUSY;
  1368. printk(KERN_ERR "could not allocate major number\n");
  1369. goto ERROR_PROVE_DEVICE;
  1370. }
  1371. printk(KERN_INFO "SUCCESS alloc_chrdev_region\n");
  1372. s_vpu_major = MAJOR(s_vpu_devt);
  1373. /* initialize the device structure and register the device with the kernel */
  1374. cdev_init(&s_vpu_cdev, &vpu_fops);
  1375. if ((cdev_add(&s_vpu_cdev, s_vpu_devt, 1)) < 0) {
  1376. err = -EBUSY;
  1377. printk(KERN_ERR "could not allocate chrdev\n");
  1378. goto ERROR_PROVE_DEVICE;
  1379. }
  1380. s_vpu_class = class_create(THIS_MODULE, VPU_DEV_NAME);
  1381. if (IS_ERR(s_vpu_class)) {
  1382. dev_err(vpu_dev, "class creat error.\n");
  1383. goto ERROR_CRART_CLASS;
  1384. }
  1385. devices = device_create(s_vpu_class, 0, MKDEV(s_vpu_major, 0),
  1386. NULL, VPU_DEV_NAME);
  1387. if (IS_ERR(devices)) {
  1388. dev_err(vpu_dev, "device creat error.\n");
  1389. goto ERROR_CREAT_DEVICE;
  1390. }
  1391. if (pdev)
  1392. s_vpu_clk = vpu_clk_get(pdev);
  1393. else
  1394. s_vpu_clk = vpu_clk_get(NULL);
  1395. if (!s_vpu_clk)
  1396. printk(KERN_ERR "[VPUDRV] : not support clock controller.\n");
  1397. else
  1398. DPRINTK("[VPUDRV] : get clock controller s_vpu_clk=%p\n", s_vpu_clk);
  1399. #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_USE_PLL_DYNAMIC_FREQ)
  1400. vpu_freq_init(&pdev->dev);
  1401. #endif
  1402. vpu_pmu_enable(s_vpu_clk->dev);
  1403. vpu_clk_enable(s_vpu_clk);
  1404. reset_control_deassert(s_vpu_clk->resets);
  1405. #ifdef VPU_SUPPORT_ISR
  1406. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1407. if (pdev)
  1408. irq = platform_get_irq(pdev, 0);
  1409. if (irq >= 0) {/* if platform driver is implemented */
  1410. s_vpu_irq = irq;
  1411. DPRINTK("[VPUDRV] : vpu irq number get from platform driver irq=0x%x\n", s_vpu_irq);
  1412. } else {
  1413. DPRINTK("[VPUDRV] : vpu irq number get from defined value irq=0x%x\n", s_vpu_irq);
  1414. }
  1415. #else
  1416. DPRINTK("[VPUDRV] : vpu irq number get from defined value irq=0x%x\n", s_vpu_irq);
  1417. #endif
  1418. err = request_irq(s_vpu_irq, vpu_irq_handler, 0, pdev->name, (void *)(&s_vpu_drv_context));
  1419. if (err) {
  1420. printk(KERN_ERR "[VPUDRV] : fail to register interrupt handler\n");
  1421. goto ERROR_PROVE_DEVICE;
  1422. }
  1423. #endif
  1424. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1425. node = of_parse_phandle(vpu_dev->of_node, "memory-region", 0);
  1426. if(node){
  1427. dev_info(vpu_dev, "Get mem form memory-region\n");
  1428. of_address_to_resource(node, 0, &res_cma);
  1429. s_video_memory.size = resource_size(&res_cma);
  1430. s_video_memory.phys_addr = res_cma.start;
  1431. }else{
  1432. dev_info(vpu_dev, "Get mem form memory-region fiiled.please check the dts file.\n");
  1433. return 0;
  1434. }
  1435. s_video_memory.base = (unsigned long)ioremap_nocache(DRAM_MEM2SYS(s_video_memory.phys_addr), PAGE_ALIGN(s_video_memory.size));
  1436. if (!s_video_memory.base) {
  1437. printk(KERN_ERR "[VPUDRV] : fail to remap video memory physical phys_addr=0x%lx, base=0x%lx, size=%d\n", s_video_memory.phys_addr, s_video_memory.base, (int)s_video_memory.size);
  1438. goto ERROR_PROVE_DEVICE;
  1439. }
  1440. if (vmem_init(&s_vmem, s_video_memory.phys_addr, s_video_memory.size) < 0) {
  1441. printk(KERN_ERR "[VPUDRV] : fail to init vmem system\n");
  1442. goto ERROR_PROVE_DEVICE;
  1443. }
  1444. DPRINTK("[VPUDRV] success to probe vpu device with reserved video memory phys_addr=0x%lx, base=0x%lx, size=%d\n", s_video_memory.phys_addr, s_video_memory.base,s_video_memory.size);
  1445. #else
  1446. DPRINTK("[VPUDRV] success to probe vpu device with non reserved video memory\n");
  1447. #endif
  1448. return 0;
  1449. ERROR_CREAT_DEVICE:
  1450. class_destroy(s_vpu_class);
  1451. ERROR_CRART_CLASS:
  1452. cdev_del(&s_vpu_cdev);
  1453. ERROR_PROVE_DEVICE:
  1454. if (s_vpu_major)
  1455. unregister_chrdev_region(s_vpu_major, 1);
  1456. if (s_vpu_register.virt_addr)
  1457. iounmap((void *)s_vpu_register.virt_addr);
  1458. return err;
  1459. }
  1460. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1461. static int vpu_remove(struct platform_device *pdev)
  1462. {
  1463. DPRINTK("[VPUDRV] vpu_remove\n");
  1464. if (s_instance_pool.base) {
  1465. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1466. vfree((const void *)s_instance_pool.base);
  1467. #else
  1468. vpu_free_dma_buffer(&s_instance_pool);
  1469. #endif
  1470. s_instance_pool.base = 0;
  1471. }
  1472. if (s_common_memory.base) {
  1473. vpu_free_dma_buffer(&s_common_memory);
  1474. s_common_memory.base = 0;
  1475. }
  1476. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1477. if (s_video_memory.base) {
  1478. iounmap((void *)s_video_memory.base);
  1479. s_video_memory.base = 0;
  1480. vmem_exit(&s_vmem);
  1481. }
  1482. #endif
  1483. if (s_vpu_major > 0) {
  1484. device_destroy(s_vpu_class, MKDEV(s_vpu_major, 0));
  1485. class_destroy(s_vpu_class);
  1486. cdev_del(&s_vpu_cdev);
  1487. unregister_chrdev_region(s_vpu_devt, 1);
  1488. s_vpu_major = 0;
  1489. }
  1490. #ifdef VPU_SUPPORT_ISR
  1491. if (s_vpu_irq)
  1492. free_irq(s_vpu_irq, &s_vpu_drv_context);
  1493. #endif
  1494. if (s_vpu_register.virt_addr)
  1495. iounmap((void *)s_vpu_register.virt_addr);
  1496. vpu_clk_put(s_vpu_clk);
  1497. vpu_pmu_disable(s_vpu_clk->dev);
  1498. return 0;
  1499. }
  1500. #endif /*VPU_SUPPORT_PLATFORM_DRIVER_REGISTER*/
  1501. #if defined(VPU_SUPPORT_PLATFORM_DRIVER_REGISTER) && defined(CONFIG_PM)
  1502. #define W5_MAX_CODE_BUF_SIZE (512*1024)
  1503. #define W5_CMD_INIT_VPU (0x0001)
  1504. #define W5_CMD_SLEEP_VPU (0x0004)
  1505. #define W5_CMD_WAKEUP_VPU (0x0002)
  1506. static void Wave5BitIssueCommand(int core, u32 cmd)
  1507. {
  1508. WriteVpuRegister(W5_VPU_BUSY_STATUS, 1);
  1509. WriteVpuRegister(W5_COMMAND, cmd);
  1510. WriteVpuRegister(W5_VPU_HOST_INT_REQ, 1);
  1511. return;
  1512. }
  1513. static int __maybe_unused vpu_runtime_suspend(struct device *dev)
  1514. {
  1515. reset_control_assert(s_vpu_clk->resets);
  1516. vpu_clk_disable(s_vpu_clk);
  1517. return 0;
  1518. }
  1519. static int __maybe_unused vpu_runtime_resume(struct device *dev)
  1520. {
  1521. vpu_clk_enable(s_vpu_clk);
  1522. return reset_control_deassert(s_vpu_clk->resets);
  1523. }
  1524. #ifdef CONFIG_PM_SLEEP
  1525. static int __maybe_unused vpu_suspend(struct device *dev)
  1526. {
  1527. int i;
  1528. int core;
  1529. unsigned long timeout = jiffies + HZ; /* vpu wait timeout to 1sec */
  1530. int product_code;
  1531. DPRINTK("[VPUDRV] vpu_suspend\n");
  1532. pm_runtime_get_sync(dev);
  1533. if (s_vpu_open_ref_count > 0) {
  1534. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  1535. if (s_bit_firmware_info[core].size == 0)
  1536. continue;
  1537. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  1538. if (PRODUCT_CODE_W_SERIES(product_code)) {
  1539. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1540. if (time_after(jiffies, timeout)) {
  1541. DPRINTK("SLEEP_VPU BUSY timeout");
  1542. goto DONE_SUSPEND;
  1543. }
  1544. }
  1545. Wave5BitIssueCommand(core, W5_CMD_SLEEP_VPU);
  1546. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1547. if (time_after(jiffies, timeout)) {
  1548. DPRINTK("SLEEP_VPU BUSY timeout");
  1549. goto DONE_SUSPEND;
  1550. }
  1551. }
  1552. if (ReadVpuRegister(W5_RET_SUCCESS) == 0) {
  1553. DPRINTK("SLEEP_VPU failed [0x%x]", ReadVpuRegister(W5_RET_FAIL_REASON));
  1554. goto DONE_SUSPEND;
  1555. }
  1556. }
  1557. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  1558. while (ReadVpuRegister(BIT_BUSY_FLAG)) {
  1559. if (time_after(jiffies, timeout))
  1560. goto DONE_SUSPEND;
  1561. }
  1562. for (i = 0; i < 64; i++)
  1563. s_vpu_reg_store[core][i] = ReadVpuRegister(BIT_BASE+(0x100+(i * 4)));
  1564. }
  1565. else {
  1566. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  1567. goto DONE_SUSPEND;
  1568. }
  1569. }
  1570. }
  1571. DONE_SUSPEND:
  1572. pm_runtime_put_sync(dev);
  1573. pm_runtime_force_suspend(dev);
  1574. return 0;
  1575. }
  1576. static int __maybe_unused vpu_resume(struct device *dev)
  1577. {
  1578. int i;
  1579. int core;
  1580. u32 val;
  1581. unsigned long timeout = jiffies + HZ; /* vpu wait timeout to 1sec */
  1582. int product_code;
  1583. unsigned long code_base;
  1584. u32 code_size;
  1585. u32 remap_size;
  1586. int regVal;
  1587. u32 hwOption = 0;
  1588. DPRINTK("[VPUDRV] vpu_resume\n");
  1589. pm_runtime_force_resume(dev);
  1590. pm_runtime_get_sync(dev);
  1591. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  1592. if (s_bit_firmware_info[core].size == 0) {
  1593. continue;
  1594. }
  1595. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  1596. if (PRODUCT_CODE_W_SERIES(product_code)) {
  1597. code_base = s_common_memory.phys_addr;
  1598. /* ALIGN TO 4KB */
  1599. code_size = (W5_MAX_CODE_BUF_SIZE&~0xfff);
  1600. if (code_size < s_bit_firmware_info[core].size*2) {
  1601. goto DONE_WAKEUP;
  1602. }
  1603. regVal = 0;
  1604. WriteVpuRegister(W5_PO_CONF, regVal);
  1605. /* Reset All blocks */
  1606. regVal = 0x7ffffff;
  1607. WriteVpuRegister(W5_VPU_RESET_REQ, regVal); /*Reset All blocks*/
  1608. /* Waiting reset done */
  1609. while (ReadVpuRegister(W5_VPU_RESET_STATUS)) {
  1610. if (time_after(jiffies, timeout))
  1611. goto DONE_WAKEUP;
  1612. }
  1613. WriteVpuRegister(W5_VPU_RESET_REQ, 0);
  1614. /* remap page size */
  1615. remap_size = (code_size >> 12) & 0x1ff;
  1616. regVal = 0x80000000 | (W5_REMAP_CODE_INDEX<<12) | (0 << 16) | (1<<11) | remap_size;
  1617. WriteVpuRegister(W5_VPU_REMAP_CTRL, regVal);
  1618. WriteVpuRegister(W5_VPU_REMAP_VADDR,0x00000000); /* DO NOT CHANGE! */
  1619. WriteVpuRegister(W5_VPU_REMAP_PADDR,code_base);
  1620. WriteVpuRegister(W5_ADDR_CODE_BASE, code_base);
  1621. WriteVpuRegister(W5_CODE_SIZE, code_size);
  1622. WriteVpuRegister(W5_CODE_PARAM, 0);
  1623. WriteVpuRegister(W5_INIT_VPU_TIME_OUT_CNT, timeout);
  1624. WriteVpuRegister(W5_HW_OPTION, hwOption);
  1625. /* Interrupt */
  1626. if (product_code == WAVE521_CODE || product_code == WAVE521C_CODE ) {
  1627. regVal = (1<<INT_WAVE5_ENC_SET_PARAM);
  1628. regVal |= (1<<INT_WAVE5_ENC_PIC);
  1629. regVal |= (1<<INT_WAVE5_INIT_SEQ);
  1630. regVal |= (1<<INT_WAVE5_DEC_PIC);
  1631. regVal |= (1<<INT_WAVE5_BSBUF_EMPTY);
  1632. }
  1633. else {
  1634. // decoder
  1635. regVal = (1<<INT_WAVE5_INIT_SEQ);
  1636. regVal |= (1<<INT_WAVE5_DEC_PIC);
  1637. regVal |= (1<<INT_WAVE5_BSBUF_EMPTY);
  1638. }
  1639. WriteVpuRegister(W5_VPU_VINT_ENABLE, regVal);
  1640. Wave5BitIssueCommand(core, W5_CMD_WAKEUP_VPU);
  1641. WriteVpuRegister(W5_VPU_REMAP_CORE_START, 1);
  1642. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1643. if (time_after(jiffies, timeout))
  1644. goto DONE_WAKEUP;
  1645. }
  1646. if (ReadVpuRegister(W5_RET_SUCCESS) == 0) {
  1647. DPRINTK("WAKEUP_VPU failed [0x%x]", ReadVpuRegister(W5_RET_FAIL_REASON));
  1648. goto DONE_WAKEUP;
  1649. }
  1650. }
  1651. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  1652. WriteVpuRegister(BIT_CODE_RUN, 0);
  1653. /*---- LOAD BOOT CODE*/
  1654. for (i = 0; i < 512; i++) {
  1655. val = s_bit_firmware_info[core].bit_code[i];
  1656. WriteVpuRegister(BIT_CODE_DOWN, ((i << 16) | val));
  1657. }
  1658. for (i = 0 ; i < 64 ; i++)
  1659. WriteVpuRegister(BIT_BASE+(0x100+(i * 4)), s_vpu_reg_store[core][i]);
  1660. WriteVpuRegister(BIT_BUSY_FLAG, 1);
  1661. WriteVpuRegister(BIT_CODE_RESET, 1);
  1662. WriteVpuRegister(BIT_CODE_RUN, 1);
  1663. while (ReadVpuRegister(BIT_BUSY_FLAG)) {
  1664. if (time_after(jiffies, timeout))
  1665. goto DONE_WAKEUP;
  1666. }
  1667. }
  1668. else {
  1669. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  1670. goto DONE_WAKEUP;
  1671. }
  1672. }
  1673. DONE_WAKEUP:
  1674. pm_runtime_put_sync(dev);
  1675. return 0;
  1676. }
  1677. #endif /* CONFIG_PM_SLEEP */
  1678. #endif /* !CONFIG_PM */
  1679. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1680. static const struct of_device_id cm_vpu_match[] = {
  1681. {
  1682. .compatible = "c&m,cm511-vpu",
  1683. },
  1684. {
  1685. .compatible = "starfive,vdec",
  1686. },
  1687. {
  1688. /* end of table */
  1689. },
  1690. };
  1691. MODULE_DEVICE_TABLE(of, cm_vpu_match);
  1692. static const struct dev_pm_ops cm_vpu_pm_ops = {
  1693. SET_RUNTIME_PM_OPS(vpu_runtime_suspend,
  1694. vpu_runtime_resume, NULL)
  1695. SET_SYSTEM_SLEEP_PM_OPS(vpu_suspend, vpu_resume)
  1696. };
  1697. static struct platform_driver vpu_driver = {
  1698. .driver = {
  1699. .name = VPU_PLATFORM_DEVICE_NAME,
  1700. .of_match_table = cm_vpu_match,
  1701. .pm = &cm_vpu_pm_ops,
  1702. },
  1703. .probe = vpu_probe,
  1704. .remove = vpu_remove,
  1705. };
  1706. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1707. static int __init vpu_init(void)
  1708. {
  1709. int res;
  1710. #ifdef SUPPORT_MULTI_INST_INTR
  1711. int i;
  1712. #endif
  1713. DPRINTK("[VPUDRV] begin vpu_init\n");
  1714. #ifdef SUPPORT_MULTI_INST_INTR
  1715. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1716. init_waitqueue_head(&s_interrupt_wait_q[i]);
  1717. }
  1718. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1719. #define MAX_INTERRUPT_QUEUE (16*MAX_NUM_INSTANCE)
  1720. res = kfifo_alloc(&s_interrupt_pending_q[i], MAX_INTERRUPT_QUEUE*sizeof(u32), GFP_KERNEL);
  1721. if (res) {
  1722. DPRINTK("[VPUDRV] kfifo_alloc failed 0x%x\n", res);
  1723. }
  1724. }
  1725. #else
  1726. init_waitqueue_head(&s_interrupt_wait_q);
  1727. #endif
  1728. s_common_memory.base = 0;
  1729. s_instance_pool.base = 0;
  1730. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1731. res = platform_driver_register(&vpu_driver);
  1732. #else
  1733. res = vpu_probe(NULL);
  1734. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1735. DPRINTK("[VPUDRV] end vpu_init result=0x%x\n", res);
  1736. return res;
  1737. }
  1738. static void __exit vpu_exit(void)
  1739. {
  1740. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1741. DPRINTK("[VPUDRV] vpu_exit\n");
  1742. platform_driver_unregister(&vpu_driver);
  1743. #else /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1744. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1745. #else
  1746. vpu_clk_disable(s_vpu_clk);
  1747. #endif
  1748. vpu_clk_put(s_vpu_clk);
  1749. if (s_instance_pool.base) {
  1750. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1751. vfree((const void *)s_instance_pool.base);
  1752. #else
  1753. vpu_free_dma_buffer(&s_instance_pool);
  1754. #endif
  1755. s_instance_pool.base = 0;
  1756. }
  1757. if (s_common_memory.base) {
  1758. vpu_free_dma_buffer(&s_common_memory);
  1759. s_common_memory.base = 0;
  1760. }
  1761. #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_USE_PLL_DYNAMIC_FREQ)
  1762. vpu_freq_close();
  1763. #endif
  1764. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1765. if (s_video_memory.base) {
  1766. iounmap((void *)s_video_memory.base);
  1767. s_video_memory.base = 0;
  1768. vmem_exit(&s_vmem);
  1769. }
  1770. #endif
  1771. if (s_vpu_major > 0) {
  1772. device_destroy(s_vpu_class, MKDEV(s_vpu_major, 0));
  1773. class_destroy(s_vpu_class);
  1774. cdev_del(&s_vpu_cdev);
  1775. unregister_chrdev_region(s_vpu_devt, 1);
  1776. s_vpu_major = 0;
  1777. }
  1778. #ifdef VPU_SUPPORT_ISR
  1779. if (s_vpu_irq)
  1780. free_irq(s_vpu_irq, &s_vpu_drv_context);
  1781. #endif
  1782. #ifdef SUPPORT_MULTI_INST_INTR
  1783. {
  1784. int i;
  1785. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1786. kfifo_free(&s_interrupt_pending_q[i]);
  1787. }
  1788. }
  1789. #endif
  1790. if (s_vpu_register.virt_addr) {
  1791. iounmap((void *)s_vpu_register.virt_addr);
  1792. s_vpu_register.virt_addr = 0x00;
  1793. }
  1794. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1795. return;
  1796. }
  1797. MODULE_AUTHOR("A customer using C&M VPU, Inc.");
  1798. MODULE_DESCRIPTION("VPU linux driver");
  1799. MODULE_LICENSE("Dual BSD/GPL");
  1800. module_init(vpu_init);
  1801. module_exit(vpu_exit);
  1802. static int vpu_pmu_enable(struct device *dev)
  1803. {
  1804. pm_runtime_set_active(dev);
  1805. pm_runtime_enable(dev);
  1806. return 0;
  1807. }
  1808. static void vpu_pmu_disable(struct device *dev)
  1809. {
  1810. pm_runtime_disable(dev);
  1811. pm_runtime_set_suspended(dev);
  1812. }
  1813. /* clk&reset for starfive jh7110*/
  1814. #ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  1815. #define CLK_ENABLE_DATA 1
  1816. #define CLK_DISABLE_DATA 0
  1817. #define CLK_EN_SHIFT 31
  1818. #define CLK_EN_MASK 0x80000000U
  1819. #define SAIF_BD_APBS_BASE 0x13020000
  1820. #define WAVE511_CLK_AXI_CTRL 0x118U
  1821. #define WAVE511_CLK_BPU_CTRL 0x11cU
  1822. #define WAVE511_CLK_VCE_CTRL 0x120U
  1823. #define WAVE511_CLK_APB_CTRL 0x124U
  1824. #define WAVE511_CLK_NOCBUS_CTRL 0x130U
  1825. #define RSTGEN_SOFTWARE_RESET_ASSERT1 0x2FCU
  1826. #define RSTGEN_SOFTWARE_RESET_STATUS1 0x30CU
  1827. #define RSTN_AXI_MASK (0x1 << 15)
  1828. #define RSTN_BPU_MASK (0x1 << 16)
  1829. #define RSTN_VCE_MASK (0x1 << 17)
  1830. #define RSTN_APB_MASK (0x1 << 18)
  1831. #define RSTN_128B_AXIMEM_MASK (0x1 << 21)
  1832. static uint32_t saif_get_reg(const volatile void __iomem *addr,
  1833. uint32_t shift, uint32_t mask)
  1834. {
  1835. u32 tmp;
  1836. tmp = readl(addr);
  1837. tmp = (tmp & mask) >> shift;
  1838. return tmp;
  1839. }
  1840. static void saif_set_reg(volatile void __iomem *addr, uint32_t data,
  1841. uint32_t shift, uint32_t mask)
  1842. {
  1843. uint32_t tmp;
  1844. tmp = readl(addr);
  1845. tmp &= ~mask;
  1846. tmp |= (data << shift) & mask;
  1847. writel(tmp, addr);
  1848. }
  1849. static void saif_assert_rst(volatile void __iomem *addr,
  1850. const volatile void __iomem *addr_status, uint32_t mask)
  1851. {
  1852. uint32_t tmp;
  1853. tmp = readl(addr);
  1854. tmp |= mask;
  1855. writel(tmp, addr);
  1856. do {
  1857. tmp = readl(addr_status);
  1858. } while ((tmp & mask) != 0);
  1859. }
  1860. static void saif_clear_rst(volatile void __iomem *addr,
  1861. const volatile void __iomem *addr_status, uint32_t mask)
  1862. {
  1863. uint32_t tmp;
  1864. tmp = readl(addr);
  1865. tmp &= ~mask;
  1866. writel(tmp, addr);
  1867. do {
  1868. tmp = readl(addr_status);
  1869. } while ((tmp & mask) != mask);
  1870. }
  1871. static void vpu_noc_vdec_bus_control(vpu_clk_t *clk, bool enable)
  1872. {
  1873. if (enable)
  1874. saif_set_reg(clk->noc_bus, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1875. else
  1876. saif_set_reg(clk->noc_bus, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1877. }
  1878. static void vpu_clk_control(vpu_clk_t *clk, bool enable)
  1879. {
  1880. if (enable) {
  1881. /*enable*/
  1882. saif_set_reg(clk->apb_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1883. saif_set_reg(clk->axi_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1884. saif_set_reg(clk->bpu_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1885. saif_set_reg(clk->vce_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1886. /*clr-reset*/
  1887. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1888. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1889. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1890. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1891. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->aximem_128b.rst_mask);
  1892. } else {
  1893. /*assert-reset*/
  1894. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1895. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1896. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1897. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1898. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->aximem_128b.rst_mask);
  1899. /*disable*/
  1900. saif_set_reg(clk->apb_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1901. saif_set_reg(clk->axi_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1902. saif_set_reg(clk->bpu_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1903. saif_set_reg(clk->vce_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1904. }
  1905. }
  1906. static void vpu_clk_reset(vpu_clk_t *clk)
  1907. {
  1908. /*assert-reset*/
  1909. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1910. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1911. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1912. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1913. /*clr-reset*/
  1914. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1915. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1916. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1917. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1918. }
  1919. int vpu_hw_reset(void)
  1920. {
  1921. if (!s_vpu_clk)
  1922. return -1;
  1923. vpu_clk_reset(s_vpu_clk);
  1924. DPRINTK("[VPUDRV] reset vpu hardware. \n");
  1925. return 0;
  1926. }
  1927. static int vpu_of_clk_get(struct platform_device *pdev, vpu_clk_t *vpu_clk)
  1928. {
  1929. if (!pdev)
  1930. return -ENXIO;
  1931. vpu_clk->clkgen = ioremap(SAIF_BD_APBS_BASE, 0x400);
  1932. if (IS_ERR(vpu_clk->clkgen)) {
  1933. dev_err(&pdev->dev, "ioremap clkgen failed.\n");
  1934. return PTR_ERR(vpu_clk->clkgen);
  1935. }
  1936. /* clkgen define */
  1937. vpu_clk->axi_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_AXI_CTRL;
  1938. vpu_clk->bpu_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_BPU_CTRL;
  1939. vpu_clk->vce_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_VCE_CTRL;
  1940. vpu_clk->apb_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_APB_CTRL;
  1941. vpu_clk->noc_bus = vpu_clk->clkgen + WAVE511_CLK_NOCBUS_CTRL;
  1942. vpu_clk->en_mask = CLK_EN_MASK;
  1943. vpu_clk->en_shift = CLK_EN_SHIFT;
  1944. /* rstgen define */
  1945. vpu_clk->rst_ctrl = vpu_clk->clkgen + RSTGEN_SOFTWARE_RESET_ASSERT1;
  1946. vpu_clk->rst_status = vpu_clk->clkgen + RSTGEN_SOFTWARE_RESET_STATUS1;
  1947. vpu_clk->axi_clk.rst_mask = RSTN_AXI_MASK;
  1948. vpu_clk->bpu_clk.rst_mask = RSTN_BPU_MASK;
  1949. vpu_clk->vce_clk.rst_mask = RSTN_VCE_MASK;
  1950. vpu_clk->apb_clk.rst_mask = RSTN_APB_MASK;
  1951. vpu_clk->aximem_128b.rst_mask = RSTN_128B_AXIMEM_MASK;
  1952. if (device_property_read_bool(&pdev->dev, "starfive,vdec_noc_ctrl"))
  1953. vpu_clk->noc_ctrl = true;
  1954. return 0;
  1955. }
  1956. static vpu_clk_t *vpu_clk_get(struct platform_device *pdev)
  1957. {
  1958. vpu_clk_t *vpu_clk;
  1959. vpu_clk = devm_kzalloc(&pdev->dev, sizeof(*vpu_clk), GFP_KERNEL);
  1960. if (!vpu_clk)
  1961. return NULL;
  1962. if (vpu_of_clk_get(pdev, vpu_clk))
  1963. goto err_get_clk;
  1964. return vpu_clk;
  1965. err_get_clk:
  1966. devm_kfree(&pdev->dev, vpu_clk);
  1967. return NULL;
  1968. }
  1969. static void vpu_clk_put(vpu_clk_t *clk)
  1970. {
  1971. if (clk->clkgen) {
  1972. iounmap(clk->clkgen);
  1973. clk->clkgen = NULL;
  1974. }
  1975. }
  1976. static int vpu_clk_enable(vpu_clk_t *clk)
  1977. {
  1978. if (clk == NULL || IS_ERR(clk))
  1979. return -1;
  1980. vpu_pmu_enable(clk->dev);
  1981. vpu_clk_control(clk, true);
  1982. if (clk->noc_ctrl == true)
  1983. vpu_noc_vdec_bus_control(clk, true);
  1984. DPRINTK("[VPUDRV] vpu_clk_enable\n");
  1985. return 0;
  1986. }
  1987. static void vpu_clk_disable(vpu_clk_t *clk)
  1988. {
  1989. if (clk == NULL || IS_ERR(clk))
  1990. return;
  1991. vpu_clk_control(clk, false);
  1992. vpu_pmu_disable(clk->dev);
  1993. if (clk->noc_ctrl == true)
  1994. vpu_noc_vdec_bus_control(clk, false);
  1995. DPRINTK("[VPUDRV] vpu_clk_disable\n");
  1996. }
  1997. #else /*STARFIVE_VPU_SUPPORT_CLOCK_CONTROL*/
  1998. int vpu_hw_reset(void)
  1999. {
  2000. DPRINTK("[VPUDRV] reset vpu hardware. \n");
  2001. /* sram do not need reset */
  2002. return reset_control_reset(s_vpu_clk->resets);
  2003. }
  2004. static int vpu_of_clk_get(struct platform_device *pdev, vpu_clk_t *vpu_clk)
  2005. {
  2006. struct device *dev = &pdev->dev;
  2007. int ret;
  2008. vpu_clk->dev = dev;
  2009. vpu_clk->clks = vpu_clks;
  2010. vpu_clk->nr_clks = ARRAY_SIZE(vpu_clks);
  2011. vpu_clk->resets = devm_reset_control_array_get_shared(dev);
  2012. if (IS_ERR(vpu_clk->resets)) {
  2013. ret = PTR_ERR(vpu_clk->resets);
  2014. dev_err(dev, "faied to get vpu reset controls\n");
  2015. }
  2016. ret = devm_clk_bulk_get(dev, vpu_clk->nr_clks, vpu_clk->clks);
  2017. if (ret)
  2018. dev_err(dev, "faied to get vpu clk controls\n");
  2019. if (device_property_read_bool(dev, "starfive,vdec_noc_ctrl"))
  2020. vpu_clk->noc_ctrl = true;
  2021. return 0;
  2022. }
  2023. static vpu_clk_t *vpu_clk_get(struct platform_device *pdev)
  2024. {
  2025. vpu_clk_t *vpu_clk;
  2026. if (!pdev)
  2027. return NULL;
  2028. vpu_clk = devm_kzalloc(&pdev->dev, sizeof(*vpu_clk), GFP_KERNEL);
  2029. if (!vpu_clk)
  2030. return NULL;
  2031. if (vpu_of_clk_get(pdev, vpu_clk))
  2032. goto err_of_clk_get;
  2033. return vpu_clk;
  2034. err_of_clk_get:
  2035. devm_kfree(&pdev->dev, vpu_clk);
  2036. return NULL;
  2037. }
  2038. static void vpu_clk_put(vpu_clk_t *clk)
  2039. {
  2040. clk_bulk_put(clk->nr_clks, clk->clks);
  2041. }
  2042. static int vpu_clk_enable(vpu_clk_t *clk)
  2043. {
  2044. int ret;
  2045. ret = clk_bulk_prepare_enable(clk->nr_clks, clk->clks);
  2046. if (ret)
  2047. dev_err(clk->dev, "enable clk error.\n");
  2048. DPRINTK("[VPUDRV] vpu_clk_enable\n");
  2049. return ret;
  2050. }
  2051. static void vpu_clk_disable(vpu_clk_t *clk)
  2052. {
  2053. clk_bulk_disable_unprepare(clk->nr_clks, clk->clks);
  2054. }
  2055. #endif