venc.c 57 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. //--=========================================================================--
  3. // This file is linux device driver for VPU.
  4. //-----------------------------------------------------------------------------
  5. //
  6. // This confidential and proprietary software may be used only
  7. // as authorized by a licensing agreement from Chips&Media Inc.
  8. // In the event of publication, the following notice is applicable:
  9. //
  10. // (C) COPYRIGHT 2006 - 2015 CHIPS&MEDIA INC.
  11. // ALL RIGHTS RESERVED
  12. //
  13. // The entire notice above must be reproduced on all authorized
  14. // copies.
  15. //
  16. //--=========================================================================-
  17. #include <linux/kernel.h>
  18. #include <linux/mm.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/ioport.h>
  21. #include <linux/module.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/wait.h>
  25. #include <linux/list.h>
  26. #include <linux/clk.h>
  27. #include <linux/delay.h>
  28. #include <linux/uaccess.h>
  29. #include <linux/cdev.h>
  30. #include <linux/slab.h>
  31. #include <linux/sched.h>
  32. #include <linux/reset.h>
  33. #include <linux/version.h>
  34. #include <linux/of.h>
  35. #include <linux/pm_runtime.h>
  36. #include "../../../vpuapi/vpuconfig.h"
  37. #include "vpu.h"
  38. extern void sifive_ccache_flush_range(phys_addr_t start, size_t len);
  39. extern void sifive_ccache_flush_entire(void);
  40. #ifndef CONFIG_PM
  41. #define CONFIG_PM
  42. #endif
  43. //#define ENABLE_DEBUG_MSG
  44. #ifdef ENABLE_DEBUG_MSG
  45. #define DPRINTK(args...) printk(KERN_INFO args);
  46. #else
  47. #define DPRINTK(args...)
  48. #endif
  49. /* definitions to be changed as customer configuration */
  50. /* if you want to have clock gating scheme frame by frame */
  51. //#define VPU_SUPPORT_CLOCK_CONTROL
  52. /* if clktree is work,try this...*/
  53. #define STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  54. /* if the driver want to use interrupt service from kernel ISR */
  55. #define VPU_SUPPORT_ISR
  56. /* if the platform driver knows the name of this driver */
  57. /* VPU_PLATFORM_DEVICE_NAME */
  58. #define VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  59. /* if this driver knows the dedicated video memory address */
  60. //#define VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  61. #define VPU_PLATFORM_DEVICE_NAME "venc"
  62. #define VPU_CLK_NAME "vcoenc"
  63. #define VPU_DEV_NAME "venc"
  64. /* if the platform driver knows this driver */
  65. /* the definition of VPU_REG_BASE_ADDR and VPU_REG_SIZE are not meaningful */
  66. //#define VPU_REG_BASE_ADDR 0x75000000
  67. #define VPU_REG_BASE_ADDR 0x130B0000
  68. #define VPU_REG_SIZE (0x4000*MAX_NUM_VPU_CORE)
  69. #ifdef VPU_SUPPORT_ISR
  70. #define VPU_IRQ_NUM (15)
  71. #endif
  72. /* this definition is only for chipsnmedia FPGA board env */
  73. /* so for SOC env of customers can be ignored */
  74. #ifndef VM_RESERVED /*for kernel up to 3.7.0 version*/
  75. # define VM_RESERVED (VM_DONTEXPAND | VM_DONTDUMP)
  76. #endif
  77. #ifdef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  78. typedef struct vpu_clkgen_t {
  79. void __iomem *en_ctrl;
  80. uint32_t rst_mask;
  81. } vpu_clkgen_t;
  82. struct clk_bulk_data vpu_clks[] = {
  83. { .id = "apb_clk" },
  84. { .id = "axi_clk" },
  85. { .id = "bpu_clk" },
  86. { .id = "vce_clk" },
  87. { .id = "noc_bus" },
  88. };
  89. #define FRAMSIZE_1080P (1920*1080)
  90. #define FRAMSIZE_720P (1280*720)
  91. #define FRAMSIZE_480P (720*480)
  92. struct vpu_devfreq_t {
  93. struct clk *axi_clk;
  94. struct clk *bpu_clk;
  95. struct clk *vce_clk;
  96. };
  97. enum VPU_DEV_FREQ {
  98. VPU_DEV_FREQ_80 = 80000000,
  99. VPU_DEV_FREQ_100 = 100000000,
  100. VPU_DEV_FREQ_150 = 150000000,
  101. VPU_DEV_FREQ_200 = 200000000,
  102. VPU_DEV_FREQ_237 = 237600000,
  103. VPU_DEV_FREQ_300 = 300000000,
  104. VPU_DEV_FREQ_MAX = VPU_DEV_FREQ_300,
  105. };
  106. enum VPU_DEV_FREQ_MODE {
  107. MODE_480P_30F,
  108. MODE_480P_60F,
  109. MODE_720P_30F,
  110. MODE_720P_60F,
  111. MODE_1080P_30F,
  112. MODE_MAX,
  113. };
  114. struct vpu_dev_freq_list {
  115. int mode;
  116. unsigned long axi_rate;
  117. unsigned long bpu_rate;
  118. unsigned long vce_rate;
  119. };
  120. typedef struct vpu_clk_t{
  121. #ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  122. void __iomem *clkgen;
  123. void __iomem *rst_ctrl;
  124. void __iomem *rst_status;
  125. void __iomem *noc_bus;
  126. uint32_t en_shift;
  127. uint32_t en_mask;
  128. vpu_clkgen_t apb_clk;
  129. vpu_clkgen_t axi_clk;
  130. vpu_clkgen_t bpu_clk;
  131. vpu_clkgen_t vce_clk;
  132. vpu_clkgen_t aximem_128b;
  133. #else
  134. struct clk_bulk_data *clks;
  135. struct reset_control *resets;
  136. struct vpu_devfreq_t vpu_devfreq;
  137. int nr_clks;
  138. #endif
  139. struct device *dev;
  140. bool noc_ctrl;
  141. }vpu_clk_t;
  142. #endif /*STARFIVE_VPU_SUPPORT_CLOCK_CONTROL*/
  143. struct device *vpu_dev;
  144. typedef struct vpu_drv_context_t {
  145. struct fasync_struct *async_queue;
  146. unsigned long interrupt_reason;
  147. u32 open_count; /*!<< device reference count. Not instance count */
  148. } vpu_drv_context_t;
  149. /* To track the allocated memory buffer */
  150. typedef struct vpudrv_buffer_pool_t {
  151. struct list_head list;
  152. struct vpudrv_buffer_t vb;
  153. struct file *filp;
  154. } vpudrv_buffer_pool_t;
  155. /* To track the instance index and buffer in instance pool */
  156. typedef struct vpudrv_instanace_list_t {
  157. struct list_head list;
  158. unsigned long inst_idx;
  159. unsigned long core_idx;
  160. struct file *filp;
  161. } vpudrv_instanace_list_t;
  162. typedef struct vpudrv_instance_pool_t {
  163. unsigned char codecInstPool[MAX_NUM_INSTANCE][MAX_INST_HANDLE_SIZE];
  164. } vpudrv_instance_pool_t;
  165. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  166. # define VPU_INIT_VIDEO_MEMORY_SIZE_IN_BYTE (62*1024*1024)
  167. # define VPU_DRAM_PHYSICAL_BASE 0x86C00000
  168. #include "vmm.h"
  169. static video_mm_t s_vmem;
  170. static vpudrv_buffer_t s_video_memory = {0};
  171. #endif /*VPU_SUPPORT_RESERVED_VIDEO_MEMORY*/
  172. static int vpu_hw_reset(void);
  173. static void vpu_clk_disable(vpu_clk_t *clk);
  174. static int vpu_clk_enable(vpu_clk_t *clk);
  175. static vpu_clk_t *vpu_clk_get(struct platform_device *pdev);
  176. static void vpu_clk_put(vpu_clk_t *clk);
  177. static int vpu_pmu_enable(struct device *dev);
  178. static void vpu_pmu_disable(struct device *dev);
  179. static int vpu_devfreq_select(struct vpudrv_devfreq_info_t *info);
  180. /* end customer definition */
  181. static vpudrv_buffer_t s_instance_pool = {0};
  182. static vpudrv_buffer_t s_common_memory = {0};
  183. static vpu_drv_context_t s_vpu_drv_context;
  184. static dev_t s_vpu_devt;
  185. static int s_vpu_major;
  186. static struct cdev s_vpu_cdev;
  187. static struct class *s_vpu_class;
  188. static struct vpu_clk_t *s_vpu_clk;
  189. static int s_vpu_open_ref_count;
  190. #ifdef VPU_SUPPORT_ISR
  191. static int s_vpu_irq = VPU_IRQ_NUM;
  192. #endif
  193. static vpudrv_buffer_t s_vpu_register = {0};
  194. static int s_interrupt_flag;
  195. static wait_queue_head_t s_interrupt_wait_q;
  196. static spinlock_t s_vpu_lock = __SPIN_LOCK_UNLOCKED(s_vpu_lock);
  197. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
  198. static DECLARE_MUTEX(s_vpu_sem);
  199. #else
  200. static DEFINE_SEMAPHORE(s_vpu_sem);
  201. #endif
  202. static struct list_head s_vbp_head = LIST_HEAD_INIT(s_vbp_head);
  203. static struct list_head s_inst_list_head = LIST_HEAD_INIT(s_inst_list_head);
  204. static vpu_bit_firmware_info_t s_bit_firmware_info[MAX_NUM_VPU_CORE];
  205. #ifdef CONFIG_PM
  206. /* implement to power management functions */
  207. #define BIT_BASE 0x0000
  208. #define BIT_CODE_RUN (BIT_BASE + 0x000)
  209. #define BIT_CODE_DOWN (BIT_BASE + 0x004)
  210. #define BIT_INT_CLEAR (BIT_BASE + 0x00C)
  211. #define BIT_INT_STS (BIT_BASE + 0x010)
  212. #define BIT_CODE_RESET (BIT_BASE + 0x014)
  213. #define BIT_INT_REASON (BIT_BASE + 0x174)
  214. #define BIT_BUSY_FLAG (BIT_BASE + 0x160)
  215. #define BIT_RUN_COMMAND (BIT_BASE + 0x164)
  216. #define BIT_RUN_INDEX (BIT_BASE + 0x168)
  217. #define BIT_RUN_COD_STD (BIT_BASE + 0x16C)
  218. /* WAVE4 registers */
  219. #define W4_REG_BASE 0x0000
  220. #define W4_VPU_BUSY_STATUS (W4_REG_BASE + 0x0070)
  221. #define W4_VPU_INT_REASON_CLEAR (W4_REG_BASE + 0x0034)
  222. #define W4_VPU_VINT_CLEAR (W4_REG_BASE + 0x003C)
  223. #define W4_VPU_VPU_INT_STS (W4_REG_BASE + 0x0044)
  224. #define W4_VPU_INT_REASON (W4_REG_BASE + 0x004c)
  225. #define W4_RET_SUCCESS (W4_REG_BASE + 0x0110)
  226. #define W4_RET_FAIL_REASON (W4_REG_BASE + 0x0114)
  227. /* WAVE4 INIT, WAKEUP */
  228. #define W4_PO_CONF (W4_REG_BASE + 0x0000)
  229. #define W4_VCPU_CUR_PC (W4_REG_BASE + 0x0004)
  230. #define W4_VPU_VINT_ENABLE (W4_REG_BASE + 0x0048)
  231. #define W4_VPU_RESET_REQ (W4_REG_BASE + 0x0050)
  232. #define W4_VPU_RESET_STATUS (W4_REG_BASE + 0x0054)
  233. #define W4_VPU_REMAP_CTRL (W4_REG_BASE + 0x0060)
  234. #define W4_VPU_REMAP_VADDR (W4_REG_BASE + 0x0064)
  235. #define W4_VPU_REMAP_PADDR (W4_REG_BASE + 0x0068)
  236. #define W4_VPU_REMAP_CORE_START (W4_REG_BASE + 0x006C)
  237. #define W4_VPU_BUSY_STATUS (W4_REG_BASE + 0x0070)
  238. #define W4_REMAP_CODE_INDEX 0
  239. enum {
  240. W4_INT_INIT_VPU = 0,
  241. W4_INT_DEC_PIC_HDR = 1,
  242. W4_INT_FINI_SEQ = 2,
  243. W4_INT_DEC_PIC = 3,
  244. W4_INT_SET_FRAMEBUF = 4,
  245. W4_INT_FLUSH_DEC = 5,
  246. W4_INT_GET_FW_VERSION = 9,
  247. W4_INT_QUERY_DEC = 10,
  248. W4_INT_SLEEP_VPU = 11,
  249. W4_INT_WAKEUP_VPU = 12,
  250. W4_INT_CHANGE_INT = 13,
  251. W4_INT_CREATE_INSTANCE = 14,
  252. W4_INT_BSBUF_EMPTY = 15, /*!<< Bitstream buffer empty */
  253. W4_INT_ENC_SLICE_INT = 15,
  254. };
  255. enum {
  256. W5_INT_INIT_VPU = 0,
  257. W5_INT_WAKEUP_VPU = 1,
  258. W5_INT_SLEEP_VPU = 2,
  259. W5_INT_CREATE_INSTANCE = 3,
  260. W5_INT_FLUSH_INSTANCE = 4,
  261. W5_INT_DESTORY_INSTANCE = 5,
  262. W5_INT_INIT_SEQ = 6,
  263. W5_INT_SET_FRAMEBUF = 7,
  264. W5_INT_DEC_PIC = 8,
  265. W5_INT_ENC_PIC = 8,
  266. W5_INT_ENC_SET_PARAM = 9,
  267. W5_INT_DEC_QUERY = 14,
  268. W5_INT_BSBUF_EMPTY = 15,
  269. };
  270. #define W4_HW_OPTION (W4_REG_BASE + 0x0124)
  271. #define W4_CODE_SIZE (W4_REG_BASE + 0x011C)
  272. /* Note: W4_INIT_CODE_BASE_ADDR should be aligned to 4KB */
  273. #define W4_ADDR_CODE_BASE (W4_REG_BASE + 0x0118)
  274. #define W4_CODE_PARAM (W4_REG_BASE + 0x0120)
  275. #define W4_INIT_VPU_TIME_OUT_CNT (W4_REG_BASE + 0x0134)
  276. /* WAVE5 registers */
  277. #define W5_ADDR_CODE_BASE (W4_REG_BASE + 0x0110)
  278. #define W5_CODE_SIZE (W4_REG_BASE + 0x0114)
  279. #define W5_CODE_PARAM (W4_REG_BASE + 0x0128)
  280. #define W5_INIT_VPU_TIME_OUT_CNT (W4_REG_BASE + 0x0130)
  281. #define W5_HW_OPTION (W4_REG_BASE + 0x012C)
  282. #define W5_RET_SUCCESS (W4_REG_BASE + 0x0108)
  283. /* WAVE4 Wave4BitIssueCommand */
  284. #define W4_CORE_INDEX (W4_REG_BASE + 0x0104)
  285. #define W4_INST_INDEX (W4_REG_BASE + 0x0108)
  286. #define W4_COMMAND (W4_REG_BASE + 0x0100)
  287. #define W4_VPU_HOST_INT_REQ (W4_REG_BASE + 0x0038)
  288. /* Product register */
  289. #define VPU_PRODUCT_CODE_REGISTER (BIT_BASE + 0x1044)
  290. static u32 s_vpu_reg_store[MAX_NUM_VPU_CORE][64];
  291. #endif
  292. #define ReadVpuRegister(addr) *(volatile unsigned int *)(s_vpu_register.virt_addr + s_bit_firmware_info[core].reg_base_offset + addr)
  293. #define WriteVpuRegister(addr, val) *(volatile unsigned int *)(s_vpu_register.virt_addr + s_bit_firmware_info[core].reg_base_offset + addr) = (unsigned int)val
  294. #define WriteVpu(addr, val) *(volatile unsigned int *)(addr) = (unsigned int)val;
  295. static void starfive_flush_dcache(phys_addr_t start, size_t len)
  296. {
  297. #ifdef ARCH_HAS_SYNC_DMA_FOR_DEVICE
  298. dma_sync_single_for_device(vpu_dev, start, len, DMA_FROM_DEVICE);
  299. #else
  300. if (len >= 0x80000)
  301. sifive_ccache_flush_entire();
  302. else
  303. sifive_ccache_flush_range(start, len);
  304. #endif
  305. }
  306. static int vpu_alloc_dma_buffer(vpudrv_buffer_t *vb)
  307. {
  308. if (!vb)
  309. return -1;
  310. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  311. vb->phys_addr = (unsigned long)vmem_alloc(&s_vmem, vb->size, 0);
  312. if ((unsigned long)vb->phys_addr == (unsigned long)-1) {
  313. printk(KERN_ERR "[VPUDRV] Physical memory allocation error size=%d\n", vb->size);
  314. return -1;
  315. }
  316. vb->base = (unsigned long)(s_video_memory.base + (vb->phys_addr - s_video_memory.phys_addr));
  317. #else
  318. vb->base = (unsigned long)dma_alloc_coherent(vpu_dev, PAGE_ALIGN(vb->size), (dma_addr_t *) (&vb->phys_addr), GFP_DMA | GFP_KERNEL);
  319. if ((void *)(vb->base) == NULL) {
  320. printk(KERN_ERR "[VPUDRV] Physical memory allocation error size=%d\n", vb->size);
  321. return -1;
  322. }
  323. starfive_flush_dcache(vb->phys_addr,PAGE_ALIGN(vb->size));
  324. #endif
  325. return 0;
  326. }
  327. static void vpu_free_dma_buffer(vpudrv_buffer_t *vb)
  328. {
  329. if (!vb)
  330. return;
  331. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  332. if (vb->base)
  333. vmem_free(&s_vmem, vb->phys_addr, 0);
  334. #else
  335. if (vb->base)
  336. dma_free_coherent(vpu_dev, PAGE_ALIGN(vb->size), (void *)vb->base, vb->phys_addr);
  337. #endif
  338. }
  339. static int vpu_free_instances(struct file *filp)
  340. {
  341. vpudrv_instanace_list_t *vil, *n;
  342. vpudrv_instance_pool_t *vip;
  343. void *vip_base;
  344. int instance_pool_size_per_core;
  345. #if !defined(PTHREAD_MUTEX_ROBUST_NP)
  346. void *vdi_mutexes_base;
  347. const int PTHREAD_MUTEX_T_DESTROY_VALUE = 0xdead10cc;
  348. #endif
  349. DPRINTK("[VPUDRV] vpu_free_instances\n");
  350. instance_pool_size_per_core = (s_instance_pool.size/MAX_NUM_VPU_CORE); /* s_instance_pool.size assigned to the size of all core once call VDI_IOCTL_GET_INSTANCE_POOL by user. */
  351. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  352. {
  353. if (vil->filp == filp) {
  354. vip_base = (void *)(s_instance_pool.base + (instance_pool_size_per_core*vil->core_idx));
  355. DPRINTK("[VPUDRV] vpu_free_instances detect instance crash instIdx=%d, coreIdx=%d, vip_base=%p, instance_pool_size_per_core=%d\n", (int)vil->inst_idx, (int)vil->core_idx, vip_base, (int)instance_pool_size_per_core);
  356. vip = (vpudrv_instance_pool_t *)vip_base;
  357. if (vip) {
  358. memset(&vip->codecInstPool[vil->inst_idx], 0x00, 4); /* only first 4 byte is key point(inUse of CodecInst in vpuapi) to free the corresponding instance. */
  359. #if !defined(PTHREAD_MUTEX_ROBUST_NP)
  360. #define PTHREAD_MUTEX_T_HANDLE_SIZE 4
  361. vdi_mutexes_base = (vip_base + (instance_pool_size_per_core - PTHREAD_MUTEX_T_HANDLE_SIZE*4));
  362. DPRINTK("[VPUDRV] vpu_free_instances : force to destroy vdi_mutexes_base=%p in userspace \n", vdi_mutexes_base);
  363. if (vdi_mutexes_base) {
  364. int i;
  365. for (i = 0; i < 4; i++) {
  366. memcpy(vdi_mutexes_base, &PTHREAD_MUTEX_T_DESTROY_VALUE, PTHREAD_MUTEX_T_HANDLE_SIZE);
  367. vdi_mutexes_base += PTHREAD_MUTEX_T_HANDLE_SIZE;
  368. }
  369. }
  370. #endif
  371. }
  372. s_vpu_open_ref_count--;
  373. list_del(&vil->list);
  374. kfree(vil);
  375. }
  376. }
  377. return 1;
  378. }
  379. static int vpu_free_buffers(struct file *filp)
  380. {
  381. vpudrv_buffer_pool_t *pool, *n;
  382. vpudrv_buffer_t vb;
  383. DPRINTK("[VPUDRV] vpu_free_buffers\n");
  384. list_for_each_entry_safe(pool, n, &s_vbp_head, list)
  385. {
  386. if (pool->filp == filp) {
  387. vb = pool->vb;
  388. if (vb.base) {
  389. vpu_free_dma_buffer(&vb);
  390. list_del(&pool->list);
  391. kfree(pool);
  392. }
  393. }
  394. }
  395. return 0;
  396. }
  397. static irqreturn_t vpu_irq_handler(int irq, void *dev_id)
  398. {
  399. vpu_drv_context_t *dev = (vpu_drv_context_t *)dev_id;
  400. /* this can be removed. it also work in VPU_WaitInterrupt of API function */
  401. int core;
  402. int product_code;
  403. DPRINTK("[VPUDRV][+]%s\n", __func__);
  404. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  405. if (s_bit_firmware_info[core].size == 0) {/* it means that we didn't get an information the current core from API layer. No core activated.*/
  406. printk(KERN_ERR "[VPUDRV] : s_bit_firmware_info[core].size is zero\n");
  407. continue;
  408. }
  409. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  410. if (PRODUCT_CODE_W_SERIES(product_code)) {
  411. if (ReadVpuRegister(W4_VPU_VPU_INT_STS)) {
  412. dev->interrupt_reason = ReadVpuRegister(W4_VPU_INT_REASON);
  413. WriteVpuRegister(W4_VPU_INT_REASON_CLEAR, dev->interrupt_reason);
  414. WriteVpuRegister(W4_VPU_VINT_CLEAR, 0x1);
  415. }
  416. }
  417. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  418. if (ReadVpuRegister(BIT_INT_STS)) {
  419. dev->interrupt_reason = ReadVpuRegister(BIT_INT_REASON);
  420. WriteVpuRegister(BIT_INT_CLEAR, 0x1);
  421. }
  422. }
  423. else {
  424. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  425. continue;
  426. }
  427. DPRINTK("[VPUDRV] product: 0x%08x intr_reason: 0x%08lx\n", product_code, dev->interrupt_reason);
  428. }
  429. if (dev->async_queue)
  430. kill_fasync(&dev->async_queue, SIGIO, POLL_IN); /* notify the interrupt to user space */
  431. s_interrupt_flag = 1;
  432. wake_up_interruptible(&s_interrupt_wait_q);
  433. DPRINTK("[VPUDRV][-]%s\n", __func__);
  434. return IRQ_HANDLED;
  435. }
  436. static int vpu_open(struct inode *inode, struct file *filp)
  437. {
  438. DPRINTK("[VPUDRV][+] %s\n", __func__);
  439. pm_runtime_get_sync(s_vpu_clk->dev);
  440. vpu_hw_reset();
  441. spin_lock(&s_vpu_lock);
  442. s_vpu_drv_context.open_count++;
  443. filp->private_data = (void *)(&s_vpu_drv_context);
  444. spin_unlock(&s_vpu_lock);
  445. DPRINTK("[VPUDRV][-] %s\n", __func__);
  446. return 0;
  447. }
  448. /*static int vpu_ioctl(struct inode *inode, struct file *filp, u_int cmd, u_long arg) // for kernel 2.6.9 of C&M*/
  449. static long vpu_ioctl(struct file *filp, u_int cmd, u_long arg)
  450. {
  451. int ret = 0;
  452. struct vpu_drv_context_t *dev = (struct vpu_drv_context_t *)filp->private_data;
  453. switch (cmd) {
  454. case VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY:
  455. {
  456. vpudrv_buffer_pool_t *vbp;
  457. DPRINTK("[VPUDRV][+]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  458. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  459. vbp = kzalloc(sizeof(*vbp), GFP_KERNEL);
  460. if (!vbp) {
  461. up(&s_vpu_sem);
  462. return -ENOMEM;
  463. }
  464. ret = copy_from_user(&(vbp->vb), (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  465. if (ret) {
  466. kfree(vbp);
  467. up(&s_vpu_sem);
  468. return -EFAULT;
  469. }
  470. ret = vpu_alloc_dma_buffer(&(vbp->vb));
  471. if (ret == -1) {
  472. ret = -ENOMEM;
  473. kfree(vbp);
  474. up(&s_vpu_sem);
  475. break;
  476. }
  477. ret = copy_to_user((void __user *)arg, &(vbp->vb), sizeof(vpudrv_buffer_t));
  478. if (ret) {
  479. kfree(vbp);
  480. ret = -EFAULT;
  481. up(&s_vpu_sem);
  482. break;
  483. }
  484. vbp->filp = filp;
  485. spin_lock(&s_vpu_lock);
  486. list_add(&vbp->list, &s_vbp_head);
  487. spin_unlock(&s_vpu_lock);
  488. up(&s_vpu_sem);
  489. }
  490. DPRINTK("[VPUDRV][-]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  491. }
  492. break;
  493. case VDI_IOCTL_FREE_PHYSICALMEMORY:
  494. {
  495. vpudrv_buffer_pool_t *vbp, *n;
  496. vpudrv_buffer_t vb;
  497. DPRINTK("[VPUDRV][+]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  498. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  499. ret = copy_from_user(&vb, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  500. if (ret) {
  501. up(&s_vpu_sem);
  502. return -EACCES;
  503. }
  504. if (vb.base)
  505. vpu_free_dma_buffer(&vb);
  506. spin_lock(&s_vpu_lock);
  507. list_for_each_entry_safe(vbp, n, &s_vbp_head, list)
  508. {
  509. if (vbp->vb.base == vb.base) {
  510. list_del(&vbp->list);
  511. kfree(vbp);
  512. break;
  513. }
  514. }
  515. spin_unlock(&s_vpu_lock);
  516. up(&s_vpu_sem);
  517. }
  518. DPRINTK("[VPUDRV][-]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  519. }
  520. break;
  521. case VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO:
  522. {
  523. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  524. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO\n");
  525. if (s_video_memory.base != 0) {
  526. ret = copy_to_user((void __user *)arg, &s_video_memory, sizeof(vpudrv_buffer_t));
  527. if (ret != 0)
  528. ret = -EFAULT;
  529. } else {
  530. ret = -EFAULT;
  531. }
  532. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO\n");
  533. #endif
  534. }
  535. break;
  536. case VDI_IOCTL_WAIT_INTERRUPT:
  537. {
  538. vpudrv_intr_info_t info;
  539. DPRINTK("[VPUDRV][+]VDI_IOCTL_WAIT_INTERRUPT\n");
  540. ret = copy_from_user(&info, (vpudrv_intr_info_t *)arg, sizeof(vpudrv_intr_info_t));
  541. if (ret != 0)
  542. return -EFAULT;
  543. ret = wait_event_interruptible_timeout(s_interrupt_wait_q, s_interrupt_flag != 0, msecs_to_jiffies(info.timeout));
  544. if (!ret) {
  545. ret = -ETIME;
  546. break;
  547. }
  548. if (signal_pending(current)) {
  549. ret = -ERESTARTSYS;
  550. break;
  551. }
  552. DPRINTK("[VPUDRV] s_interrupt_flag(%d), reason(0x%08lx)\n", s_interrupt_flag, dev->interrupt_reason);
  553. info.intr_reason = dev->interrupt_reason;
  554. s_interrupt_flag = 0;
  555. dev->interrupt_reason = 0;
  556. ret = copy_to_user((void __user *)arg, &info, sizeof(vpudrv_intr_info_t));
  557. DPRINTK("[VPUDRV][-]VDI_IOCTL_WAIT_INTERRUPT\n");
  558. if (ret != 0)
  559. return -EFAULT;
  560. }
  561. break;
  562. case VDI_IOCTL_SET_CLOCK_GATE:
  563. {
  564. u32 clkgate;
  565. DPRINTK("[VPUDRV][+]VDI_IOCTL_SET_CLOCK_GATE\n");
  566. if (get_user(clkgate, (u32 __user *) arg))
  567. return -EFAULT;
  568. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  569. if (clkgate)
  570. vpu_clk_enable(s_vpu_clk);
  571. else
  572. vpu_clk_disable(s_vpu_clk);
  573. #endif
  574. DPRINTK("[VPUDRV][-]VDI_IOCTL_SET_CLOCK_GATE\n");
  575. }
  576. break;
  577. case VDI_IOCTL_GET_INSTANCE_POOL:
  578. {
  579. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_INSTANCE_POOL\n");
  580. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  581. if (s_instance_pool.base != 0) {
  582. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(vpudrv_buffer_t));
  583. if (ret != 0)
  584. ret = -EFAULT;
  585. } else {
  586. ret = copy_from_user(&s_instance_pool, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  587. if (ret == 0) {
  588. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  589. s_instance_pool.size = PAGE_ALIGN(s_instance_pool.size);
  590. s_instance_pool.base = (unsigned long)vmalloc(s_instance_pool.size);
  591. s_instance_pool.phys_addr = s_instance_pool.base;
  592. if (s_instance_pool.base != 0)
  593. #else
  594. if (vpu_alloc_dma_buffer(&s_instance_pool) != -1)
  595. #endif
  596. {
  597. memset((void *)s_instance_pool.base, 0x0, s_instance_pool.size); /*clearing memory*/
  598. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(vpudrv_buffer_t));
  599. if (ret == 0) {
  600. /* success to get memory for instance pool */
  601. up(&s_vpu_sem);
  602. break;
  603. }
  604. }
  605. }
  606. ret = -EFAULT;
  607. }
  608. up(&s_vpu_sem);
  609. }
  610. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_INSTANCE_POOL\n");
  611. }
  612. break;
  613. case VDI_IOCTL_GET_COMMON_MEMORY:
  614. {
  615. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_COMMON_MEMORY\n");
  616. if (s_common_memory.base != 0) {
  617. ret = copy_to_user((void __user *)arg, &s_common_memory, sizeof(vpudrv_buffer_t));
  618. if (ret != 0)
  619. ret = -EFAULT;
  620. } else {
  621. ret = copy_from_user(&s_common_memory, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  622. if (ret == 0) {
  623. if (vpu_alloc_dma_buffer(&s_common_memory) != -1) {
  624. ret = copy_to_user((void __user *)arg, &s_common_memory, sizeof(vpudrv_buffer_t));
  625. if (ret == 0) {
  626. /* success to get memory for common memory */
  627. break;
  628. }
  629. }
  630. }
  631. ret = -EFAULT;
  632. }
  633. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_COMMON_MEMORY\n");
  634. }
  635. break;
  636. case VDI_IOCTL_OPEN_INSTANCE:
  637. {
  638. vpudrv_inst_info_t inst_info;
  639. vpudrv_instanace_list_t *vil, *n;
  640. vil = kzalloc(sizeof(*vil), GFP_KERNEL);
  641. if (!vil)
  642. return -ENOMEM;
  643. if (copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t)))
  644. return -EFAULT;
  645. vil->inst_idx = inst_info.inst_idx;
  646. vil->core_idx = inst_info.core_idx;
  647. vil->filp = filp;
  648. spin_lock(&s_vpu_lock);
  649. list_add(&vil->list, &s_inst_list_head);
  650. inst_info.inst_open_count = 0; /* counting the current open instance number */
  651. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  652. {
  653. if (vil->core_idx == inst_info.core_idx)
  654. inst_info.inst_open_count++;
  655. }
  656. spin_unlock(&s_vpu_lock);
  657. s_vpu_open_ref_count++; /* flag just for that vpu is in opened or closed */
  658. if (copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t))) {
  659. kfree(vil);
  660. return -EFAULT;
  661. }
  662. DPRINTK("[VPUDRV] VDI_IOCTL_OPEN_INSTANCE core_idx=%d, inst_idx=%d, s_vpu_open_ref_count=%d, inst_open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, s_vpu_open_ref_count, inst_info.inst_open_count);
  663. }
  664. break;
  665. case VDI_IOCTL_CLOSE_INSTANCE:
  666. {
  667. vpudrv_inst_info_t inst_info;
  668. vpudrv_instanace_list_t *vil, *n;
  669. DPRINTK("[VPUDRV][+]VDI_IOCTL_CLOSE_INSTANCE\n");
  670. if (copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t)))
  671. return -EFAULT;
  672. spin_lock(&s_vpu_lock);
  673. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  674. {
  675. if (vil->inst_idx == inst_info.inst_idx && vil->core_idx == inst_info.core_idx) {
  676. list_del(&vil->list);
  677. kfree(vil);
  678. break;
  679. }
  680. }
  681. inst_info.inst_open_count = 0; /* counting the current open instance number */
  682. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  683. {
  684. if (vil->core_idx == inst_info.core_idx)
  685. inst_info.inst_open_count++;
  686. }
  687. spin_unlock(&s_vpu_lock);
  688. s_vpu_open_ref_count--; /* flag just for that vpu is in opened or closed */
  689. if (copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t)))
  690. return -EFAULT;
  691. DPRINTK("[VPUDRV] VDI_IOCTL_CLOSE_INSTANCE core_idx=%d, inst_idx=%d, s_vpu_open_ref_count=%d, inst_open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, s_vpu_open_ref_count, inst_info.inst_open_count);
  692. }
  693. break;
  694. case VDI_IOCTL_GET_INSTANCE_NUM:
  695. {
  696. vpudrv_inst_info_t inst_info;
  697. vpudrv_instanace_list_t *vil, *n;
  698. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_INSTANCE_NUM\n");
  699. ret = copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t));
  700. if (ret != 0)
  701. break;
  702. inst_info.inst_open_count = 0;
  703. spin_lock(&s_vpu_lock);
  704. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  705. {
  706. if (vil->core_idx == inst_info.core_idx)
  707. inst_info.inst_open_count++;
  708. }
  709. spin_unlock(&s_vpu_lock);
  710. ret = copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t));
  711. DPRINTK("[VPUDRV] VDI_IOCTL_GET_INSTANCE_NUM core_idx=%d, inst_idx=%d, open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, inst_info.inst_open_count);
  712. }
  713. break;
  714. case VDI_IOCTL_RESET:
  715. {
  716. vpu_hw_reset();
  717. }
  718. break;
  719. case VDI_IOCTL_GET_REGISTER_INFO:
  720. {
  721. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_REGISTER_INFO\n");
  722. ret = copy_to_user((void __user *)arg, &s_vpu_register, sizeof(vpudrv_buffer_t));
  723. if (ret != 0)
  724. ret = -EFAULT;
  725. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_REGISTER_INFO s_vpu_register.phys_addr==0x%lx, s_vpu_register.virt_addr=0x%lx, s_vpu_register.size=%d\n", s_vpu_register.phys_addr , s_vpu_register.virt_addr, s_vpu_register.size);
  726. }
  727. break;
  728. case VDI_IOCTL_FLUSH_DCACHE:
  729. {
  730. vpudrv_flush_cache_t cache_info;
  731. DPRINTK("[JPUDRV][+]VDI_IOCTL_FLUSH_DCACHE\n");
  732. ret = copy_from_user(&cache_info, (vpudrv_flush_cache_t *)arg, sizeof(vpudrv_flush_cache_t));
  733. if (ret != 0)
  734. ret = -EFAULT;
  735. if(cache_info.flag)
  736. starfive_flush_dcache(cache_info.start,cache_info.size);
  737. DPRINTK("[JPUDRV][-]VDI_IOCTL_FLUSH_DCACHE\n");
  738. break;
  739. }
  740. case VDI_IOCTL_DEVFREQ_SET:
  741. {
  742. vpudrv_devfreq_info_t devfreq_info;
  743. ret = copy_from_user(&devfreq_info, (vpudrv_devfreq_info_t *)arg, sizeof(vpudrv_devfreq_info_t));
  744. if (ret != 0)
  745. ret = -EFAULT;
  746. vpu_devfreq_select(&devfreq_info);
  747. break;
  748. }
  749. default:
  750. {
  751. printk(KERN_ERR "[VPUDRV] No such IOCTL, cmd is %d\n", cmd);
  752. }
  753. break;
  754. }
  755. return ret;
  756. }
  757. static ssize_t vpu_read(struct file *filp, char __user *buf, size_t len, loff_t *ppos)
  758. {
  759. return -1;
  760. }
  761. static ssize_t vpu_write(struct file *filp, const char __user *buf, size_t len, loff_t *ppos)
  762. {
  763. /* DPRINTK("[VPUDRV] vpu_write len=%d\n", (int)len); */
  764. if (!buf) {
  765. printk(KERN_ERR "[VPUDRV] vpu_write buf = NULL error \n");
  766. return -EFAULT;
  767. }
  768. if (len == sizeof(vpu_bit_firmware_info_t)) {
  769. vpu_bit_firmware_info_t *bit_firmware_info;
  770. bit_firmware_info = kmalloc(sizeof(vpu_bit_firmware_info_t), GFP_KERNEL);
  771. if (!bit_firmware_info) {
  772. printk(KERN_ERR "[VPUDRV] vpu_write bit_firmware_info allocation error \n");
  773. return -EFAULT;
  774. }
  775. if (copy_from_user(bit_firmware_info, buf, len)) {
  776. printk(KERN_ERR "[VPUDRV] vpu_write copy_from_user error for bit_firmware_info\n");
  777. return -EFAULT;
  778. }
  779. if (bit_firmware_info->size == sizeof(vpu_bit_firmware_info_t)) {
  780. DPRINTK("[VPUDRV] vpu_write set bit_firmware_info coreIdx=0x%x, reg_base_offset=0x%x size=0x%x, bit_code[0]=0x%x\n",
  781. bit_firmware_info->core_idx, (int)bit_firmware_info->reg_base_offset, bit_firmware_info->size, bit_firmware_info->bit_code[0]);
  782. if (bit_firmware_info->core_idx > MAX_NUM_VPU_CORE) {
  783. printk(KERN_ERR "[VPUDRV] vpu_write coreIdx[%d] is exceeded than MAX_NUM_VPU_CORE[%d]\n", bit_firmware_info->core_idx, MAX_NUM_VPU_CORE);
  784. return -ENODEV;
  785. }
  786. memcpy((void *)&s_bit_firmware_info[bit_firmware_info->core_idx], bit_firmware_info, sizeof(vpu_bit_firmware_info_t));
  787. kfree(bit_firmware_info);
  788. return len;
  789. }
  790. kfree(bit_firmware_info);
  791. }
  792. return -1;
  793. }
  794. static int vpu_release(struct inode *inode, struct file *filp)
  795. {
  796. int ret = 0;
  797. DPRINTK("[VPUDRV] vpu_release\n");
  798. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  799. /* found and free the not handled buffer by user applications */
  800. vpu_free_buffers(filp);
  801. /* found and free the not closed instance by user applications */
  802. vpu_free_instances(filp);
  803. s_vpu_drv_context.open_count--;
  804. if (s_vpu_drv_context.open_count == 0) {
  805. if (s_instance_pool.base) {
  806. DPRINTK("[VPUDRV] free instance pool\n");
  807. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  808. vfree((const void *)s_instance_pool.base);
  809. #else
  810. vpu_free_dma_buffer(&s_instance_pool);
  811. #endif
  812. s_instance_pool.base = 0;
  813. }
  814. if (s_common_memory.base) {
  815. DPRINTK("[VPUDRV] free common memory\n");
  816. vpu_free_dma_buffer(&s_common_memory);
  817. s_common_memory.base = 0;
  818. }
  819. }
  820. }
  821. up(&s_vpu_sem);
  822. pm_runtime_put_sync(s_vpu_clk->dev);
  823. return 0;
  824. }
  825. static int vpu_fasync(int fd, struct file *filp, int mode)
  826. {
  827. struct vpu_drv_context_t *dev = (struct vpu_drv_context_t *)filp->private_data;
  828. return fasync_helper(fd, filp, mode, &dev->async_queue);
  829. }
  830. static int vpu_map_to_register(struct file *fp, struct vm_area_struct *vm)
  831. {
  832. unsigned long pfn;
  833. vm->vm_flags |= VM_IO | VM_RESERVED;
  834. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  835. pfn = s_vpu_register.phys_addr >> PAGE_SHIFT;
  836. return remap_pfn_range(vm, vm->vm_start, pfn, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  837. }
  838. static int vpu_map_to_physical_memory(struct file *fp, struct vm_area_struct *vm)
  839. {
  840. vm->vm_flags |= VM_IO | VM_RESERVED;
  841. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  842. return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  843. }
  844. static int vpu_map_to_instance_pool_memory(struct file *fp, struct vm_area_struct *vm)
  845. {
  846. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  847. int ret;
  848. long length = vm->vm_end - vm->vm_start;
  849. unsigned long start = vm->vm_start;
  850. char *vmalloc_area_ptr = (char *)s_instance_pool.base;
  851. unsigned long pfn;
  852. vm->vm_flags |= VM_RESERVED;
  853. /* loop over all pages, map it page individually */
  854. while (length > 0)
  855. {
  856. pfn = vmalloc_to_pfn(vmalloc_area_ptr);
  857. if ((ret = remap_pfn_range(vm, start, pfn, PAGE_SIZE, PAGE_SHARED)) < 0) {
  858. return ret;
  859. }
  860. start += PAGE_SIZE;
  861. vmalloc_area_ptr += PAGE_SIZE;
  862. length -= PAGE_SIZE;
  863. }
  864. return 0;
  865. #else
  866. vm->vm_flags |= VM_RESERVED;
  867. return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  868. #endif
  869. }
  870. /*!
  871. * @brief memory map interface for vpu file operation
  872. * @return 0 on success or negative error code on error
  873. */
  874. static int vpu_mmap(struct file *fp, struct vm_area_struct *vm)
  875. {
  876. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  877. if (vm->vm_pgoff == 0)
  878. return vpu_map_to_instance_pool_memory(fp, vm);
  879. if (vm->vm_pgoff == (s_vpu_register.phys_addr>>PAGE_SHIFT))
  880. return vpu_map_to_register(fp, vm);
  881. return vpu_map_to_physical_memory(fp, vm);
  882. #else
  883. if (vm->vm_pgoff) {
  884. if (vm->vm_pgoff == (s_instance_pool.phys_addr>>PAGE_SHIFT))
  885. return vpu_map_to_instance_pool_memory(fp, vm);
  886. return vpu_map_to_physical_memory(fp, vm);
  887. } else {
  888. return vpu_map_to_register(fp, vm);
  889. }
  890. #endif
  891. }
  892. struct file_operations vpu_fops = {
  893. .owner = THIS_MODULE,
  894. .open = vpu_open,
  895. .read = vpu_read,
  896. .write = vpu_write,
  897. /*.ioctl = vpu_ioctl, // for kernel 2.6.9 of C&M*/
  898. .unlocked_ioctl = vpu_ioctl,
  899. .release = vpu_release,
  900. .fasync = vpu_fasync,
  901. .mmap = vpu_mmap,
  902. };
  903. static int vpu_probe(struct platform_device *pdev)
  904. {
  905. int err = 0;
  906. struct resource *res = NULL;
  907. struct device *devices;
  908. int irq = -1;
  909. DPRINTK("[VPUDRV] vpu_probe\n");
  910. if(pdev){
  911. vpu_dev = &pdev->dev;
  912. vpu_dev->coherent_dma_mask = 0xffffffff;
  913. }
  914. if (pdev)
  915. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  916. if (res) {/* if platform driver is implemented */
  917. s_vpu_register.phys_addr = res->start;
  918. s_vpu_register.virt_addr = (unsigned long)ioremap_nocache(res->start, res->end - res->start);
  919. s_vpu_register.size = res->end - res->start;
  920. DPRINTK("[VPUDRV] : vpu base address get from platform driver physical base addr==0x%lx, virtual base=0x%lx\n", s_vpu_register.phys_addr , s_vpu_register.virt_addr);
  921. } else {
  922. s_vpu_register.phys_addr = VPU_REG_BASE_ADDR;
  923. s_vpu_register.virt_addr = (unsigned long)ioremap_nocache(s_vpu_register.phys_addr, VPU_REG_SIZE);
  924. s_vpu_register.size = VPU_REG_SIZE;
  925. DPRINTK("[VPUDRV] : vpu base address get from defined value physical base addr==0x%lx, virtual base=0x%lx\n", s_vpu_register.phys_addr, s_vpu_register.virt_addr);
  926. }
  927. /* get the major number of the character device */
  928. if ((alloc_chrdev_region(&s_vpu_devt, 0, 1, VPU_DEV_NAME)) < 0) {
  929. err = -EBUSY;
  930. printk(KERN_ERR "could not allocate major number\n");
  931. goto ERROR_PROVE_DEVICE;
  932. }
  933. printk(KERN_INFO "SUCCESS alloc_chrdev_region\n");
  934. s_vpu_major = MAJOR(s_vpu_devt);
  935. /* initialize the device structure and register the device with the kernel */
  936. cdev_init(&s_vpu_cdev, &vpu_fops);
  937. if ((cdev_add(&s_vpu_cdev, s_vpu_devt, 1)) < 0) {
  938. err = -EBUSY;
  939. printk(KERN_ERR "could not allocate chrdev\n");
  940. goto ERROR_PROVE_DEVICE;
  941. }
  942. s_vpu_class = class_create(THIS_MODULE, VPU_DEV_NAME);
  943. if (IS_ERR(s_vpu_class)) {
  944. dev_err(vpu_dev, "class creat error.\n");
  945. goto ERROR_CRART_CLASS;
  946. }
  947. devices = device_create(s_vpu_class, 0, MKDEV(s_vpu_major, 0),
  948. NULL, VPU_DEV_NAME);
  949. if (IS_ERR(devices)) {
  950. dev_err(vpu_dev, "device creat error.\n");
  951. goto ERROR_CREAT_DEVICE;
  952. }
  953. if (pdev)
  954. s_vpu_clk = vpu_clk_get(pdev);
  955. else
  956. s_vpu_clk = vpu_clk_get(NULL);
  957. if (!s_vpu_clk)
  958. printk(KERN_ERR "[VPUDRV] : not support clock controller.\n");
  959. else
  960. DPRINTK("[VPUDRV] : get clock controller s_vpu_clk=%p\n", s_vpu_clk);
  961. vpu_pmu_enable(s_vpu_clk->dev);
  962. vpu_clk_enable(s_vpu_clk);
  963. reset_control_deassert(s_vpu_clk->resets);
  964. #ifdef VPU_SUPPORT_ISR
  965. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  966. if (pdev)
  967. irq = platform_get_irq(pdev, 0);
  968. if (irq >= 0) {/* if platform driver is implemented */
  969. s_vpu_irq = irq;
  970. DPRINTK("[VPUDRV] : vpu irq number get from platform driver irq=0x%x\n", s_vpu_irq);
  971. } else {
  972. DPRINTK("[VPUDRV] : vpu irq number get from defined value irq=0x%x\n", s_vpu_irq);
  973. }
  974. #else
  975. DPRINTK("[VPUDRV] : vpu irq number get from defined value irq=0x%x\n", s_vpu_irq);
  976. #endif
  977. err = request_irq(s_vpu_irq, vpu_irq_handler, 0, "VPU_CODEC_IRQ", (void *)(&s_vpu_drv_context));
  978. if (err) {
  979. printk(KERN_ERR "[VPUDRV] : fail to register interrupt handler\n");
  980. goto ERROR_PROVE_DEVICE;
  981. }
  982. #endif
  983. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  984. s_video_memory.size = VPU_INIT_VIDEO_MEMORY_SIZE_IN_BYTE;
  985. s_video_memory.phys_addr = VPU_DRAM_PHYSICAL_BASE;
  986. s_video_memory.base = (unsigned long)ioremap_nocache(s_video_memory.phys_addr, PAGE_ALIGN(s_video_memory.size));
  987. if (!s_video_memory.base) {
  988. printk(KERN_ERR "[VPUDRV] : fail to remap video memory physical phys_addr==0x%lx, base==0x%lx, size=%d\n", s_video_memory.phys_addr, s_video_memory.base, (int)s_video_memory.size);
  989. goto ERROR_PROVE_DEVICE;
  990. }
  991. if (vmem_init(&s_vmem, s_video_memory.phys_addr, s_video_memory.size) < 0) {
  992. printk(KERN_ERR "[VPUDRV] : fail to init vmem system\n");
  993. goto ERROR_PROVE_DEVICE;
  994. }
  995. DPRINTK("[VPUDRV] success to probe vpu device with reserved video memory phys_addr==0x%lx, base = =0x%lx\n", s_video_memory.phys_addr, s_video_memory.base);
  996. #else
  997. DPRINTK("[VPUDRV] success to probe vpu device with non reserved video memory\n");
  998. #endif
  999. return 0;
  1000. ERROR_CREAT_DEVICE:
  1001. class_destroy(s_vpu_class);
  1002. ERROR_CRART_CLASS:
  1003. cdev_del(&s_vpu_cdev);
  1004. ERROR_PROVE_DEVICE:
  1005. if (s_vpu_major)
  1006. unregister_chrdev_region(s_vpu_major, 1);
  1007. if (s_vpu_register.virt_addr)
  1008. iounmap((void *)s_vpu_register.virt_addr);
  1009. return err;
  1010. }
  1011. static int vpu_remove(struct platform_device *pdev)
  1012. {
  1013. DPRINTK("[VPUDRV] vpu_remove\n");
  1014. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1015. if (s_instance_pool.base) {
  1016. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1017. vfree((const void *)s_instance_pool.base);
  1018. #else
  1019. vpu_free_dma_buffer(&s_instance_pool);
  1020. #endif
  1021. s_instance_pool.base = 0;
  1022. }
  1023. if (s_common_memory.base) {
  1024. vpu_free_dma_buffer(&s_common_memory);
  1025. s_common_memory.base = 0;
  1026. }
  1027. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1028. if (s_video_memory.base) {
  1029. iounmap((void *)s_video_memory.base);
  1030. s_video_memory.base = 0;
  1031. vmem_exit(&s_vmem);
  1032. }
  1033. #endif
  1034. if (s_vpu_major > 0) {
  1035. device_destroy(s_vpu_class, MKDEV(s_vpu_major, 0));
  1036. class_destroy(s_vpu_class);
  1037. cdev_del(&s_vpu_cdev);
  1038. unregister_chrdev_region(s_vpu_devt, 1);
  1039. s_vpu_major = 0;
  1040. }
  1041. #ifdef VPU_SUPPORT_ISR
  1042. if (s_vpu_irq)
  1043. free_irq(s_vpu_irq, &s_vpu_drv_context);
  1044. #endif
  1045. if (s_vpu_register.virt_addr)
  1046. iounmap((void *)s_vpu_register.virt_addr);
  1047. vpu_clk_put(s_vpu_clk);
  1048. vpu_pmu_disable(&pdev->dev);
  1049. #endif /*VPU_SUPPORT_PLATFORM_DRIVER_REGISTER*/
  1050. return 0;
  1051. }
  1052. #ifdef CONFIG_PM
  1053. #define W4_MAX_CODE_BUF_SIZE (512*1024)
  1054. #define W4_CMD_INIT_VPU (0x0001)
  1055. #define W4_CMD_SLEEP_VPU (0x0400)
  1056. #define W4_CMD_WAKEUP_VPU (0x0800)
  1057. #define W5_CMD_SLEEP_VPU (0x0004)
  1058. #define W5_CMD_WAKEUP_VPU (0x0002)
  1059. static void Wave4BitIssueCommand(int core, u32 cmd)
  1060. {
  1061. WriteVpuRegister(W4_VPU_BUSY_STATUS, 1);
  1062. WriteVpuRegister(W4_CORE_INDEX, 0);
  1063. /* coreIdx = ReadVpuRegister(W4_VPU_BUSY_STATUS);*/
  1064. /* coreIdx = 0;*/
  1065. /* WriteVpuRegister(W4_INST_INDEX, (instanceIndex&0xffff)|(codecMode<<16));*/
  1066. WriteVpuRegister(W4_COMMAND, cmd);
  1067. WriteVpuRegister(W4_VPU_HOST_INT_REQ, 1);
  1068. return;
  1069. }
  1070. static int __maybe_unused vpu_runtime_suspend(struct device *dev)
  1071. {
  1072. reset_control_assert(s_vpu_clk->resets);
  1073. vpu_clk_disable(s_vpu_clk);
  1074. return 0;
  1075. }
  1076. static int __maybe_unused vpu_runtime_resume(struct device *dev)
  1077. {
  1078. vpu_clk_enable(s_vpu_clk);
  1079. return reset_control_deassert(s_vpu_clk->resets);
  1080. }
  1081. #ifdef CONFIG_PM_SLEEP
  1082. static int __maybe_unused vpu_suspend(struct device *dev)
  1083. {
  1084. int i;
  1085. int core;
  1086. unsigned long timeout = jiffies + HZ; /* vpu wait timeout to 1sec */
  1087. int product_code;
  1088. DPRINTK("[VPUDRV] vpu_suspend\n");
  1089. pm_runtime_get_sync(dev);
  1090. if (s_vpu_open_ref_count > 0) {
  1091. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  1092. if (s_bit_firmware_info[core].size == 0)
  1093. continue;
  1094. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  1095. if (PRODUCT_CODE_W_SERIES(product_code)) {
  1096. unsigned long cmd_reg = W4_CMD_SLEEP_VPU;
  1097. unsigned long suc_reg = W4_RET_SUCCESS;
  1098. while (ReadVpuRegister(W4_VPU_BUSY_STATUS)) {
  1099. if (time_after(jiffies, timeout)) {
  1100. DPRINTK("SLEEP_VPU BUSY timeout");
  1101. goto DONE_SUSPEND;
  1102. }
  1103. }
  1104. if (product_code == WAVE512_CODE || product_code == WAVE520_CODE) {
  1105. cmd_reg = W5_CMD_SLEEP_VPU;
  1106. suc_reg = W5_RET_SUCCESS;
  1107. }
  1108. Wave4BitIssueCommand(core, cmd_reg);
  1109. while (ReadVpuRegister(W4_VPU_BUSY_STATUS)) {
  1110. if (time_after(jiffies, timeout)) {
  1111. DPRINTK("SLEEP_VPU BUSY timeout");
  1112. goto DONE_SUSPEND;
  1113. }
  1114. }
  1115. if (ReadVpuRegister(suc_reg) == 0) {
  1116. DPRINTK("SLEEP_VPU failed [0x%x]", ReadVpuRegister(W4_RET_FAIL_REASON));
  1117. goto DONE_SUSPEND;
  1118. }
  1119. }
  1120. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  1121. while (ReadVpuRegister(BIT_BUSY_FLAG)) {
  1122. if (time_after(jiffies, timeout))
  1123. goto DONE_SUSPEND;
  1124. }
  1125. for (i = 0; i < 64; i++)
  1126. s_vpu_reg_store[core][i] = ReadVpuRegister(BIT_BASE+(0x100+(i * 4)));
  1127. }
  1128. else {
  1129. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  1130. goto DONE_SUSPEND;
  1131. }
  1132. }
  1133. }
  1134. DONE_SUSPEND:
  1135. pm_runtime_put_sync(dev);
  1136. pm_runtime_force_suspend(dev);
  1137. return 0;
  1138. }
  1139. static int __maybe_unused vpu_resume(struct device *dev)
  1140. {
  1141. int i;
  1142. int core;
  1143. u32 val;
  1144. unsigned long timeout = jiffies + HZ; /* vpu wait timeout to 1sec */
  1145. int product_code;
  1146. unsigned long code_base;
  1147. u32 code_size;
  1148. u32 remap_size;
  1149. int regVal;
  1150. u32 hwOption = 0;
  1151. DPRINTK("[VPUDRV] vpu_resume\n");
  1152. pm_runtime_force_resume(dev);
  1153. pm_runtime_get_sync(dev);
  1154. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  1155. if (s_bit_firmware_info[core].size == 0) {
  1156. continue;
  1157. }
  1158. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  1159. if (PRODUCT_CODE_W_SERIES(product_code)) {
  1160. unsigned long addr_code_base_reg = W4_ADDR_CODE_BASE;
  1161. unsigned long code_size_reg = W4_CODE_SIZE;
  1162. unsigned long code_param_reg = W4_CODE_PARAM;
  1163. unsigned long timeout_cnt_reg = W4_INIT_VPU_TIME_OUT_CNT;
  1164. unsigned long hw_opt_reg = W4_HW_OPTION;
  1165. unsigned long suc_reg = W4_RET_SUCCESS;
  1166. if (product_code == WAVE512_CODE || product_code == WAVE520_CODE) {
  1167. addr_code_base_reg = W5_ADDR_CODE_BASE;
  1168. code_size_reg = W5_CODE_SIZE;
  1169. code_param_reg = W5_CODE_PARAM;
  1170. timeout_cnt_reg = W5_INIT_VPU_TIME_OUT_CNT;
  1171. hw_opt_reg = W5_HW_OPTION;
  1172. suc_reg = W5_RET_SUCCESS;
  1173. }
  1174. code_base = s_common_memory.phys_addr;
  1175. /* ALIGN TO 4KB */
  1176. code_size = (W4_MAX_CODE_BUF_SIZE&~0xfff);
  1177. if (code_size < s_bit_firmware_info[core].size*2) {
  1178. goto DONE_WAKEUP;
  1179. }
  1180. regVal = 0;
  1181. WriteVpuRegister(W4_PO_CONF, regVal);
  1182. /* Reset All blocks */
  1183. regVal = 0x7ffffff;
  1184. WriteVpuRegister(W4_VPU_RESET_REQ, regVal); /*Reset All blocks*/
  1185. /* Waiting reset done */
  1186. while (ReadVpuRegister(W4_VPU_RESET_STATUS)) {
  1187. if (time_after(jiffies, timeout))
  1188. goto DONE_WAKEUP;
  1189. }
  1190. WriteVpuRegister(W4_VPU_RESET_REQ, 0);
  1191. /* remap page size */
  1192. remap_size = (code_size >> 12) & 0x1ff;
  1193. regVal = 0x80000000 | (W4_REMAP_CODE_INDEX<<12) | (0 << 16) | (1<<11) | remap_size;
  1194. WriteVpuRegister(W4_VPU_REMAP_CTRL, regVal);
  1195. WriteVpuRegister(W4_VPU_REMAP_VADDR, 0x00000000); /* DO NOT CHANGE! */
  1196. WriteVpuRegister(W4_VPU_REMAP_PADDR, code_base);
  1197. WriteVpuRegister(addr_code_base_reg, code_base);
  1198. WriteVpuRegister(code_size_reg, code_size);
  1199. WriteVpuRegister(code_param_reg, 0);
  1200. WriteVpuRegister(timeout_cnt_reg, timeout);
  1201. WriteVpuRegister(hw_opt_reg, hwOption);
  1202. /* Interrupt */
  1203. if (product_code == WAVE512_CODE) {
  1204. // decoder
  1205. regVal = (1<<W5_INT_INIT_SEQ);
  1206. regVal |= (1<<W5_INT_DEC_PIC);
  1207. regVal |= (1<<W5_INT_BSBUF_EMPTY);
  1208. }
  1209. else if (product_code == WAVE520_CODE) {
  1210. regVal = (1<<W5_INT_ENC_SET_PARAM);
  1211. regVal |= (1<<W5_INT_ENC_PIC);
  1212. }
  1213. else {
  1214. regVal = (1<<W4_INT_DEC_PIC_HDR);
  1215. regVal |= (1<<W4_INT_DEC_PIC);
  1216. regVal |= (1<<W4_INT_QUERY_DEC);
  1217. regVal |= (1<<W4_INT_SLEEP_VPU);
  1218. regVal |= (1<<W4_INT_BSBUF_EMPTY);
  1219. }
  1220. WriteVpuRegister(W4_VPU_VINT_ENABLE, regVal);
  1221. Wave4BitIssueCommand(core, W4_CMD_INIT_VPU);
  1222. WriteVpuRegister(W4_VPU_REMAP_CORE_START, 1);
  1223. while (ReadVpuRegister(W4_VPU_BUSY_STATUS)) {
  1224. if (time_after(jiffies, timeout))
  1225. goto DONE_WAKEUP;
  1226. }
  1227. if (ReadVpuRegister(suc_reg) == 0) {
  1228. DPRINTK("WAKEUP_VPU failed [0x%x]", ReadVpuRegister(W4_RET_FAIL_REASON));
  1229. goto DONE_WAKEUP;
  1230. }
  1231. }
  1232. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  1233. WriteVpuRegister(BIT_CODE_RUN, 0);
  1234. /*---- LOAD BOOT CODE*/
  1235. for (i = 0; i < 512; i++) {
  1236. val = s_bit_firmware_info[core].bit_code[i];
  1237. WriteVpuRegister(BIT_CODE_DOWN, ((i << 16) | val));
  1238. }
  1239. for (i = 0 ; i < 64 ; i++)
  1240. WriteVpuRegister(BIT_BASE+(0x100+(i * 4)), s_vpu_reg_store[core][i]);
  1241. WriteVpuRegister(BIT_BUSY_FLAG, 1);
  1242. WriteVpuRegister(BIT_CODE_RESET, 1);
  1243. WriteVpuRegister(BIT_CODE_RUN, 1);
  1244. while (ReadVpuRegister(BIT_BUSY_FLAG)) {
  1245. if (time_after(jiffies, timeout))
  1246. goto DONE_WAKEUP;
  1247. }
  1248. }
  1249. else {
  1250. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  1251. goto DONE_WAKEUP;
  1252. }
  1253. }
  1254. DONE_WAKEUP:
  1255. pm_runtime_put_sync(dev);
  1256. return 0;
  1257. }
  1258. #endif /* CONFIG_PM_SLEEP */
  1259. #endif /* CONFIG_PM */
  1260. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1261. static const struct of_device_id vpu_of_id_table[] = {
  1262. { .compatible = "cnm,cnm420l-vpu" },
  1263. { .compatible = "starfive,venc" },
  1264. {}
  1265. };
  1266. MODULE_DEVICE_TABLE(of, vpu_of_id_table);
  1267. static const struct dev_pm_ops cm_vpu_pm_ops = {
  1268. SET_RUNTIME_PM_OPS(vpu_runtime_suspend,
  1269. vpu_runtime_resume, NULL)
  1270. SET_SYSTEM_SLEEP_PM_OPS(vpu_suspend, vpu_resume)
  1271. };
  1272. static struct platform_driver vpu_driver = {
  1273. .driver = {
  1274. .name = VPU_PLATFORM_DEVICE_NAME,
  1275. .of_match_table = of_match_ptr(vpu_of_id_table),
  1276. .pm = &cm_vpu_pm_ops,
  1277. },
  1278. .probe = vpu_probe,
  1279. .remove = vpu_remove,
  1280. };
  1281. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1282. static int __init vpu_init(void)
  1283. {
  1284. int res;
  1285. DPRINTK("[VPUDRV] begin vpu_init\n");
  1286. init_waitqueue_head(&s_interrupt_wait_q);
  1287. s_common_memory.base = 0;
  1288. s_instance_pool.base = 0;
  1289. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1290. res = platform_driver_register(&vpu_driver);
  1291. #else
  1292. res = vpu_probe(NULL);
  1293. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1294. DPRINTK("[VPUDRV] end vpu_init result=0x%x\n", res);
  1295. return res;
  1296. }
  1297. static void __exit vpu_exit(void)
  1298. {
  1299. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1300. DPRINTK("[VPUDRV] vpu_exit\n");
  1301. platform_driver_unregister(&vpu_driver);
  1302. #else /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1303. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1304. #else
  1305. vpu_clk_disable(s_vpu_clk);
  1306. #endif
  1307. vpu_clk_put(s_vpu_clk);
  1308. if (s_instance_pool.base) {
  1309. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1310. vfree((const void *)s_instance_pool.base);
  1311. #else
  1312. vpu_free_dma_buffer(&s_instance_pool);
  1313. #endif
  1314. s_instance_pool.base = 0;
  1315. }
  1316. if (s_common_memory.base) {
  1317. vpu_free_dma_buffer(&s_common_memory);
  1318. s_common_memory.base = 0;
  1319. }
  1320. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1321. if (s_video_memory.base) {
  1322. iounmap((void *)s_video_memory.base);
  1323. s_video_memory.base = 0;
  1324. vmem_exit(&s_vmem);
  1325. }
  1326. #endif
  1327. if (s_vpu_major > 0) {
  1328. device_destroy(s_vpu_class, MKDEV(s_vpu_major, 0));
  1329. class_destroy(s_vpu_class);
  1330. cdev_del(&s_vpu_cdev);
  1331. unregister_chrdev_region(s_vpu_devt, 1);
  1332. s_vpu_major = 0;
  1333. }
  1334. #ifdef VPU_SUPPORT_ISR
  1335. if (s_vpu_irq)
  1336. free_irq(s_vpu_irq, &s_vpu_drv_context);
  1337. #endif
  1338. if (s_vpu_register.virt_addr) {
  1339. iounmap((void *)s_vpu_register.virt_addr);
  1340. s_vpu_register.virt_addr = 0x00;
  1341. }
  1342. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1343. return;
  1344. }
  1345. MODULE_AUTHOR("A customer using C&M VPU, Inc.");
  1346. MODULE_DESCRIPTION("VPU linux driver");
  1347. MODULE_LICENSE("Dual BSD/GPL");
  1348. module_init(vpu_init);
  1349. module_exit(vpu_exit);
  1350. static int vpu_pmu_enable(struct device *dev)
  1351. {
  1352. pm_runtime_set_active(dev);
  1353. pm_runtime_enable(dev);
  1354. return 0;
  1355. }
  1356. static void vpu_pmu_disable(struct device *dev)
  1357. {
  1358. pm_runtime_disable(dev);
  1359. pm_runtime_set_suspended(dev);
  1360. }
  1361. #ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  1362. #define CLK_ENABLE_DATA 1
  1363. #define CLK_DISABLE_DATA 0
  1364. #define CLK_EN_SHIFT 31
  1365. #define CLK_EN_MASK 0x80000000U
  1366. #define SAIF_BD_APBS_BASE 0x13020000
  1367. #define WAVE420L_CLK_AXI_CTRL 0x138U
  1368. #define WAVE420L_CLK_BPU_CTRL 0x13cU
  1369. #define WAVE420L_CLK_VCE_CTRL 0x140U
  1370. #define WAVE420L_CLK_APB_CTRL 0x144U
  1371. #define WAVE420L_CLK_NOCBUS_CTRL 0x148U
  1372. #define RSTGEN_SOFTWARE_RESET_ASSERT1 0x2FCU
  1373. #define RSTGEN_SOFTWARE_RESET_STATUS1 0x30CU
  1374. #define RSTN_AXI_MASK (0x1 << 22)
  1375. #define RSTN_BPU_MASK (0x1 << 23)
  1376. #define RSTN_VCE_MASK (0x1 << 24)
  1377. #define RSTN_APB_MASK (0x1 << 25)
  1378. #define RSTN_128B_AXIMEM_MASK (0x1 << 26)
  1379. static void saif_set_reg(volatile void __iomem *addr, uint32_t data,
  1380. uint32_t shift, uint32_t mask)
  1381. {
  1382. uint32_t tmp;
  1383. tmp = readl(addr);
  1384. tmp &= ~mask;
  1385. tmp |= (data << shift) & mask;
  1386. writel(tmp, addr);
  1387. }
  1388. static void saif_assert_rst(volatile void __iomem *addr,
  1389. const volatile void __iomem *addr_status, uint32_t mask)
  1390. {
  1391. uint32_t tmp;
  1392. tmp = readl(addr);
  1393. tmp |= mask;
  1394. writel(tmp, addr);
  1395. do {
  1396. tmp = readl(addr_status);
  1397. } while ((tmp & mask) != 0);
  1398. }
  1399. static void saif_clear_rst(volatile void __iomem *addr,
  1400. const volatile void __iomem *addr_status, uint32_t mask)
  1401. {
  1402. uint32_t tmp;
  1403. tmp = readl(addr);
  1404. tmp &= ~mask;
  1405. writel(tmp, addr);
  1406. do {
  1407. tmp = readl(addr_status);
  1408. } while ((tmp & mask) != mask);
  1409. }
  1410. static void vpu_noc_vdec_bus_control(vpu_clk_t *clk, bool enable)
  1411. {
  1412. if (enable)
  1413. saif_set_reg(clk->noc_bus, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1414. else
  1415. saif_set_reg(clk->noc_bus, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1416. }
  1417. static void vpu_clk_control(vpu_clk_t *clk, bool enable)
  1418. {
  1419. if (enable) {
  1420. /*enable*/
  1421. saif_set_reg(clk->apb_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1422. saif_set_reg(clk->axi_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1423. saif_set_reg(clk->bpu_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1424. saif_set_reg(clk->vce_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1425. /*clr-reset*/
  1426. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1427. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1428. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1429. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1430. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->aximem_128b.rst_mask);
  1431. } else {
  1432. /*assert-reset*/
  1433. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1434. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1435. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1436. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1437. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->aximem_128b.rst_mask);
  1438. /*disable*/
  1439. saif_set_reg(clk->apb_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1440. saif_set_reg(clk->axi_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1441. saif_set_reg(clk->bpu_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1442. saif_set_reg(clk->vce_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1443. }
  1444. }
  1445. static int vpu_of_clk_get(struct platform_device *pdev, vpu_clk_t *vpu_clk)
  1446. {
  1447. if (!pdev)
  1448. return -ENXIO;
  1449. vpu_clk->clkgen = ioremap(SAIF_BD_APBS_BASE, 0x400);
  1450. if (IS_ERR(vpu_clk->clkgen)) {
  1451. dev_err(dev, "ioremap clkgen failed.\n");
  1452. return PTR_ERR(vpu_clk->clkgen);
  1453. }
  1454. /* clkgen define */
  1455. vpu_clk->axi_clk.en_ctrl = vpu_clk->clkgen + WAVE420L_CLK_AXI_CTRL;
  1456. vpu_clk->bpu_clk.en_ctrl = vpu_clk->clkgen + WAVE420L_CLK_BPU_CTRL;
  1457. vpu_clk->vce_clk.en_ctrl = vpu_clk->clkgen + WAVE420L_CLK_VCE_CTRL;
  1458. vpu_clk->apb_clk.en_ctrl = vpu_clk->clkgen + WAVE420L_CLK_APB_CTRL;
  1459. vpu_clk->noc_bus = vpu_clk->clkgen + WAVE420L_CLK_NOCBUS_CTRL;
  1460. vpu_clk->en_mask = CLK_EN_MASK;
  1461. vpu_clk->en_shift = CLK_EN_SHIFT;
  1462. /* rstgen define */
  1463. vpu_clk->rst_ctrl = vpu_clk->clkgen + RSTGEN_SOFTWARE_RESET_ASSERT1;
  1464. vpu_clk->rst_status = vpu_clk->clkgen + RSTGEN_SOFTWARE_RESET_STATUS1;
  1465. vpu_clk->axi_clk.rst_mask = RSTN_AXI_MASK;
  1466. vpu_clk->bpu_clk.rst_mask = RSTN_BPU_MASK;
  1467. vpu_clk->vce_clk.rst_mask = RSTN_VCE_MASK;
  1468. vpu_clk->apb_clk.rst_mask = RSTN_APB_MASK;
  1469. vpu_clk->aximem_128b.rst_mask = RSTN_128B_AXIMEM_MASK;
  1470. if (device_property_read_bool(&pdev->dev, "starfive,venc_noc_ctrl"))
  1471. vpu_clk->noc_ctrl = true;
  1472. return 0;
  1473. }
  1474. static void vpu_clk_reset(vpu_clk_t *clk)
  1475. {
  1476. /*assert-reset*/
  1477. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1478. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1479. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1480. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1481. /*clr-reset*/
  1482. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1483. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1484. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1485. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1486. }
  1487. int vpu_hw_reset(void)
  1488. {
  1489. if (!s_vpu_clk)
  1490. return -1;
  1491. vpu_clk_reset(s_vpu_clk);
  1492. DPRINTK("[VPUDRV] reset vpu hardware. \n");
  1493. return 0;
  1494. }
  1495. struct vpu_clk_t *vpu_clk_get(struct platform_device *pdev)
  1496. {
  1497. vpu_clk_t *vpu_clk;
  1498. vpu_clk = devm_kzalloc(&pdev->dev, sizeof(*vpu_clk), GFP_KERNEL);
  1499. if (!vpu_clk)
  1500. return NULL;
  1501. if (vpu_of_clk_get(dev, vpu_clk))
  1502. goto err_get_clk;
  1503. return vpu_clk;
  1504. err_get_clk:
  1505. devm_kfree(&pdev->dev, vpu_clk);
  1506. return NULL;
  1507. }
  1508. void vpu_clk_put(struct vpu_clk_t *clk)
  1509. {
  1510. if (clk->clkgen) {
  1511. iounmap(clk->clkgen);
  1512. clk->clkgen = NULL;
  1513. }
  1514. }
  1515. static int vpu_clk_enable(struct vpu_clk_t *clk)
  1516. {
  1517. if (clk == NULL || IS_ERR(clk))
  1518. return -1;
  1519. vpu_pmu_enable(clk->dev);
  1520. vpu_clk_control(clk, true);
  1521. if (clk->noc_ctrl == true)
  1522. vpu_noc_vdec_bus_control(clk, true);
  1523. DPRINTK("[VPUDRV] vpu_clk_enable\n");
  1524. return 0;
  1525. }
  1526. void vpu_clk_disable(struct vpu_clk_t *clk)
  1527. {
  1528. if (clk == NULL || IS_ERR(clk))
  1529. return;
  1530. vpu_clk_control(clk, false);
  1531. vpu_pmu_disable(clk->dev);
  1532. if (clk->noc_ctrl == true)
  1533. vpu_noc_vdec_bus_control(clk, false);
  1534. DPRINTK("[VPUDRV] vpu_clk_disable\n");
  1535. }
  1536. #else /*STARFIVE_VPU_SUPPORT_CLOCK_CONTROL*/
  1537. static const struct vpu_dev_freq_list wave420l_dev_freq_lists[MODE_MAX+1] = {
  1538. [MODE_480P_30F] = {
  1539. .mode = MODE_480P_30F,
  1540. .axi_rate = VPU_DEV_FREQ_80,
  1541. .bpu_rate = VPU_DEV_FREQ_80,
  1542. .vce_rate = VPU_DEV_FREQ_80,
  1543. },
  1544. [MODE_480P_60F] = {
  1545. .mode = MODE_480P_60F,
  1546. .axi_rate = VPU_DEV_FREQ_100,
  1547. .bpu_rate = VPU_DEV_FREQ_100,
  1548. .vce_rate = VPU_DEV_FREQ_100,
  1549. },
  1550. [MODE_720P_30F] = {
  1551. .mode = MODE_720P_30F,
  1552. .axi_rate = VPU_DEV_FREQ_150,
  1553. .bpu_rate = VPU_DEV_FREQ_150,
  1554. .vce_rate = VPU_DEV_FREQ_150,
  1555. },
  1556. [MODE_720P_60F] = {
  1557. .mode = MODE_720P_60F,
  1558. .axi_rate = VPU_DEV_FREQ_237,
  1559. .bpu_rate = VPU_DEV_FREQ_237,
  1560. .vce_rate = VPU_DEV_FREQ_237,
  1561. },
  1562. [MODE_1080P_30F] = {
  1563. .mode = MODE_1080P_30F,
  1564. .axi_rate = VPU_DEV_FREQ_300,
  1565. .bpu_rate = VPU_DEV_FREQ_300,
  1566. .vce_rate = VPU_DEV_FREQ_300,
  1567. },
  1568. [MODE_MAX] = {
  1569. .mode = MODE_MAX,
  1570. .axi_rate = VPU_DEV_FREQ_MAX,
  1571. .bpu_rate = VPU_DEV_FREQ_MAX,
  1572. .vce_rate = VPU_DEV_FREQ_MAX,
  1573. },
  1574. };
  1575. static int vpu_devfreq_init(vpu_clk_t *vpu_clk)
  1576. {
  1577. struct vpu_devfreq_t *dev_freq = &vpu_clk->vpu_devfreq;
  1578. dev_freq->axi_clk = devm_clk_get_optional(vpu_clk->dev, "axi_clk");
  1579. if (IS_ERR(dev_freq->axi_clk))
  1580. return PTR_ERR(dev_freq->axi_clk);
  1581. dev_freq->bpu_clk = devm_clk_get_optional(vpu_clk->dev, "bpu_clk");
  1582. if (IS_ERR(dev_freq->bpu_clk))
  1583. return PTR_ERR(dev_freq->bpu_clk);
  1584. dev_freq->vce_clk = devm_clk_get_optional(vpu_clk->dev, "vce_clk");
  1585. if (IS_ERR(dev_freq->vce_clk))
  1586. return PTR_ERR(dev_freq->vce_clk);
  1587. return 0;
  1588. }
  1589. static int vpu_devfreq_set(vpu_clk_t *vpu_clk, const struct vpu_dev_freq_list *freq_list)
  1590. {
  1591. struct vpu_devfreq_t *dev_freq = &vpu_clk->vpu_devfreq;
  1592. int ret;
  1593. dev_dbg(vpu_clk->dev, "axi_clk:%ld bpu_clk:%ld vce_clk:%ld\n",
  1594. freq_list->axi_rate, freq_list->bpu_rate, freq_list->vce_rate);
  1595. ret = clk_set_rate(dev_freq->axi_clk, freq_list->axi_rate);
  1596. if (ret)
  1597. dev_err(vpu_clk->dev, "set clk error, ret:%d \n", ret);
  1598. ret = clk_set_rate(dev_freq->bpu_clk, freq_list->bpu_rate);
  1599. if (ret)
  1600. dev_err(vpu_clk->dev, "set clk error, ret:%d \n", ret);
  1601. ret = clk_set_rate(dev_freq->vce_clk, freq_list->vce_rate);
  1602. if (ret)
  1603. dev_err(vpu_clk->dev, "set clk error, ret:%d \n", ret);
  1604. return ret;
  1605. }
  1606. static int vpu_devfreq_select(struct vpudrv_devfreq_info_t *info)
  1607. {
  1608. unsigned long framsize = info->picWidth*info->picHeight;
  1609. int frameRateInfo = info->frameRateInfo;
  1610. int mode;
  1611. if (frameRateInfo <= 30) {
  1612. if (framsize <= FRAMSIZE_480P)
  1613. mode = MODE_480P_30F;
  1614. else if (framsize <= FRAMSIZE_720P)
  1615. mode = MODE_720P_30F;
  1616. else if (framsize <= FRAMSIZE_1080P)
  1617. mode = MODE_1080P_30F;
  1618. else
  1619. mode = MODE_MAX;
  1620. } else {
  1621. if (framsize <= FRAMSIZE_480P)
  1622. mode = MODE_480P_60F;
  1623. else if (framsize <= FRAMSIZE_720P)
  1624. mode = MODE_720P_60F;
  1625. else
  1626. mode = MODE_MAX;
  1627. }
  1628. return vpu_devfreq_set(s_vpu_clk, &wave420l_dev_freq_lists[mode]);
  1629. }
  1630. int vpu_hw_reset(void)
  1631. {
  1632. DPRINTK("[VPUDRV] reset vpu hardware. \n");
  1633. /* sram do not need reset */
  1634. return reset_control_reset(s_vpu_clk->resets);
  1635. }
  1636. static int vpu_of_clk_get(struct platform_device *pdev, vpu_clk_t *vpu_clk)
  1637. {
  1638. struct device *dev = &pdev->dev;
  1639. int ret;
  1640. vpu_clk->dev = dev;
  1641. vpu_clk->clks = vpu_clks;
  1642. vpu_clk->nr_clks = ARRAY_SIZE(vpu_clks);
  1643. vpu_clk->resets = devm_reset_control_array_get_exclusive(dev);
  1644. if (IS_ERR(vpu_clk->resets)) {
  1645. ret = PTR_ERR(vpu_clk->resets);
  1646. dev_err(dev, "faied to get vpu reset controls\n");
  1647. }
  1648. ret = devm_clk_bulk_get(dev, vpu_clk->nr_clks, vpu_clk->clks);
  1649. if (ret)
  1650. dev_err(dev, "faied to get vpu clk controls\n");
  1651. if (device_property_read_bool(dev, "starfive,venc_noc_ctrl"))
  1652. vpu_clk->noc_ctrl = true;
  1653. return 0;
  1654. }
  1655. static vpu_clk_t *vpu_clk_get(struct platform_device *pdev)
  1656. {
  1657. vpu_clk_t *vpu_clk;
  1658. if (!pdev)
  1659. return NULL;
  1660. vpu_clk = devm_kzalloc(&pdev->dev, sizeof(*vpu_clk), GFP_KERNEL);
  1661. if (!vpu_clk)
  1662. return NULL;
  1663. if (vpu_of_clk_get(pdev, vpu_clk))
  1664. goto err_of_clk_get;
  1665. vpu_devfreq_init(vpu_clk);
  1666. return vpu_clk;
  1667. err_of_clk_get:
  1668. devm_kfree(&pdev->dev, vpu_clk);
  1669. return NULL;
  1670. }
  1671. static void vpu_clk_put(vpu_clk_t *clk)
  1672. {
  1673. clk_bulk_put(clk->nr_clks, clk->clks);
  1674. }
  1675. static int vpu_clk_enable(vpu_clk_t *clk)
  1676. {
  1677. int ret;
  1678. ret = clk_bulk_prepare_enable(clk->nr_clks, clk->clks);
  1679. if (ret)
  1680. dev_err(clk->dev, "enable clk error.\n");
  1681. DPRINTK("[VPUDRV] vpu_clk_enable\n");
  1682. return ret;
  1683. }
  1684. static void vpu_clk_disable(vpu_clk_t *clk)
  1685. {
  1686. clk_bulk_disable_unprepare(clk->nr_clks, clk->clks);
  1687. }
  1688. #endif /*STARFIVE_VPU_SUPPORT_CLOCK_CONTROL*/