jpu.c 43 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. //--=========================================================================--
  3. // This file is linux device driver for JPU.
  4. //-----------------------------------------------------------------------------
  5. //
  6. // This confidential and proprietary software may be used only
  7. // as authorized by a licensing agreement from Chips&Media Inc.
  8. // In the event of publication, the following notice is applicable:
  9. //
  10. // (C) COPYRIGHT 2006 - 2016 CHIPS&MEDIA INC.
  11. // ALL RIGHTS RESERVED
  12. //
  13. // The entire notice above must be reproduced on all authorized
  14. // copies.
  15. // Copyright (C) 2022 StarFive Technology Co., Ltd.
  16. //--=========================================================================-
  17. #include <linux/kernel.h>
  18. #include <linux/device.h>
  19. #include <linux/mm.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/ioport.h>
  22. #include <linux/module.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/dma-mapping.h>
  25. #include <linux/of.h>
  26. #include <linux/of_address.h>
  27. #include <linux/pm_runtime.h>
  28. #include <linux/wait.h>
  29. #include <linux/list.h>
  30. #include <linux/clk.h>
  31. #include <linux/delay.h>
  32. #include <linux/uaccess.h>
  33. #include <linux/cdev.h>
  34. #include <linux/slab.h>
  35. #include <linux/sched.h>
  36. #include <linux/sched/signal.h>
  37. #include <linux/reset.h>
  38. #include <linux/version.h>
  39. #include "../../../jpuapi/jpuconfig.h"
  40. #include "jpu.h"
  41. extern void sifive_ccache_flush_range(phys_addr_t start, size_t len);
  42. extern void sifive_ccache_flush_entire(void);
  43. //#define ENABLE_DEBUG_MSG
  44. #ifdef ENABLE_DEBUG_MSG
  45. #define DPRINTK(args...) printk(KERN_INFO args);
  46. #else
  47. #define DPRINTK(args...)
  48. #endif
  49. /* definitions to be changed as customer configuration */
  50. /* if you want to have clock gating scheme frame by frame */
  51. //#define JPU_SUPPORT_CLOCK_CONTROL
  52. #define JPU_SUPPORT_ISR
  53. //#define JPU_IRQ_CONTROL
  54. /* if clktree is work,try this...*/
  55. #define STARFIVE_JPU_SUPPORT_CLOCK_CONTROL
  56. /* if the platform driver knows the name of this driver */
  57. /* JPU_PLATFORM_DEVICE_NAME */
  58. #define JPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  59. /* if this driver knows the dedicated video memory address */
  60. //#define JPU_SUPPORT_RESERVED_VIDEO_MEMORY //if this driver knows the dedicated video memory address
  61. #define JPU_PLATFORM_DEVICE_NAME "cnm_jpu"
  62. #define JPU_CLK_NAME "jpege"
  63. #define JPU_DEV_NAME "jpu"
  64. #define JPU_REG_BASE_ADDR 0x11900000
  65. #define JPU_REG_SIZE 0x300
  66. #ifdef JPU_SUPPORT_ISR
  67. #define JPU_IRQ_NUM 24
  68. /* if the driver want to disable and enable IRQ whenever interrupt asserted. */
  69. /*#define JPU_IRQ_CONTROL*/
  70. #endif
  71. #ifndef VM_RESERVED /*for kernel up to 3.7.0 version*/
  72. #define VM_RESERVED (VM_DONTEXPAND | VM_DONTDUMP)
  73. #endif
  74. struct device *jpu_dev;
  75. typedef struct jpu_drv_context_t {
  76. struct fasync_struct *async_queue;
  77. u32 open_count; /*!<< device reference count. Not instance count */
  78. u32 interrupt_reason[MAX_NUM_INSTANCE];
  79. } jpu_drv_context_t;
  80. /* To track the allocated memory buffer */
  81. typedef struct jpudrv_buffer_pool_t {
  82. struct list_head list;
  83. struct jpudrv_buffer_t jb;
  84. struct file* filp;
  85. } jpudrv_buffer_pool_t;
  86. /* To track the instance index and buffer in instance pool */
  87. typedef struct jpudrv_instance_list_t {
  88. struct list_head list;
  89. unsigned long inst_idx;
  90. struct file* filp;
  91. } jpudrv_instance_list_t;
  92. typedef struct jpudrv_instance_pool_t {
  93. unsigned char codecInstPool[MAX_NUM_INSTANCE][MAX_INST_HANDLE_SIZE];
  94. } jpudrv_instance_pool_t;
  95. #ifndef STARFIVE_JPU_SUPPORT_CLOCK_CONTROL
  96. typedef struct jpu_clkgen_t {
  97. void __iomem *en_ctrl;
  98. uint32_t rst_mask;
  99. } jpu_clkgen_t;
  100. #endif
  101. struct clk_bulk_data jpu_clks[] = {
  102. { .id = "axi_clk" },
  103. { .id = "core_clk" },
  104. { .id = "apb_clk" },
  105. { .id = "noc_bus" },
  106. };
  107. typedef struct jpu_clk_t {
  108. #ifndef STARFIVE_JPU_SUPPORT_CLOCK_CONTROL
  109. void __iomem *clkgen;
  110. void __iomem *rst_ctrl;
  111. void __iomem *rst_status;
  112. uint32_t en_shift;
  113. uint32_t en_mask;
  114. jpu_clkgen_t apb_clk;
  115. jpu_clkgen_t axi_clk;
  116. jpu_clkgen_t core_clk;
  117. #else
  118. struct clk_bulk_data *clks;
  119. struct reset_control *resets;
  120. int nr_clks;
  121. #endif
  122. struct device *dev;
  123. } jpu_clk_t;
  124. #ifdef JPU_SUPPORT_RESERVED_VIDEO_MEMORY
  125. #include "jmm.h"
  126. static jpu_mm_t s_jmem;
  127. static jpudrv_buffer_t s_video_memory = {0};
  128. #endif /* JPU_SUPPORT_RESERVED_VIDEO_MEMORY */
  129. static int jpu_hw_reset(void);
  130. static void jpu_clk_disable(jpu_clk_t *clk);
  131. static int jpu_clk_enable(jpu_clk_t *clk);
  132. static jpu_clk_t *jpu_clk_get(struct platform_device *pdev);
  133. static void jpu_clk_put(jpu_clk_t *clk);
  134. static int jpu_pmu_enable(struct device *dev);
  135. static void jpu_pmu_disable(struct device *dev);
  136. // end customer definition
  137. static jpudrv_buffer_t s_instance_pool = {0};
  138. static jpu_drv_context_t s_jpu_drv_context;
  139. static dev_t s_jpu_devt;
  140. static int s_jpu_major;
  141. static struct cdev s_jpu_cdev;
  142. static struct class *s_jpu_class;
  143. static jpu_clk_t *s_jpu_clk;
  144. static int s_jpu_open_ref_count;
  145. #ifdef JPU_SUPPORT_ISR
  146. static int s_jpu_irq = JPU_IRQ_NUM;
  147. #endif
  148. static jpudrv_buffer_t s_jpu_register = {0};
  149. static int s_interrupt_flag[MAX_NUM_INSTANCE];
  150. static wait_queue_head_t s_interrupt_wait_q[MAX_NUM_INSTANCE];
  151. static spinlock_t s_jpu_lock = __SPIN_LOCK_UNLOCKED(s_jpu_lock);
  152. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
  153. static DECLARE_MUTEX(s_jpu_sem);
  154. #else
  155. static DEFINE_SEMAPHORE(s_jpu_sem);
  156. #endif
  157. static struct list_head s_jbp_head = LIST_HEAD_INIT(s_jbp_head);
  158. static struct list_head s_inst_list_head = LIST_HEAD_INIT(s_inst_list_head);
  159. #ifdef CONFIG_PM
  160. /* implement to power management functions */
  161. #endif
  162. #define NPT_BASE 0x0000
  163. #define NPT_REG_SIZE 0x300
  164. #define MJPEG_PIC_STATUS_REG(_inst_no) (NPT_BASE + (_inst_no*NPT_REG_SIZE) + 0x004)
  165. #define ReadJpuRegister(addr) *(volatile unsigned int *)(s_jpu_register.virt_addr + addr)
  166. #define WriteJpuRegister(addr, val) *(volatile unsigned int *)(s_jpu_register.virt_addr + addr) = (unsigned int)val
  167. #define WriteJpu(addr, val) *(volatile unsigned int *)(addr) = (unsigned int)val;
  168. static void starfive_flush_dcache(phys_addr_t start, size_t len)
  169. {
  170. #ifdef ARCH_HAS_SYNC_DMA_FOR_DEVICE
  171. dma_sync_single_for_device(jpu_dev, start, len, DMA_FROM_DEVICE);
  172. #else
  173. if (len >= 0x80000)
  174. sifive_ccache_flush_entire();
  175. else
  176. sifive_ccache_flush_range(start, len);
  177. #endif
  178. }
  179. static int jpu_alloc_dma_buffer(jpudrv_buffer_t *jb)
  180. {
  181. if (!jb)
  182. return -1;
  183. #ifdef JPU_SUPPORT_RESERVED_VIDEO_MEMORY
  184. jb->phys_addr = (unsigned long long)jmem_alloc(&s_jmem, jb->size, 0);
  185. if ((unsigned long)jb->phys_addr == (unsigned long)-1) {
  186. printk(KERN_ERR "[JPUDRV] Physical memory allocation error size=%d\n", jb->size);
  187. return -1;
  188. }
  189. jb->base = (unsigned long)(s_video_memory.base + (jb->phys_addr - s_video_memory.phys_addr));
  190. #else
  191. jb->base = (unsigned long)dma_alloc_coherent(jpu_dev, PAGE_ALIGN(jb->size), (dma_addr_t *) (&jb->phys_addr), GFP_DMA | GFP_KERNEL);
  192. if ((void *)(jb->base) == NULL) {
  193. printk(KERN_ERR "[JPUDRV] Physical memory allocation error size=%d\n", jb->size);
  194. return -1;
  195. }
  196. starfive_flush_dcache(jb->phys_addr,PAGE_ALIGN(jb->size));
  197. #endif /* JPU_SUPPORT_RESERVED_VIDEO_MEMORY */
  198. return 0;
  199. }
  200. static void jpu_free_dma_buffer(jpudrv_buffer_t *jb)
  201. {
  202. if (!jb) {
  203. return;
  204. }
  205. if (jb->base)
  206. #ifdef JPU_SUPPORT_RESERVED_VIDEO_MEMORY
  207. jmem_free(&s_jmem, jb->phys_addr, 0);
  208. #else
  209. dma_free_coherent(jpu_dev, PAGE_ALIGN(jb->size), (void *)jb->base, jb->phys_addr);
  210. #endif /* JPUR_SUPPORT_RESERVED_VIDEO_MEMORY */
  211. }
  212. static int jpu_free_instances(struct file *filp)
  213. {
  214. jpudrv_instance_list_t *vil, *n;
  215. jpudrv_instance_pool_t *vip;
  216. void *vip_base;
  217. int instance_pool_size_per_core;
  218. #if !defined(PTHREAD_MUTEX_ROBUST_NP)
  219. void *jdi_mutexes_base;
  220. const int PTHREAD_MUTEX_T_DESTROY_VALUE = 0xdead10cc;
  221. #endif
  222. DPRINTK("[JPUDRV] jpu_free_instances\n");
  223. instance_pool_size_per_core = (s_instance_pool.size/MAX_NUM_JPU_CORE); /* s_instance_pool.size assigned to the size of all core once call JDI_IOCTL_GET_INSTANCE_POOL by user. */
  224. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  225. {
  226. if (vil->filp == filp) {
  227. vip_base = (void *)(s_instance_pool.base + instance_pool_size_per_core);
  228. DPRINTK("[JPUDRV] jpu_free_instances detect instance crash instIdx=%d, vip_base=%p, instance_pool_size_per_core=%d\n", (int)vil->inst_idx, vip_base, (int)instance_pool_size_per_core);
  229. vip = (jpudrv_instance_pool_t *)vip_base;
  230. if (vip) {
  231. memset(&vip->codecInstPool[vil->inst_idx], 0x00, 4); /* only first 4 byte is key point(inUse of CodecInst in jpuapi) to free the corresponding instance. */
  232. #if !defined(PTHREAD_MUTEX_ROBUST_NP)
  233. #define PTHREAD_MUTEX_T_HANDLE_SIZE 4
  234. jdi_mutexes_base = (vip_base + (instance_pool_size_per_core - PTHREAD_MUTEX_T_HANDLE_SIZE*4));
  235. DPRINTK("[JPUDRV] jpu_free_instances : force to destroy jdi_mutexes_base=%p in userspace \n", jdi_mutexes_base);
  236. if (jdi_mutexes_base) {
  237. int i;
  238. for (i = 0; i < 4; i++) {
  239. memcpy(jdi_mutexes_base, &PTHREAD_MUTEX_T_DESTROY_VALUE, PTHREAD_MUTEX_T_HANDLE_SIZE);
  240. jdi_mutexes_base += PTHREAD_MUTEX_T_HANDLE_SIZE;
  241. }
  242. }
  243. #endif
  244. }
  245. s_jpu_open_ref_count--;
  246. list_del(&vil->list);
  247. kfree(vil);
  248. }
  249. }
  250. return 1;
  251. }
  252. static int jpu_free_buffers(struct file *filp)
  253. {
  254. jpudrv_buffer_pool_t *pool, *n;
  255. jpudrv_buffer_t jb;
  256. DPRINTK("[JPUDRV] jpu_free_buffers\n");
  257. list_for_each_entry_safe(pool, n, &s_jbp_head, list)
  258. {
  259. if (pool->filp == filp) {
  260. jb = pool->jb;
  261. if (jb.base) {
  262. jpu_free_dma_buffer(&jb);
  263. list_del(&pool->list);
  264. kfree(pool);
  265. }
  266. }
  267. }
  268. return 0;
  269. }
  270. static irqreturn_t jpu_irq_handler(int irq, void *dev_id)
  271. {
  272. jpu_drv_context_t* dev = (jpu_drv_context_t *)dev_id;
  273. int i;
  274. u32 flag;
  275. DPRINTK("[JPUDRV][+]%s\n", __func__);
  276. #ifdef JPU_IRQ_CONTROL
  277. disable_irq_nosync(s_jpu_irq);
  278. #endif
  279. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  280. flag = ReadJpuRegister(MJPEG_PIC_STATUS_REG(i));
  281. if (flag != 0) {
  282. break;
  283. }
  284. }
  285. dev->interrupt_reason[i] = flag;
  286. s_interrupt_flag[i] = 1;
  287. DPRINTK("[JPUDRV][%d] INTERRUPT FLAG: %08x, %08x\n", i, dev->interrupt_reason[i], MJPEG_PIC_STATUS_REG(i));
  288. if (dev->async_queue)
  289. kill_fasync(&dev->async_queue, SIGIO, POLL_IN); // notify the interrupt to userspace
  290. #ifndef JPU_IRQ_CONTROL
  291. WriteJpuRegister(MJPEG_PIC_STATUS_REG(i),flag); //clear interrut
  292. #endif
  293. wake_up_interruptible(&s_interrupt_wait_q[i]);
  294. DPRINTK("[JPUDRV][-]%s\n", __func__);
  295. return IRQ_HANDLED;
  296. }
  297. static int jpu_open(struct inode *inode, struct file *filp)
  298. {
  299. DPRINTK("[JPUDRV][+] %s\n", __func__);
  300. pm_runtime_get_sync(s_jpu_clk->dev);
  301. spin_lock(&s_jpu_lock);
  302. s_jpu_drv_context.open_count++;
  303. filp->private_data = (void *)(&s_jpu_drv_context);
  304. spin_unlock(&s_jpu_lock);
  305. DPRINTK("[JPUDRV][-] %s\n", __func__);
  306. return 0;
  307. }
  308. static long jpu_ioctl(struct file *filp, u_int cmd, u_long arg)
  309. {
  310. int ret = 0;
  311. switch (cmd)
  312. {
  313. case JDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY:
  314. {
  315. jpudrv_buffer_pool_t *jbp;
  316. DPRINTK("[JPUDRV][+]JDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  317. if ((ret = down_interruptible(&s_jpu_sem)) == 0) {
  318. jbp = kzalloc(sizeof(jpudrv_buffer_pool_t), GFP_KERNEL);
  319. if (!jbp) {
  320. up(&s_jpu_sem);
  321. return -ENOMEM;
  322. }
  323. ret = copy_from_user(&(jbp->jb), (jpudrv_buffer_t *)arg, sizeof(jpudrv_buffer_t));
  324. if (ret)
  325. {
  326. kfree(jbp);
  327. up(&s_jpu_sem);
  328. return -EFAULT;
  329. }
  330. ret = jpu_alloc_dma_buffer(&(jbp->jb));
  331. if (ret == -1)
  332. {
  333. ret = -ENOMEM;
  334. kfree(jbp);
  335. up(&s_jpu_sem);
  336. break;
  337. }
  338. ret = copy_to_user((void __user *)arg, &(jbp->jb), sizeof(jpudrv_buffer_t));
  339. if (ret)
  340. {
  341. kfree(jbp);
  342. ret = -EFAULT;
  343. up(&s_jpu_sem);
  344. break;
  345. }
  346. jbp->filp = filp;
  347. spin_lock(&s_jpu_lock);
  348. list_add(&jbp->list, &s_jbp_head);
  349. spin_unlock(&s_jpu_lock);
  350. up(&s_jpu_sem);
  351. }
  352. DPRINTK("[JPUDRV][-]JDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  353. }
  354. break;
  355. case JDI_IOCTL_GET_PHYSICAL_MEMORY:
  356. {
  357. jpudrv_buffer_pool_t *jbp = NULL;
  358. void *user_address = NULL;
  359. struct task_struct *my_struct = NULL;
  360. struct mm_struct *mm = NULL;
  361. unsigned long address = 0;
  362. pgd_t *pgd = NULL;
  363. DPRINTK("[JPUDRV][+]JDI_IOCTL_GET_PHYSICAL_MEMORY\n");
  364. if ((ret = down_interruptible(&s_jpu_sem)) == 0) {
  365. jbp = kzalloc(sizeof(jpudrv_buffer_pool_t), GFP_KERNEL);
  366. if (!jbp) {
  367. up(&s_jpu_sem);
  368. return -ENOMEM;
  369. }
  370. ret = copy_from_user(&(jbp->jb), (jpudrv_buffer_t *)arg, sizeof(jpudrv_buffer_t));
  371. if (ret)
  372. {
  373. kfree(jbp);
  374. up(&s_jpu_sem);
  375. return -EFAULT;
  376. }
  377. user_address = (void *)jbp->jb.virt_addr;
  378. my_struct = get_current();
  379. mm = my_struct->mm;
  380. address = (unsigned long)user_address;
  381. pgd = pgd_offset(mm, address);
  382. if (!pgd_none(*pgd) && !pgd_bad(*pgd)) {
  383. p4d_t *p4d = p4d_offset(pgd, address);
  384. pud_t *pud = pud_offset(p4d, address);
  385. if (!pud_none(*pud) && !pud_bad(*pud)) {
  386. pmd_t *pmd = pmd_offset(pud, address);
  387. if (!pmd_none(*pmd) && !pmd_bad(*pmd)) {
  388. pte_t *pte = pte_offset_map(pmd, address);
  389. if (!pte_none(*pte)) {
  390. struct page *pg = pte_page(*pte);
  391. unsigned long phys = page_to_phys(pg);
  392. unsigned long virt = (unsigned long)phys_to_virt(phys);
  393. printk("phy address = %lx, virt = %lx\r\n", phys, virt);
  394. jbp->jb.phys_addr = phys;
  395. jbp->jb.base = virt;
  396. }
  397. pte_unmap(pte);
  398. }
  399. }
  400. }
  401. ret = copy_to_user((void __user *)arg, &(jbp->jb), sizeof(jpudrv_buffer_t));
  402. if (ret)
  403. {
  404. kfree(jbp);
  405. ret = -EFAULT;
  406. up(&s_jpu_sem);
  407. break;
  408. }
  409. kfree(jbp);
  410. up(&s_jpu_sem);
  411. }
  412. DPRINTK("[JPUDRV][-]JDI_IOCTL_GET_PHYSICAL_MEMORY\n");
  413. }
  414. break;
  415. case JDI_IOCTL_FREE_PHYSICALMEMORY:
  416. {
  417. jpudrv_buffer_pool_t *jbp, *n;
  418. jpudrv_buffer_t jb;
  419. DPRINTK("[JPUDRV][+]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  420. if ((ret = down_interruptible(&s_jpu_sem)) == 0) {
  421. ret = copy_from_user(&jb, (jpudrv_buffer_t *)arg, sizeof(jpudrv_buffer_t));
  422. if (ret) {
  423. up(&s_jpu_sem);
  424. return -EACCES;
  425. }
  426. if (jb.base)
  427. jpu_free_dma_buffer(&jb);
  428. spin_lock(&s_jpu_lock);
  429. list_for_each_entry_safe(jbp, n, &s_jbp_head, list) {
  430. if (jbp->jb.base == jb.base) {
  431. list_del(&jbp->list);
  432. kfree(jbp);
  433. break;
  434. }
  435. }
  436. spin_unlock(&s_jpu_lock);
  437. up(&s_jpu_sem);
  438. }
  439. DPRINTK("[JPUDRV][-]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  440. }
  441. break;
  442. case JDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO:
  443. {
  444. #ifdef JPU_SUPPORT_RESERVED_VIDEO_MEMORY
  445. if (s_video_memory.base != 0) {
  446. ret = copy_to_user((void __user *)arg, &s_video_memory, sizeof(jpudrv_buffer_t));
  447. if (ret != 0)
  448. ret = -EFAULT;
  449. } else {
  450. ret = -EFAULT;
  451. }
  452. #endif /* JPU_SUPPORT_RESERVED_VIDEO_MEMORY */
  453. }
  454. break;
  455. case JDI_IOCTL_WAIT_INTERRUPT:
  456. {
  457. jpudrv_intr_info_t info;
  458. struct jpu_drv_context_t *dev = (struct jpu_drv_context_t *)filp->private_data;
  459. u32 instance_no;
  460. DPRINTK("[JPUDRV][+]JDI_IOCTL_WAIT_INTERRUPT\n");
  461. ret = copy_from_user(&info, (jpudrv_intr_info_t *)arg, sizeof(jpudrv_intr_info_t));
  462. if (ret != 0)
  463. return -EFAULT;
  464. instance_no = info.inst_idx;
  465. DPRINTK("[JPUDRV] INSTANCE NO: %d\n", instance_no);
  466. ret = wait_event_interruptible_timeout(s_interrupt_wait_q[instance_no], s_interrupt_flag[instance_no] != 0, msecs_to_jiffies(info.timeout));
  467. if (!ret) {
  468. DPRINTK("[JPUDRV] INSTANCE NO: %d ETIME\n", instance_no);
  469. ret = -ETIME;
  470. break;
  471. }
  472. if (signal_pending(current)) {
  473. ret = -ERESTARTSYS;
  474. DPRINTK("[JPUDRV] INSTANCE NO: %d ERESTARTSYS\n", instance_no);
  475. break;
  476. }
  477. DPRINTK("[JPUDRV] INST(%d) s_interrupt_flag(%d), reason(0x%08x)\n", instance_no, s_interrupt_flag[instance_no], dev->interrupt_reason[instance_no]);
  478. info.intr_reason = dev->interrupt_reason[instance_no];
  479. s_interrupt_flag[instance_no] = 0;
  480. dev->interrupt_reason[instance_no] = 0;
  481. ret = copy_to_user((void __user *)arg, &info, sizeof(jpudrv_intr_info_t));
  482. #ifdef JPU_IRQ_CONTROL
  483. enable_irq(s_jpu_irq);
  484. #endif
  485. DPRINTK("[VPUDRV][-]VDI_IOCTL_WAIT_INTERRUPT\n");
  486. if (ret != 0)
  487. return -EFAULT;
  488. }
  489. break;
  490. case JDI_IOCTL_SET_CLOCK_GATE:
  491. {
  492. u32 clkgate;
  493. if (get_user(clkgate, (u32 __user *) arg))
  494. return -EFAULT;
  495. #ifdef JPU_SUPPORT_CLOCK_CONTROL
  496. if (clkgate)
  497. jpu_clk_enable(s_jpu_clk);
  498. else
  499. jpu_clk_disable(s_jpu_clk);
  500. #endif /* JPU_SUPPORT_CLOCK_CONTROL */
  501. }
  502. break;
  503. case JDI_IOCTL_GET_INSTANCE_POOL:
  504. DPRINTK("[JPUDRV][+]JDI_IOCTL_GET_INSTANCE_POOL\n");
  505. if ((ret = down_interruptible(&s_jpu_sem)) == 0) {
  506. if (s_instance_pool.base != 0) {
  507. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(jpudrv_buffer_t));
  508. } else {
  509. ret = copy_from_user(&s_instance_pool, (jpudrv_buffer_t *)arg, sizeof(jpudrv_buffer_t));
  510. if (ret == 0) {
  511. s_instance_pool.size = PAGE_ALIGN(s_instance_pool.size);
  512. s_instance_pool.base = (unsigned long)vmalloc(s_instance_pool.size);
  513. s_instance_pool.phys_addr = s_instance_pool.base;
  514. if (s_instance_pool.base != 0) {
  515. memset((void *)s_instance_pool.base, 0x0, s_instance_pool.size); /*clearing memory*/
  516. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(jpudrv_buffer_t));
  517. if (ret == 0) {
  518. /* success to get memory for instance pool */
  519. up(&s_jpu_sem);
  520. break;
  521. }
  522. }
  523. ret = -EFAULT;
  524. }
  525. }
  526. up(&s_jpu_sem);
  527. }
  528. DPRINTK("[JPUDRV][-]JDI_IOCTL_GET_INSTANCE_POOL: %s base: %lx, size: %d\n",
  529. (ret==0 ? "OK" : "NG"), s_instance_pool.base, s_instance_pool.size);
  530. break;
  531. case JDI_IOCTL_OPEN_INSTANCE:
  532. {
  533. jpudrv_inst_info_t inst_info;
  534. if (copy_from_user(&inst_info, (jpudrv_inst_info_t *)arg, sizeof(jpudrv_inst_info_t)))
  535. return -EFAULT;
  536. spin_lock(&s_jpu_lock);
  537. s_jpu_open_ref_count++; /* flag just for that jpu is in opened or closed */
  538. inst_info.inst_open_count = s_jpu_open_ref_count;
  539. spin_unlock(&s_jpu_lock);
  540. if (copy_to_user((void __user *)arg, &inst_info, sizeof(jpudrv_inst_info_t))) {
  541. return -EFAULT;
  542. }
  543. DPRINTK("[JPUDRV] JDI_IOCTL_OPEN_INSTANCE inst_idx=%d, s_jpu_open_ref_count=%d, inst_open_count=%d\n",
  544. (int)inst_info.inst_idx, s_jpu_open_ref_count, inst_info.inst_open_count);
  545. }
  546. break;
  547. case JDI_IOCTL_CLOSE_INSTANCE:
  548. {
  549. jpudrv_inst_info_t inst_info;
  550. DPRINTK("[JPUDRV][+]JDI_IOCTL_CLOSE_INSTANCE\n");
  551. if (copy_from_user(&inst_info, (jpudrv_inst_info_t *)arg, sizeof(jpudrv_inst_info_t)))
  552. return -EFAULT;
  553. spin_lock(&s_jpu_lock);
  554. s_jpu_open_ref_count--; /* flag just for that jpu is in opened or closed */
  555. inst_info.inst_open_count = s_jpu_open_ref_count;
  556. spin_unlock(&s_jpu_lock);
  557. if (copy_to_user((void __user *)arg, &inst_info, sizeof(jpudrv_inst_info_t)))
  558. return -EFAULT;
  559. DPRINTK("[JPUDRV] JDI_IOCTL_CLOSE_INSTANCE inst_idx=%d, s_jpu_open_ref_count=%d, inst_open_count=%d\n",
  560. (int)inst_info.inst_idx, s_jpu_open_ref_count, inst_info.inst_open_count);
  561. }
  562. break;
  563. case JDI_IOCTL_GET_INSTANCE_NUM:
  564. {
  565. jpudrv_inst_info_t inst_info;
  566. DPRINTK("[JPUDRV][+]JDI_IOCTL_GET_INSTANCE_NUM\n");
  567. ret = copy_from_user(&inst_info, (jpudrv_inst_info_t *)arg, sizeof(jpudrv_inst_info_t));
  568. if (ret != 0)
  569. break;
  570. spin_lock(&s_jpu_lock);
  571. inst_info.inst_open_count = s_jpu_open_ref_count;
  572. spin_unlock(&s_jpu_lock);
  573. ret = copy_to_user((void __user *)arg, &inst_info, sizeof(jpudrv_inst_info_t));
  574. DPRINTK("[JPUDRV] JDI_IOCTL_GET_INSTANCE_NUM inst_idx=%d, open_count=%d\n", (int)inst_info.inst_idx, inst_info.inst_open_count);
  575. }
  576. break;
  577. case JDI_IOCTL_RESET:
  578. jpu_hw_reset();
  579. break;
  580. case JDI_IOCTL_GET_REGISTER_INFO:
  581. DPRINTK("[JPUDRV][+]JDI_IOCTL_GET_REGISTER_INFO\n");
  582. ret = copy_to_user((void __user *)arg, &s_jpu_register, sizeof(jpudrv_buffer_t));
  583. if (ret != 0)
  584. ret = -EFAULT;
  585. DPRINTK("[JPUDRV][-]JDI_IOCTL_GET_REGISTER_INFO s_jpu_register.phys_addr=0x%lx, s_jpu_register.virt_addr=0x%lx, s_jpu_register.size=%d\n",
  586. s_jpu_register.phys_addr , s_jpu_register.virt_addr, s_jpu_register.size);
  587. break;
  588. case JDI_IOCTL_FLUSH_DCACHE:
  589. {
  590. jpudrv_flush_cache_t cache_info;
  591. //DPRINTK("[JPUDRV][+]JDI_IOCTL_FLUSH_DCACHE\n");
  592. ret = copy_from_user(&cache_info, (jpudrv_flush_cache_t *)arg, sizeof(jpudrv_flush_cache_t));
  593. if (ret != 0)
  594. ret = -EFAULT;
  595. if(cache_info.flag)
  596. starfive_flush_dcache(cache_info.start,cache_info.size);
  597. //DPRINTK("[JPUDRV][-]JDI_IOCTL_FLUSH_DCACHE\n");
  598. break;
  599. }
  600. default:
  601. {
  602. printk(KERN_ERR "No such IOCTL, cmd is %d\n", cmd);
  603. }
  604. break;
  605. }
  606. return ret;
  607. }
  608. static ssize_t jpu_read(struct file *filp, char __user *buf, size_t len, loff_t *ppos)
  609. {
  610. return -1;
  611. }
  612. static ssize_t jpu_write(struct file *filp, const char __user *buf, size_t len, loff_t *ppos)
  613. {
  614. /* DPRINTK("[VPUDRV] vpu_write len=%d\n", (int)len); */
  615. if (!buf) {
  616. printk(KERN_ERR "[VPUDRV] vpu_write buf = NULL error \n");
  617. return -EFAULT;
  618. }
  619. return -1;
  620. }
  621. static int jpu_release(struct inode *inode, struct file *filp)
  622. {
  623. int ret = 0;
  624. u32 open_count;
  625. DPRINTK("[JPUDRV][+] jpu_release\n");
  626. if ((ret = down_interruptible(&s_jpu_sem)) == 0) {
  627. /* found and free the not handled buffer by user applications */
  628. jpu_free_buffers(filp);
  629. /* found and free the not closed instance by user applications */
  630. jpu_free_instances(filp);
  631. DPRINTK("[JPUDRV] open_count: %d\n", s_jpu_drv_context.open_count);
  632. spin_lock(&s_jpu_lock);
  633. s_jpu_drv_context.open_count--;
  634. open_count = s_jpu_drv_context.open_count;
  635. spin_unlock(&s_jpu_lock);
  636. if (open_count == 0) {
  637. if (s_instance_pool.base) {
  638. DPRINTK("[JPUDRV] free instance pool\n");
  639. vfree((const void *)s_instance_pool.base);
  640. s_instance_pool.base = 0;
  641. }
  642. }
  643. }
  644. up(&s_jpu_sem);
  645. DPRINTK("[JPUDRV][-] jpu_release\n");
  646. pm_runtime_put_sync(s_jpu_clk->dev);
  647. return 0;
  648. }
  649. static int jpu_fasync(int fd, struct file *filp, int mode)
  650. {
  651. struct jpu_drv_context_t *dev = (struct jpu_drv_context_t *)filp->private_data;
  652. return fasync_helper(fd, filp, mode, &dev->async_queue);
  653. }
  654. static int jpu_map_to_register(struct file *fp, struct vm_area_struct *vm)
  655. {
  656. unsigned long pfn;
  657. vm->vm_flags |= VM_IO | VM_RESERVED;
  658. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  659. pfn = s_jpu_register.phys_addr >> PAGE_SHIFT;
  660. return remap_pfn_range(vm, vm->vm_start, pfn, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  661. }
  662. static int jpu_map_to_physical_memory(struct file *fp, struct vm_area_struct *vm)
  663. {
  664. vm->vm_flags |= VM_IO | VM_RESERVED;
  665. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  666. return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  667. }
  668. static int jpu_map_to_instance_pool_memory(struct file *fp, struct vm_area_struct *vm)
  669. {
  670. int ret;
  671. long length = vm->vm_end - vm->vm_start;
  672. unsigned long start = vm->vm_start;
  673. char *vmalloc_area_ptr = (char *)s_instance_pool.base;
  674. unsigned long pfn;
  675. vm->vm_flags |= VM_RESERVED;
  676. /* loop over all pages, map it page individually */
  677. while (length > 0) {
  678. pfn = vmalloc_to_pfn(vmalloc_area_ptr);
  679. if ((ret = remap_pfn_range(vm, start, pfn, PAGE_SIZE, PAGE_SHARED)) < 0) {
  680. return ret;
  681. }
  682. start += PAGE_SIZE;
  683. vmalloc_area_ptr += PAGE_SIZE;
  684. length -= PAGE_SIZE;
  685. }
  686. return 0;
  687. }
  688. /*!
  689. * @brief memory map interface for jpu file operation
  690. * @return 0 on success or negative error code on error
  691. */
  692. static int jpu_mmap(struct file *fp, struct vm_area_struct *vm)
  693. {
  694. if (vm->vm_pgoff == 0)
  695. return jpu_map_to_instance_pool_memory(fp, vm);
  696. if (vm->vm_pgoff == (s_jpu_register.phys_addr>>PAGE_SHIFT))
  697. return jpu_map_to_register(fp, vm);
  698. return jpu_map_to_physical_memory(fp, vm);
  699. }
  700. struct file_operations jpu_fops = {
  701. .owner = THIS_MODULE,
  702. .open = jpu_open,
  703. .read = jpu_read,
  704. .write = jpu_write,
  705. .unlocked_ioctl = jpu_ioctl,
  706. .release = jpu_release,
  707. .fasync = jpu_fasync,
  708. .mmap = jpu_mmap,
  709. };
  710. static int jpu_probe(struct platform_device *pdev)
  711. {
  712. int err = 0;
  713. struct resource *res = NULL;
  714. struct device *devices;
  715. #ifdef JPU_SUPPORT_RESERVED_VIDEO_MEMORY
  716. struct resource res_cma;
  717. struct device_node *node;
  718. #endif
  719. int irq = -1;
  720. DPRINTK("[JPUDRV] jpu_probe\n");
  721. if (pdev) {
  722. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  723. }
  724. if (res) {/* if platform driver is implemented */
  725. s_jpu_register.phys_addr = res->start;
  726. s_jpu_register.virt_addr = (unsigned long)ioremap(res->start, res->end - res->start);
  727. s_jpu_register.size = res->end - res->start;
  728. DPRINTK("[JPUDRV] : jpu base address get from platform driver physical base addr==0x%lx, virtual base=0x%lx\n", s_jpu_register.phys_addr , s_jpu_register.virt_addr);
  729. } else {
  730. s_jpu_register.phys_addr = JPU_REG_BASE_ADDR;
  731. s_jpu_register.virt_addr = (unsigned long)ioremap(s_jpu_register.phys_addr, JPU_REG_SIZE);
  732. s_jpu_register.size = JPU_REG_SIZE;
  733. DPRINTK("[JPUDRV] : jpu base address get from defined value physical base addr==0x%lx, virtual base=0x%lx\n", s_jpu_register.phys_addr, s_jpu_register.virt_addr);
  734. }
  735. if (pdev) {
  736. jpu_dev = &pdev->dev;
  737. //jpu_dev->dma_ops = NULL;
  738. dev_info(jpu_dev,"init device.\n");
  739. }
  740. /* get the major number of the character device */
  741. if ((alloc_chrdev_region(&s_jpu_devt, 0, 1, JPU_DEV_NAME)) < 0) {
  742. err = -EBUSY;
  743. printk(KERN_ERR "could not allocate major number\n");
  744. goto ERROR_PROVE_DEVICE;
  745. }
  746. s_jpu_major = MAJOR(s_jpu_devt);
  747. /* initialize the device structure and register the device with the kernel */
  748. cdev_init(&s_jpu_cdev, &jpu_fops);
  749. if ((cdev_add(&s_jpu_cdev, s_jpu_devt, 1)) < 0) {
  750. err = -EBUSY;
  751. printk(KERN_ERR "could not allocate chrdev\n");
  752. goto ERROR_PROVE_DEVICE;
  753. }
  754. s_jpu_class = class_create(THIS_MODULE, JPU_DEV_NAME);
  755. if (IS_ERR(s_jpu_class)) {
  756. dev_err(jpu_dev, "class creat error.\n");
  757. goto ERROR_CRART_CLASS;
  758. }
  759. devices = device_create(s_jpu_class, 0, MKDEV(s_jpu_major, 0),
  760. NULL, JPU_DEV_NAME);
  761. if (IS_ERR(devices)) {
  762. dev_err(jpu_dev, "device creat error.\n");
  763. goto ERROR_CREAT_DEVICE;
  764. }
  765. if (pdev)
  766. s_jpu_clk = jpu_clk_get(pdev);
  767. else
  768. s_jpu_clk = jpu_clk_get(NULL);
  769. if (!s_jpu_clk) {
  770. printk(KERN_ERR "[JPUDRV] : not support clock controller.\n");
  771. }
  772. else {
  773. DPRINTK("[JPUDRV] : get clock controller s_jpu_clk=%p\n", s_jpu_clk);
  774. }
  775. jpu_pmu_enable(s_jpu_clk->dev);
  776. jpu_clk_enable(s_jpu_clk);
  777. reset_control_deassert(s_jpu_clk->resets);
  778. #ifdef JPU_SUPPORT_ISR
  779. #ifdef JPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  780. if(pdev)
  781. irq = platform_get_irq(pdev, 0);
  782. if (irq >= 0) {/* if platform driver is implemented */
  783. s_jpu_irq = irq;
  784. DPRINTK("[JPUDRV] : jpu irq number get from platform driver irq=0x%x\n", s_jpu_irq );
  785. } else {
  786. DPRINTK("[JPUDRV] : jpu irq number get from defined value irq=0x%x\n", s_jpu_irq );
  787. }
  788. #else
  789. DPRINTK("[JPUDRV] : jpu irq number get from defined value irq=0x%x\n", s_jpu_irq);
  790. #endif
  791. err = request_irq(s_jpu_irq, jpu_irq_handler, 0, "JPU_CODEC_IRQ", (void *)(&s_jpu_drv_context));
  792. if (err) {
  793. printk(KERN_ERR "[JPUDRV] : fail to register interrupt handler\n");
  794. goto ERROR_PROVE_DEVICE;
  795. }
  796. #endif
  797. #ifdef JPU_SUPPORT_RESERVED_VIDEO_MEMORY
  798. node = of_parse_phandle(jpu_dev->of_node, "memory-region", 0);
  799. if(node){
  800. dev_info(jpu_dev, "Get mem form memory-region\n");
  801. of_address_to_resource(node, 0, &res_cma);
  802. s_video_memory.size = resource_size(&res_cma);
  803. s_video_memory.phys_addr = res_cma.start;
  804. }else{
  805. dev_info(jpu_dev, "Get mem form reserved memory failed.please check the dts file.\n");
  806. return 0;
  807. }
  808. s_video_memory.base = (unsigned long)ioremap(MEM2SYS(s_video_memory.phys_addr), PAGE_ALIGN(s_video_memory.size));
  809. if (!s_video_memory.base) {
  810. printk(KERN_ERR "[JPUDRV] : fail to remap video memory physical phys_addr=0x%lx, base=0x%lx, size=%d\n", MEM2SYS(s_video_memory.phys_addr), s_video_memory.base, s_video_memory.size);
  811. goto ERROR_PROVE_DEVICE;
  812. }
  813. if (jmem_init(&s_jmem, s_video_memory.phys_addr, s_video_memory.size) < 0) {
  814. printk(KERN_ERR "[JPUDRV] : fail to init vmem system\n");
  815. goto ERROR_PROVE_DEVICE;
  816. }
  817. DPRINTK("[JPUDRV] success to probe jpu device with reserved video memory phys_addr=0x%lx, base=0x%lx\n", s_video_memory.phys_addr, s_video_memory.base);
  818. #else
  819. DPRINTK("[JPUDRV] success to probe jpu device with non reserved video memory\n");
  820. #endif
  821. return 0;
  822. ERROR_CREAT_DEVICE:
  823. class_destroy(s_jpu_class);
  824. ERROR_CRART_CLASS:
  825. cdev_del(&s_jpu_cdev);
  826. ERROR_PROVE_DEVICE:
  827. if (s_jpu_major)
  828. unregister_chrdev_region(s_jpu_major, 1);
  829. if (s_jpu_register.virt_addr)
  830. iounmap((void *)s_jpu_register.virt_addr);
  831. return err;
  832. }
  833. static int jpu_remove(struct platform_device *pdev)
  834. {
  835. DPRINTK("[JPUDRV] jpu_remove\n");
  836. #ifdef JPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  837. if (s_instance_pool.base) {
  838. vfree((const void *)s_instance_pool.base);
  839. s_instance_pool.base = 0;
  840. }
  841. #ifdef JPU_SUPPORT_RESERVED_VIDEO_MEMORY
  842. if (s_video_memory.base) {
  843. iounmap((void *)s_video_memory.base);
  844. s_video_memory.base = 0;
  845. jmem_exit(&s_jmem);
  846. }
  847. #endif
  848. if (s_jpu_major > 0) {
  849. device_destroy(s_jpu_class, MKDEV(s_jpu_major, 0));
  850. class_destroy(s_jpu_class);
  851. cdev_del(&s_jpu_cdev);
  852. unregister_chrdev_region(s_jpu_devt, 1);
  853. s_jpu_major = 0;
  854. }
  855. #ifdef JPU_SUPPORT_ISR
  856. if (s_jpu_irq)
  857. free_irq(s_jpu_irq, &s_jpu_drv_context);
  858. #endif
  859. if (s_jpu_register.virt_addr)
  860. iounmap((void*)s_jpu_register.virt_addr);
  861. jpu_clk_put(s_jpu_clk);
  862. jpu_pmu_disable(&pdev->dev);
  863. #endif /* JPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  864. return 0;
  865. }
  866. #ifdef CONFIG_PM
  867. static int __maybe_unused jpu_runtime_suspend(struct device *dev)
  868. {
  869. reset_control_assert(s_jpu_clk->resets);
  870. jpu_clk_disable(s_jpu_clk);
  871. return 0;
  872. }
  873. static int __maybe_unused jpu_runtime_resume(struct device *dev)
  874. {
  875. jpu_clk_enable(s_jpu_clk);
  876. return reset_control_deassert(s_jpu_clk->resets);
  877. }
  878. #endif /* CONFIG_PM */
  879. #ifdef CONFIG_PM_SLEEP
  880. static int __maybe_unused jpu_suspend(struct device *dev)
  881. {
  882. pm_runtime_force_suspend(dev);
  883. return 0;
  884. }
  885. static int __maybe_unused jpu_resume(struct device *dev)
  886. {
  887. pm_runtime_force_resume(dev);
  888. return 0;
  889. }
  890. #endif /* CONFIG_PM_SLEEP */
  891. static const struct dev_pm_ops cm_jpu_pm_ops = {
  892. SET_RUNTIME_PM_OPS(jpu_runtime_suspend,
  893. jpu_runtime_resume, NULL)
  894. SET_SYSTEM_SLEEP_PM_OPS(jpu_suspend, jpu_resume)
  895. };
  896. #ifdef JPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  897. static const struct of_device_id jpu_of_id_table[] = {
  898. { .compatible = "cm,codaj12-jpu-1" },
  899. { .compatible = "starfive,jpu" },
  900. {}
  901. };
  902. MODULE_DEVICE_TABLE(of, jpu_of_id_table);
  903. static struct platform_driver jpu_driver = {
  904. .driver = {
  905. .name = JPU_PLATFORM_DEVICE_NAME,
  906. .of_match_table = of_match_ptr(jpu_of_id_table),
  907. .pm = &cm_jpu_pm_ops,
  908. },
  909. .probe = jpu_probe,
  910. .remove = jpu_remove,
  911. };
  912. #endif /* JPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  913. static int __init jpu_init(void)
  914. {
  915. int res = 0;
  916. u32 i;
  917. DPRINTK("[JPUDRV] begin jpu_init\n");
  918. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  919. init_waitqueue_head(&s_interrupt_wait_q[i]);
  920. }
  921. s_instance_pool.base = 0;
  922. #ifdef JPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  923. res = platform_driver_register(&jpu_driver);
  924. #else
  925. res = jpu_probe(NULL);
  926. #endif /* JPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  927. DPRINTK("[JPUDRV] end jpu_init result=0x%x\n", res);
  928. return res;
  929. }
  930. static void __exit jpu_exit(void)
  931. {
  932. DPRINTK("[JPUDRV] [+]jpu_exit\n");
  933. #ifdef JPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  934. platform_driver_unregister(&jpu_driver);
  935. #else /* JPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  936. #ifdef JPU_SUPPORT_CLOCK_CONTROL
  937. #else
  938. jpu_clk_disable(s_jpu_clk);
  939. #endif /* JPU_SUPPORT_CLOCK_CONTROL */
  940. jpu_clk_put(s_jpu_clk);
  941. if (s_instance_pool.base) {
  942. vfree((const void *)s_instance_pool.base);
  943. s_instance_pool.base = 0;
  944. }
  945. #ifdef JPU_SUPPORT_RESERVED_VIDEO_MEMORY
  946. if (s_video_memory.base) {
  947. iounmap((void *)s_video_memory.base);
  948. s_video_memory.base = 0;
  949. jmem_exit(&s_jmem);
  950. }
  951. #endif /* JPU_SUPPORT_RESERVED_VIDEO_MEMORY */
  952. if (s_jpu_major > 0) {
  953. device_destroy(s_jpu_class, MKDEV(s_jpu_major, 0));
  954. class_destroy(s_jpu_class);
  955. cdev_del(&s_jpu_cdev);
  956. unregister_chrdev_region(s_jpu_devt, 1);
  957. s_jpu_major = 0;
  958. }
  959. #ifdef JPU_SUPPORT_ISR
  960. if (s_jpu_irq)
  961. free_irq(s_jpu_irq, &s_jpu_drv_context);
  962. #endif /* JPU_SUPPORT_ISR */
  963. if (s_jpu_register.virt_addr) {
  964. iounmap((void *)s_jpu_register.virt_addr);
  965. s_jpu_register.virt_addr = 0x00;
  966. }
  967. #endif /* JPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  968. DPRINTK("[JPUDRV] [-]jpu_exit\n");
  969. return;
  970. }
  971. MODULE_AUTHOR("A customer using C&M JPU, Inc.");
  972. MODULE_DESCRIPTION("JPU linux driver");
  973. MODULE_LICENSE("Dual BSD/GPL");
  974. module_init(jpu_init);
  975. module_exit(jpu_exit);
  976. static int jpu_pmu_enable(struct device *dev)
  977. {
  978. pm_runtime_set_active(dev);
  979. pm_runtime_enable(dev);
  980. return 0;
  981. }
  982. static void jpu_pmu_disable(struct device *dev)
  983. {
  984. pm_runtime_disable(dev);
  985. pm_runtime_set_suspended(dev);
  986. }
  987. #ifndef STARFIVE_JPU_SUPPORT_CLOCK_CONTROL
  988. #define CLK_ENABLE_DATA 1
  989. #define CLK_DISABLE_DATA 0
  990. #define CLK_EN_SHIFT 31
  991. #define CLK_EN_MASK 0x80000000U
  992. #define SAIF_BD_APBS_BASE 0x13020000
  993. #define CODAJ12_CLK_AXI_CTRL 0x108U
  994. #define CODAJ12_CLK_APB_CTRL 0x110U
  995. #define CODAJ12_CLK_CORE_CTRL 0x10cU
  996. #define RSTGEN_SOFTWARE_RESET_ASSERT1 0x2FCU
  997. #define RSTGEN_SOFTWARE_RESET_STATUS1 0x30CU
  998. #define RSTN_AXI_MASK (0x1 << 12)
  999. #define RSTN_CORE_MASK (0x1 << 13)
  1000. #define RSTN_APB_MASK (0x1 << 14)
  1001. static __maybe_unused uint32_t saif_get_reg(
  1002. const volatile void __iomem *addr,
  1003. uint32_t shift, uint32_t mask)
  1004. {
  1005. u32 tmp;
  1006. tmp = readl(addr);
  1007. tmp = (tmp & mask) >> shift;
  1008. return tmp;
  1009. }
  1010. static void saif_set_reg(volatile void __iomem *addr, uint32_t data,
  1011. uint32_t shift, uint32_t mask)
  1012. {
  1013. uint32_t tmp;
  1014. tmp = readl(addr);
  1015. tmp &= ~mask;
  1016. tmp |= (data << shift) & mask;
  1017. writel(tmp, addr);
  1018. }
  1019. static void saif_assert_rst(volatile void __iomem *addr,
  1020. const volatile void __iomem *addr_status, uint32_t mask)
  1021. {
  1022. uint32_t tmp;
  1023. tmp = readl(addr);
  1024. tmp |= mask;
  1025. writel(tmp, addr);
  1026. do {
  1027. tmp = readl(addr_status);
  1028. } while ((tmp & mask) != 0);
  1029. }
  1030. static void saif_clear_rst(volatile void __iomem *addr,
  1031. const volatile void __iomem *addr_status, uint32_t mask)
  1032. {
  1033. uint32_t tmp;
  1034. tmp = readl(addr);
  1035. tmp &= ~mask;
  1036. writel(tmp, addr);
  1037. do {
  1038. tmp = readl(addr_status);
  1039. } while ((tmp & mask) != mask);
  1040. }
  1041. static void jpu_clk_control(jpu_clk_t *clk, bool enable)
  1042. {
  1043. if (enable) {
  1044. /*enable*/
  1045. saif_set_reg(clk->apb_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1046. saif_set_reg(clk->axi_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1047. saif_set_reg(clk->core_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1048. /*clr-reset*/
  1049. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1050. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1051. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->core_clk.rst_mask);
  1052. } else {
  1053. /*assert-reset*/
  1054. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1055. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1056. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->core_clk.rst_mask);
  1057. /*disable*/
  1058. saif_set_reg(clk->apb_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1059. saif_set_reg(clk->axi_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1060. saif_set_reg(clk->core_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1061. }
  1062. }
  1063. static void jpu_clk_reset(jpu_clk_t *clk)
  1064. {
  1065. /*assert-reset*/
  1066. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1067. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1068. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->core_clk.rst_mask);
  1069. /*clr-reset*/
  1070. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1071. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1072. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->core_clk.rst_mask);
  1073. }
  1074. int jpu_hw_reset(void)
  1075. {
  1076. if (!s_jpu_clk)
  1077. return -1;
  1078. jpu_clk_reset(s_jpu_clk);
  1079. DPRINTK("[VPUDRV] reset vpu hardware. \n");
  1080. return 0;
  1081. }
  1082. static int jpu_of_clk_get(struct platform_device *pdev, jpu_clk_t *jpu_clk)
  1083. {
  1084. if (!pdev)
  1085. return -ENXIO;
  1086. jpu_clk->clkgen = ioremap(SAIF_BD_APBS_BASE, 0x400);
  1087. if (IS_ERR(jpu_clk->clkgen)) {
  1088. dev_err(&pdev->dev, "ioremap clkgen failed.\n");
  1089. return PTR_ERR(jpu_clk->clkgen);
  1090. }
  1091. /* clkgen define */
  1092. jpu_clk->axi_clk.en_ctrl = jpu_clk->clkgen + CODAJ12_CLK_AXI_CTRL;
  1093. jpu_clk->apb_clk.en_ctrl = jpu_clk->clkgen + CODAJ12_CLK_APB_CTRL;
  1094. jpu_clk->core_clk.en_ctrl = jpu_clk->clkgen + CODAJ12_CLK_CORE_CTRL;
  1095. jpu_clk->en_mask = CLK_EN_MASK;
  1096. jpu_clk->en_shift = CLK_EN_SHIFT;
  1097. /* rstgen define */
  1098. jpu_clk->rst_ctrl = jpu_clk->clkgen + RSTGEN_SOFTWARE_RESET_ASSERT1;
  1099. jpu_clk->rst_status = jpu_clk->clkgen + RSTGEN_SOFTWARE_RESET_STATUS1;
  1100. jpu_clk->axi_clk.rst_mask = RSTN_AXI_MASK;
  1101. jpu_clk->apb_clk.rst_mask = RSTN_APB_MASK;
  1102. jpu_clk->core_clk.rst_mask = RSTN_CORE_MASK;
  1103. return 0;
  1104. }
  1105. static jpu_clk_t *jpu_clk_get(struct platform_device *pdev)
  1106. {
  1107. jpu_clk_t *jpu_clk;
  1108. jpu_clk = devm_kzalloc(&pdev->dev, sizeof(*jpu_clk), GFP_KERNEL);
  1109. if (!jpu_clk)
  1110. return NULL;
  1111. if (jpu_of_clk_get(pdev, jpu_clk))
  1112. goto err_get_clk;
  1113. return jpu_clk;
  1114. err_get_clk:
  1115. devm_kfree(&pdev->dev, jpu_clk);
  1116. return NULL;
  1117. }
  1118. static void jpu_clk_put(jpu_clk_t *clk)
  1119. {
  1120. if (clk->clkgen) {
  1121. iounmap(clk->clkgen);
  1122. clk->clkgen = NULL;
  1123. }
  1124. }
  1125. static int jpu_clk_enable(jpu_clk_t *clk)
  1126. {
  1127. if (clk == NULL || IS_ERR(clk))
  1128. return -1;
  1129. jpu_pmu_enable(clk->dev);
  1130. jpu_clk_control(clk, true);
  1131. DPRINTK("[VPUDRV] vpu_clk_enable\n");
  1132. return 0;
  1133. }
  1134. static void jpu_clk_disable(jpu_clk_t *clk)
  1135. {
  1136. if (clk == NULL || IS_ERR(clk))
  1137. return;
  1138. jpu_clk_control(clk, false);
  1139. jpu_pmu_disable(clk->dev);
  1140. DPRINTK("[VPUDRV] vpu_clk_disable\n");
  1141. }
  1142. #else /* STARFIVE_JPU_SUPPORT_CLOCK_CONTROL */
  1143. static int jpu_hw_reset(void)
  1144. {
  1145. return reset_control_reset(s_jpu_clk->resets);
  1146. }
  1147. static int jpu_of_clk_get(struct platform_device *pdev, jpu_clk_t *jpu_clk)
  1148. {
  1149. struct device *dev = &pdev->dev;
  1150. int ret;
  1151. jpu_clk->dev = dev;
  1152. jpu_clk->clks = jpu_clks;
  1153. jpu_clk->nr_clks = ARRAY_SIZE(jpu_clks);
  1154. jpu_clk->resets = devm_reset_control_array_get_shared(dev);
  1155. if (IS_ERR(jpu_clk->resets)) {
  1156. ret = PTR_ERR(jpu_clk->resets);
  1157. dev_err(dev, "faied to get jpu reset controls\n");
  1158. }
  1159. ret = devm_clk_bulk_get(dev, jpu_clk->nr_clks, jpu_clk->clks);
  1160. if (ret)
  1161. dev_err(dev, "faied to get jpu clk controls\n");
  1162. return 0;
  1163. }
  1164. static jpu_clk_t *jpu_clk_get(struct platform_device *pdev)
  1165. {
  1166. jpu_clk_t *jpu_clk;
  1167. if (!pdev)
  1168. return NULL;
  1169. jpu_clk = devm_kzalloc(&pdev->dev, sizeof(*jpu_clk), GFP_KERNEL);
  1170. if (!jpu_clk)
  1171. return NULL;
  1172. if (jpu_of_clk_get(pdev, jpu_clk))
  1173. goto err_of_clk_get;
  1174. return jpu_clk;
  1175. err_of_clk_get:
  1176. devm_kfree(&pdev->dev, jpu_clk);
  1177. return NULL;
  1178. }
  1179. static void jpu_clk_put(jpu_clk_t *clk)
  1180. {
  1181. clk_bulk_put(clk->nr_clks, clk->clks);
  1182. }
  1183. static int jpu_clk_enable(jpu_clk_t *clk)
  1184. {
  1185. int ret;
  1186. ret = clk_bulk_prepare_enable(clk->nr_clks, clk->clks);
  1187. if (ret)
  1188. dev_err(clk->dev, "enable clk error.\n");
  1189. DPRINTK("[VPUDRV] jpu_clk_enable\n");
  1190. return ret;
  1191. }
  1192. static void jpu_clk_disable(jpu_clk_t *clk)
  1193. {
  1194. clk_bulk_disable_unprepare(clk->nr_clks, clk->clks);
  1195. }
  1196. #endif /* STARFIVE_JPU_SUPPORT_CLOCK_CONTROL */