stf_isp_til_rdma.h 23 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stf_isp_til_rdma.h
  4. * @author StarFive Isp Team
  5. * @version V1.0
  6. * @date 12/14/2019
  7. * @brief
  8. ******************************************************************************
  9. * @copy
  10. *
  11. * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  12. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  13. * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
  14. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  15. * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  16. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  17. *
  18. * Copyright (C) 2019 - 2022 StarFive Technology Co., Ltd.
  19. */
  20. #ifndef __STF_ISP_TIL_RDMA_H__
  21. #define __STF_ISP_TIL_RDMA_H__
  22. #include "registers/stf_isp_rdma.h"
  23. /* add tiling input/output image registers structure */
  24. typedef enum _EN_TIL_MODE {
  25. EN_TIL_MODE_NULL = 0,
  26. EN_TIL_MODE_1_READ,
  27. EN_TIL_MODE_1_WRITE,
  28. EN_TIL_MODE_MAX,
  29. } EN_TIL_MODE, *PEN_TIL_MODE;
  30. typedef enum _EN_TIL_IMG_TYPE {
  31. EN_TIL_IMG_TYPE_BAYER = 0,
  32. EN_TIL_IMG_TYPE_RGB,
  33. EN_TIL_IMG_TYPE_YUV,
  34. EN_TIL_IMG_TYPE_MAX,
  35. } EN_TIL_IMG_TYPE, *PEN_TIL_IMG_TYPE;
  36. typedef enum _EN_TIL_FORMAT {
  37. EN_TIL_FMT_RAW10_6PIX_1QW = 0, //0 : RAW10 bit (6 pixels per 1QW) QW= 64bit word, msb 4bit no use.
  38. EN_TIL_FMT_RAW12_5PIX_1QW, //1 : RAW12 bit (5 pixels per 1QW), msb 4bit no use.
  39. EN_TIL_FMT_YUV420_SEMI, //2 : YUV semi-planar 8bit: Y plane, UV plane 4:2:0 JPEG/JFIF progressive mode using the averaging value of the 4 UV points between horizontal and vertical.
  40. EN_TIL_FMT_RAW10_32PIX_5QW, //3 : Optional fully packed RAW10 (320 bits = 32 pixels = 5QW), no redundant bit.
  41. EN_TIL_FMT_RAW12_16PIX_3QW, //4 : Optional fully packed RAW12 (192 bits = 16 pixels = 3QW), no redundant bit.
  42. EN_TIL_FMT_YUV420_SEMI_HOR_AVG, //5 : YUV semi-planar 8bit: Y plane, UV plane 4:2:0 mode using the averaging value of the 2 UV points between the horizontal direction.
  43. EN_TIL_FMT_YUV420_SEMI_1ST_EVEN,//6 : YUV semi-planar 8bit: Y plane, UV plane 4:2:0 mode using the first position of the even horizontal with no averaging value.
  44. EN_TIL_FMT_RAW_FLEX, //7 : RAW flexible bit whose bit number is less than 25 bits with no gap package. The bit number is specified in register 0x0B38 bit[24:20](Read) and bit[8:4](Write).
  45. EN_TIL_FMT_MAX
  46. } EN_TIL_FORMAT, *PEN_TIL_FORMAT;
  47. typedef enum _EN_TIL_RAW_10_MODE {
  48. EN_TIL_RAW_10_MODE_6PIX_1QW = 0,//0 : RAW10 bit (6 pixels per 1QW) QW= 64bit word, msb 4bit no use.
  49. EN_TIL_RAW_10_MODE_3PIX_1DW, //1 : RAW10bit format is changed to IMG ISP RAW 10 bit format (IMG 3 pack in a DW).
  50. EN_TIL_RAW_10_MODE_MAX
  51. } EN_TIL_RAW_10_MODE, *PEN_TIL_RAW_10_MODE;
  52. typedef enum _EN_TIL_YUV_BITMODE {
  53. EN_TIL_YUVBIT_8BIT = 0,
  54. EN_TIL_YUVBIT_10BIT,
  55. } EN_TIL_YUV_BITMODE, *PEN_TIL_YUV_BITMODE;
  56. typedef enum _EN_RD_UV_LINE_BUF {
  57. EN_RD_UV_LINE_BUF_ENABLE = 0, //0 : enable the UV line buffer function. (no UV reload for odd lines).
  58. EN_RD_UV_LINE_BUF_DISABLE, //1 : Disable the UV line buffer function when UV AXI READ controller reads the UV data form DRAM.
  59. EN_RD_UV_LINE_BUF_MAX
  60. } EN_RD_UV_LINE_BUF, *PEN_RD_UV_LINE_BUF;
  61. typedef enum _EN_TIL_FLEX_BIT {
  62. EN_TIL_FLEX_BIT_RAW_8BIT = 0,
  63. EN_TIL_FLEX_BIT_RAW_10BIT,
  64. EN_TIL_FLEX_BIT_RAW_12BIT,
  65. EN_TIL_FLEX_BIT_RAW_14BIT,
  66. EN_TIL_FLEX_BIT_RGB_8BIT,
  67. EN_TIL_FLEX_BIT_RGB_10BIT,
  68. EN_TIL_FLEX_BIT_YUV_8BIT,
  69. EN_TIL_FLEX_BIT_YUV_10BIT,
  70. EN_TIL_FLEX_BIT_MAX,
  71. } EN_TIL_FLEX_BIT, *PEN_TIL_FLEX_BIT;
  72. typedef enum _EN_TIL_PATH {
  73. EN_TIL_PATH_BF_DBC = 0, //0 : RAW 10 bits, only for tiling read.
  74. EN_TIL_PATH_BF_CFA, //1 : RGB 10 bits.
  75. EN_TIL_PATH_BF_SHRP, //2 : YUV 10 bits.
  76. EN_TIL_PATH_BF_SCALE_OUT, //3 : YUV 10 bits, only for tiling write.
  77. EN_TIL_PATH_MAX,
  78. } EN_TIL_PATH, *PEN_TIL_PATH;
  79. typedef enum _EN_TIL_READ {
  80. EN_TIL_READ_DIS = 0, // 0 : Disable the read function of the ITI interface from DRAM buffer.
  81. EN_TIL_READ_EN, // 1 : Enable the read function of the ITI interface from DRAM buffer.
  82. EN_TIL_READ_MAX
  83. } EN_TIL_READ, *PEN_TIL_READ;
  84. typedef enum _EN_TIL_WRITE {
  85. EN_TIL_WRITE_DIS = 0, // 0 : Disable the write function of the ITI interface into DRAM buffer.
  86. EN_TIL_WRITE_EN, // 1 : Enable the write function of the ITI interface into DRAM buffer.
  87. EN_TIL_WRITE_MAX
  88. } EN_TIL_WRITE, *PEN_TIL_WRITE;
  89. typedef enum _EN_TIL_LOOPBACK {
  90. EN_TIL_LOOPBACK_DIS = 0, // 0 : Disable the loop back self test where the write AXI controller obtains the input data from the AXI read controller.
  91. EN_TIL_LOOPBACK_EN, // 1 : Enable the loop back self test where the write AXI controller obtains the input data from the AXI read controller.
  92. EN_TIL_LOOPBACK_MAX
  93. } EN_TIL_LOOPBACK, *PEN_TIL_LOOPBACK;
  94. typedef enum _EN_TIL_MOVE_DRAM_DATA {
  95. EN_TIL_MOVE_DRAM_DATA_DIS = 0, // 0 : Disable the move data function from the reading address to the writing address. (move data directly from read to write, can be used for copying data).
  96. EN_TIL_MOVE_DRAM_DATA_EN, // 1 : Enable the move data function from the reading address to the writing address. (move data directly from read to write, can be used for copying data).
  97. EN_TIL_MOVE_DRAM_DATA_MAX
  98. } EN_TIL_MOVE_DRAM_DATA, *PEN_TIL_MOVE_DRAM_DATA;
  99. typedef enum _EN_TIL_RVI {
  100. EN_TIL_RVI_DEPENDENT = 0, // 0 : Disable the independent READ RVI signal function under the normal DRAM read mode.
  101. EN_TIL_RVI_INDEPENDENT, // 1 : Enable the independent READ RVI signal function under the normal DRAM read mode.
  102. EN_TIL_RVI_MAX
  103. } EN_TIL_RD_RVI, *PEN_TIL_RD_RVI;
  104. typedef enum _EN_TIL_YUV420_FMT {
  105. EN_TIL_YUV420_FMT_12 = 0, // 0: DRAM data format for UV (YCbCr 420 NV12).
  106. EN_TIL_YUV420_FMT_21, // 1: DRAM data format for VU (YCrCb 420 NV21).
  107. EN_TIL_YUV420_FMT_MAX
  108. } EN_TIL_YUV420_FMT, *PEN_TIL_YUV420_FMT;
  109. typedef enum _EN_TIL_SYMBOL {
  110. EN_TIL_SYMBOL_R = 0,
  111. EN_TIL_SYMBOL_GR,
  112. EN_TIL_SYMBOL_GB,
  113. EN_TIL_SYMBOL_B,
  114. } EN_TIL_SYMBOL, *PEN_TIL_SYMBOL;
  115. typedef struct _ST_TIL_ALL_BUSY_STATUS {
  116. STF_U8 u8IspIdx;
  117. STF_U32 u32BusyStatus;
  118. } ST_TIL_ALL_BUSY_STATUS, *PST_TIL_ALL_BUSY_STATUS;
  119. typedef struct _ST_TIL_BUSY_STATUS {
  120. STF_U8 u8IspIdx;
  121. STF_BOOL8 bBusyStatus;
  122. } ST_TIL_BUSY_STATUS, *PST_TIL_BUSY_STATUS;
  123. typedef struct _ST_TIL_1_CFG_REG {
  124. //-------------------------------------------------------------------------
  125. REG_ITIPDFR Til_1_DataFormat; // 0x0B38, ITI package data format register.
  126. REG_ITIDPSR Til_1_PathSelect; // 0x0B48, ISP tiling interface data path select register.
  127. //-------------------------------------------------------------------------
  128. } ST_TIL_1_CFG_REG, *PST_TIL_1_CFG_REG;
  129. #define ST_TIL_1_CFG_REG_SIZE (sizeof(ST_TIL_1_CFG_REG))
  130. #define ST_TIL_1_CFG_REG_LEN (ST_TIL_1_CFG_REG_SIZE / sizeof(STF_U32))
  131. typedef struct _ST_TIL_1_RD_REG {
  132. //-------------------------------------------------------------------------
  133. REG_ITIIWSR Til_1_WindowSize; // 0x0B20, ITI image window size register.
  134. #if defined(V4L2_DRIVER)
  135. #else
  136. REG_ITIDRYSAR Til_1_ReadYAddr; // 0x0B30, ITI DRAM read Y start address register, 8-byte alignment.
  137. REG_ITIDRUSAR Til_1_ReadUvAddr; // 0x0B34, ITI DRAM read UV start address register, 8-byte alignment.
  138. #endif //#if defined(V4L2_DRIVER)
  139. REG_ITIDRLSR Til_1_ReadStride; // 0x0B3C, ITI DRAM read line stride register.
  140. REG_ITIDPSR Til_1_PathSelect; // 0x0B48, ISP tiling interface data path select register.
  141. REG_ITIPDFR Til_1_DataFormat; // 0x0B38, ITI package data format register.
  142. REG_ITIAIR Til_1_AxiId; // 0x0B44, ISP tiling interface AXI ID register.
  143. //-------------------------------------------------------------------------
  144. } ST_TIL_1_RD_REG, *PST_TIL_1_RD_REG;
  145. #define ST_TIL_1_RD_REG_SIZE (sizeof(ST_TIL_1_RD_REG))
  146. #define ST_TIL_1_RD_REG_LEN (ST_TIL_1_RD_REG_SIZE / sizeof(STF_U32))
  147. typedef struct _ST_TIL_1_WR_REG {
  148. //-------------------------------------------------------------------------
  149. REG_ITIIWSR Til_1_WindowSize; // 0x0B20, ITI image window size register.
  150. #if defined(V4L2_DRIVER)
  151. #else
  152. REG_ITIDWYSAR Til_1_WriteYAddr; // 0x0B28, ITI DRAM write Y start address register, 8-byte alignment.
  153. REG_ITIDWUSAR Til_1_WriteUvAddr;// 0x0B2C, ITI DRAM write UV start address register, 8-byte alignment.
  154. #endif //#if defined(V4L2_DRIVER)
  155. REG_ITIDWLSR Til_1_WriteStride; // 0x0B24, ITI DRAM write line stride register, 8-byte alignment.
  156. REG_ITIDPSR Til_1_PathSelect; // 0x0B48, ISP tiling interface data path select register.
  157. REG_ITIPDFR Til_1_DataFormat; // 0x0B38, ITI package data format register.
  158. REG_ITIAIR Til_1_AxiId; // 0x0B44, ISP tiling interface AXI ID register.
  159. //-------------------------------------------------------------------------
  160. } ST_TIL_1_WR_REG, *PST_TIL_1_WR_REG;
  161. #define ST_TIL_1_WR_REG_SIZE (sizeof(ST_TIL_1_WR_REG))
  162. #define ST_TIL_1_WR_REG_LEN (ST_TIL_1_WR_REG_SIZE / sizeof(STF_U32))
  163. typedef struct _ST_TIL_1_WS_REG {
  164. //-------------------------------------------------------------------------
  165. REG_ITIIWSR Til_1_WindowSize; // 0x0B20, ITI image window size register.
  166. //-------------------------------------------------------------------------
  167. } ST_TIL_1_WS_REG, *PST_TIL_1_WS_REG;
  168. #define ST_TIL_1_WS_REG_SIZE (sizeof(ST_TIL_1_WS_REG))
  169. #define ST_TIL_1_WS_REG_LEN (ST_TIL_1_WS_REG_SIZE / sizeof(STF_U32))
  170. typedef struct _ST_TIL_1_WR_SD_REG {
  171. //-------------------------------------------------------------------------
  172. REG_ITIDWLSR Til_1_WriteStride; // 0x0B24, ITI DRAM write line stride register, 8-byte alignment.
  173. //-------------------------------------------------------------------------
  174. } ST_TIL_1_WR_SD_REG, *PST_TIL_1_WR_SD_REG;
  175. #define ST_TIL_1_WR_SD_REG_SIZE (sizeof(ST_TIL_1_WR_SD_REG))
  176. #define ST_TIL_1_WR_SD_REG_LEN (ST_TIL_1_WR_SD_REG_SIZE / sizeof(STF_U32))
  177. typedef struct _ST_TIL_1_WR_ADDR_REG {
  178. //-------------------------------------------------------------------------
  179. REG_ITIDWYSAR Til_1_WriteYAddr; // 0x0B28, ITI DRAM write Y start address register, 8-byte alignment.
  180. REG_ITIDWUSAR Til_1_WriteUvAddr;// 0x0B2C, ITI DRAM write UV start address register, 8-byte alignment.
  181. //-------------------------------------------------------------------------
  182. } ST_TIL_1_WR_ADDR_REG, *PST_TIL_1_WR_BUF_REG;
  183. #define ST_TIL_1_WR_ADDR_REG_SIZE (sizeof(ST_TIL_1_WR_ADDR_REG))
  184. #define ST_TIL_1_WR_ADDR_REG_LEN (ST_TIL_1_WR_ADDR_REG_SIZE / sizeof(STF_U32))
  185. typedef struct _ST_TIL_1_RD_ADDR_REG {
  186. //-------------------------------------------------------------------------
  187. REG_ITIDRYSAR Til_1_ReadYAddr; // 0x0B30, ITI DRAM read Y start address register, 8-byte alignment.
  188. REG_ITIDRUSAR Til_1_ReadUvAddr; // 0x0B34, ITI DRAM read UV start address register, 8-byte alignment.
  189. //-------------------------------------------------------------------------
  190. } ST_TIL_1_RD_ADDR_REG, *PST_TIL_1_RD_ADDR_REG;
  191. #define ST_TIL_1_RD_ADDR_REG_SIZE (sizeof(ST_TIL_1_RD_ADDR_REG))
  192. #define ST_TIL_1_RD_ADDR_REG_LEN (ST_TIL_1_RD_ADDR_REG_SIZE / sizeof(STF_U32))
  193. typedef struct _ST_TIL_1_PDF_REG {
  194. //-------------------------------------------------------------------------
  195. REG_ITIPDFR Til_1_DataFormat; // 0x0B38, ITI package data format register.
  196. //-------------------------------------------------------------------------
  197. } ST_TIL_1_PDF_REG, *PST_TIL_1_PDF_REG;
  198. #define ST_TIL_1_PDF_REG_SIZE (sizeof(ST_TIL_1_PDF_REG))
  199. #define ST_TIL_1_PDF_REG_LEN (ST_TIL_1_PDF_REG_SIZE / sizeof(STF_U32))
  200. typedef struct _ST_TIL_1_RD_SD_REG {
  201. //-------------------------------------------------------------------------
  202. REG_ITIDRLSR Til_1_ReadStride; // 0x0B3C, ITI DRAM read line stride register.
  203. //-------------------------------------------------------------------------
  204. } ST_TIL_1_RD_SD_REG, *PST_TIL_1_RD_SD_REG;
  205. #define ST_TIL_1_RD_SD_REG_SIZE (sizeof(ST_TIL_1_RD_SD_REG))
  206. #define ST_TIL_1_RD_SD_REG_LEN (ST_TIL_1_RD_SD_REG_SIZE / sizeof(STF_U32))
  207. typedef struct _ST_TIL_1_BS_REG {
  208. //-------------------------------------------------------------------------
  209. REG_ITIBSR Til_1_BusyStatus; // 0x0B40, ISP tiling interface BUSY status register.
  210. //-------------------------------------------------------------------------
  211. } ST_TIL_1_BS_REG, *PST_TIL_1_BS_REG;
  212. #define ST_TIL_1_BS_REG_SIZE (sizeof(ST_TIL_1_BS_REG))
  213. #define ST_TIL_1_BS_REG_LEN (ST_TIL_1_BS_REG_SIZE / sizeof(STF_U32))
  214. typedef struct _ST_TIL_1_AXI_REG {
  215. //-------------------------------------------------------------------------
  216. REG_ITIAIR Til_1_AxiId; // 0x0B44, ISP tiling interface AXI ID register.
  217. //-------------------------------------------------------------------------
  218. } ST_TIL_1_AXI_REG, *PST_TIL_1_AXI_REG;
  219. #define ST_TIL_1_AXI_REG_SIZE (sizeof(ST_TIL_1_AXI_REG))
  220. #define ST_TIL_1_AXI_REG_LEN (ST_TIL_1_AXI_REG_SIZE / sizeof(STF_U32))
  221. typedef struct _ST_TIL_1_DPS_REG {
  222. //-------------------------------------------------------------------------
  223. REG_ITIDPSR Til_1_PathSelect; // 0x0B48, ISP tiling interface data path select register.
  224. //-------------------------------------------------------------------------
  225. } ST_TIL_1_DPS_REG, *PST_TIL_1_DPS_REG;
  226. #define ST_TIL_1_DPS_REG_SIZE (sizeof(ST_TIL_1_DPS_REG))
  227. #define ST_TIL_1_DPS_REG_LEN (ST_TIL_1_DPS_REG_SIZE / sizeof(STF_U32))
  228. typedef struct _ST_TIL_REG {
  229. //-------------------------------------------------------------------------
  230. REG_ITIIWSR Til_1_WindowSize; // 0x0B20, ITI image window size register.
  231. REG_ITIDWLSR Til_1_WriteStride; // 0x0B24, ITI DRAM write line stride register, 8-byte alignment.
  232. #if defined(V4L2_DRIVER)
  233. #else
  234. REG_ITIDWYSAR Til_1_WriteYAddr; // 0x0B28, ITI DRAM write Y start address register, 8-byte alignment.
  235. REG_ITIDWUSAR Til_1_WriteUvAddr;// 0x0B2C, ITI DRAM write UV start address register, 8-byte alignment.
  236. #endif //#if defined(V4L2_DRIVER)
  237. #if defined(V4L2_DRIVER)
  238. #else
  239. REG_ITIDRYSAR Til_1_ReadYAddr; // 0x0B30, ITI DRAM read Y start address register, 8-byte alignment.
  240. REG_ITIDRUSAR Til_1_ReadUvAddr; // 0x0B34, ITI DRAM read UV start address register, 8-byte alignment.
  241. #endif //#if defined(V4L2_DRIVER)
  242. REG_ITIPDFR Til_1_DataFormat; // 0x0B38, ITI package data format register.
  243. REG_ITIDRLSR Til_1_ReadStride; // 0x0B3C, ITI DRAM read line stride register.
  244. #if defined(V4L2_DRIVER)
  245. #else
  246. REG_ITIBSR Til_1_BusyStatus; // 0x0B40, ISP tiling interface BUSY status register.
  247. #endif //#if defined(V4L2_DRIVER)
  248. REG_ITIAIR Til_1_AxiId; // 0x0B44, ISP tiling interface AXI ID register.
  249. REG_ITIDPSR Til_1_PathSelect; // 0x0B48, ISP tiling interface data path select register.
  250. //-------------------------------------------------------------------------
  251. } ST_TIL_REG, *PST_TIL_REG;
  252. #define ST_TIL_REG_SIZE (sizeof(ST_TIL_REG))
  253. #define ST_TIL_REG_LEN (ST_TIL_REG_SIZE / sizeof(STF_U32))
  254. #pragma pack(push, 8)
  255. typedef struct _ST_TIL_RDMA {
  256. #if defined(SUPPORT_RDMA_FEATURE)
  257. ST_RDMA_CMD stRdmaStartCmd __attribute__ ((aligned (8)));
  258. #endif //SUPPORT_RDMA_FEATURE
  259. ST_TIL_1_WS_REG stTil_1_WSReg __attribute__ ((aligned (8)));
  260. #if defined(SUPPORT_RDMA_FEATURE)
  261. ST_RDMA_CMD stRdmaTil_1_WrSdCmd __attribute__ ((aligned (8)));
  262. #endif //SUPPORT_RDMA_FEATURE
  263. ST_TIL_1_WR_SD_REG stTil_1_WrSdReg __attribute__ ((aligned (8)));
  264. #if defined(V4L2_DRIVER)
  265. #else
  266. #if defined(SUPPORT_RDMA_FEATURE)
  267. ST_RDMA_CMD stRdmaTil_1_WrAddrCmd __attribute__ ((aligned (8)));
  268. #endif //SUPPORT_RDMA_FEATURE
  269. ST_TIL_1_WR_ADDR_REG stTil_1_WrAddrReg __attribute__ ((aligned (8)));
  270. #endif //#if defined(V4L2_DRIVER)
  271. #if defined(V4L2_DRIVER)
  272. #else
  273. #if defined(SUPPORT_RDMA_FEATURE)
  274. ST_RDMA_CMD stRdmaTil_1_RdAddrCmd __attribute__ ((aligned (8)));
  275. #endif //SUPPORT_RDMA_FEATURE
  276. ST_TIL_1_RD_ADDR_REG stTil_1_RdAddrReg __attribute__ ((aligned (8)));
  277. #endif //#if defined(V4L2_DRIVER)
  278. #if defined(SUPPORT_RDMA_FEATURE)
  279. ST_RDMA_CMD stRdmaTil_1_PDFCmd __attribute__ ((aligned (8)));
  280. #endif //SUPPORT_RDMA_FEATURE
  281. ST_TIL_1_PDF_REG stTil_1_PDFReg __attribute__ ((aligned (8)));
  282. #if defined(SUPPORT_RDMA_FEATURE)
  283. ST_RDMA_CMD stRdmaTil_1_RdSdCmd __attribute__ ((aligned (8)));
  284. #endif //SUPPORT_RDMA_FEATURE
  285. ST_TIL_1_RD_SD_REG stTil_1_RdSdReg __attribute__ ((aligned (8)));
  286. #if defined(V4L2_DRIVER)
  287. #else
  288. #if defined(SUPPORT_RDMA_FEATURE)
  289. ST_RDMA_CMD stRdmaTil_1_BSCmd __attribute__ ((aligned (8)));
  290. #endif //SUPPORT_RDMA_FEATURE
  291. ST_TIL_1_BS_REG stTil_1_BSReg __attribute__ ((aligned (8)));
  292. #endif //#if defined(V4L2_DRIVER)
  293. #if defined(SUPPORT_RDMA_FEATURE)
  294. ST_RDMA_CMD stRdmaTil_1_AxiCmd __attribute__ ((aligned (8)));
  295. #endif //SUPPORT_RDMA_FEATURE
  296. ST_TIL_1_AXI_REG stTil_1_AxiReg __attribute__ ((aligned (8)));
  297. #if defined(SUPPORT_RDMA_FEATURE)
  298. ST_RDMA_CMD stRdmaTil_1_DPSCmd __attribute__ ((aligned (8)));
  299. #endif //SUPPORT_RDMA_FEATURE
  300. ST_TIL_1_DPS_REG stTil_1_DPSReg __attribute__ ((aligned (8)));
  301. #if defined(SUPPORT_RDMA_FEATURE)
  302. ST_RDMA_CMD stRdmaEndCmd __attribute__ ((aligned (8)));
  303. #endif //SUPPORT_RDMA_FEATURE
  304. } ST_TIL_RDMA, *PST_TIL_RDMA;
  305. #define ST_TIL_RDMA_SIZE (sizeof(ST_TIL_RDMA))
  306. #define ST_TIL_RDMA_LEN (ST_TIL_RDMA_SIZE / (sizeof(STF_U32) * 2))
  307. #define ST_TIL_1_WS_RDMA_SIZE (sizeof(ST_RDMA_CMD) + (((sizeof(ST_TIL_1_WS_REG) + 7) / 8) * 8))
  308. #define ST_TIL_1_WS_RDMA_LEN (ST_TIL_1_WS_RDMA_SIZE / (sizeof(STF_U32) * 2))
  309. #define ST_TIL_1_WR_SD_RDMA_SIZE (sizeof(ST_RDMA_CMD) + (((sizeof(ST_TIL_1_WR_SD_REG) + 7) / 8) * 8))
  310. #define ST_TIL_1_WR_SD_RDMA_LEN (ST_TIL_1_WR_SD_RDMA_SIZE / (sizeof(STF_U32) * 2))
  311. #define ST_TIL_1_WR_ADDR_RDMA_SIZE (sizeof(ST_RDMA_CMD) + (((sizeof(ST_TIL_1_WR_ADDR_REG) + 7) / 8) * 8))
  312. #define ST_TIL_1_WR_ADDR_RDMA_LEN (ST_TIL_1_WR_ADDR_RDMA_SIZE / (sizeof(STF_U32) * 2))
  313. #define ST_TIL_1_RD_ADDR_RDMA_SIZE (sizeof(ST_RDMA_CMD) + (((sizeof(ST_TIL_1_RD_ADDR_REG) + 7) / 8) * 8))
  314. #define ST_TIL_1_RD_ADDR_RDMA_LEN (ST_TIL_1_RD_ADDR_RDMA_SIZE / (sizeof(STF_U32) * 2))
  315. #define ST_TIL_1_PDF_RDMA_SIZE (sizeof(ST_RDMA_CMD) + (((sizeof(ST_TIL_1_PDF_REG) + 7) / 8) * 8))
  316. #define ST_TIL_1_PDF_RDMA_LEN (ST_TIL_1_PDF_RDMA_SIZE / (sizeof(STF_U32) * 2))
  317. #define ST_TIL_1_RD_SD_RDMA_SIZE (sizeof(ST_RDMA_CMD) + (((sizeof(ST_TIL_1_RD_SD_REG) + 7) / 8) * 8))
  318. #define ST_TIL_1_RD_SD_RDMA_LEN (ST_TIL_1_RD_SD_RDMA_SIZE / (sizeof(STF_U32) * 2))
  319. #define ST_TIL_1_BS_RDMA_SIZE (sizeof(ST_RDMA_CMD) + (((sizeof(ST_TIL_1_BS_REG) + 7) / 8) * 8))
  320. #define ST_TIL_1_BS_RDMA_LEN (ST_TIL_1_BS_RDMA_SIZE / (sizeof(STF_U32) * 2))
  321. #define ST_TIL_1_AXI_RDMA_SIZE (sizeof(ST_RDMA_CMD) + (((sizeof(ST_TIL_1_AXI_REG) + 7) / 8) * 8))
  322. #define ST_TIL_1_AXI_RDMA_LEN (ST_TIL_1_AXI_RDMA_SIZE / (sizeof(STF_U32) * 2))
  323. #define ST_TIL_1_DPS_RDMA_SIZE (sizeof(ST_RDMA_CMD) + (((sizeof(ST_TIL_1_DPS_REG) + 7) / 8) * 8))
  324. #define ST_TIL_1_DPS_RDMA_LEN (ST_TIL_1_DPS_RDMA_SIZE / (sizeof(STF_U32) * 2))
  325. typedef struct _ST_ISP_TIL_RDMA {
  326. STF_U8 u8IspIdx;
  327. ST_TIL_RDMA stTilRdma __attribute__ ((aligned (8)));
  328. } ST_ISP_TIL_RDMA, *PST_ISP_TIL_RDMA;
  329. #pragma pack(pop)
  330. ///* tiling input/output image registers interface */
  331. ////-----------------------------------------------------------------------------
  332. //extern
  333. //STF_VOID STFHAL_ISP_TIL_SetReg(
  334. // STF_U8 u8IspIdx,
  335. // ST_TIL_RDMA *pstTilRdma
  336. // );
  337. //extern
  338. //STF_U32 STFHAL_ISP_TIL_GetAllBusyStatus(
  339. // STF_U8 u8IspIdx
  340. // );
  341. //extern
  342. //STF_VOID STFHAL_ISP_TIL_1_SetWindowReg(
  343. // STF_U8 u8IspIdx,
  344. // ST_TIL_RDMA *pstTilRdma
  345. // );
  346. //extern
  347. //STF_VOID STFHAL_ISP_TIL_1_SetConfigReg(
  348. // STF_U8 u8IspIdx,
  349. // ST_TIL_RDMA *pstTilRdma
  350. // );
  351. //extern
  352. //STF_VOID STFHAL_ISP_TIL_1_SetReadReg(
  353. // STF_U8 u8IspIdx,
  354. // ST_TIL_RDMA *pstTilRdma
  355. // );
  356. //extern
  357. //STF_VOID STFHAL_ISP_TIL_1_SetWriteReg(
  358. // STF_U8 u8IspIdx,
  359. // ST_TIL_RDMA *pstTilRdma
  360. // );
  361. //extern
  362. //STF_U32 STFHAL_ISP_TIL_1_GetBusyStatus(
  363. // STF_U8 u8IspIdx
  364. // );
  365. //extern
  366. //STF_BOOL8 STFHAL_ISP_TIL_1_IsReadBusy(
  367. // STF_U8 u8IspIdx
  368. // );
  369. //extern
  370. //STF_BOOL8 STFHAL_ISP_TIL_1_IsWriteBusy(
  371. // STF_U8 u8IspIdx
  372. // );
  373. ////-----------------------------------------------------------------------------
  374. //extern
  375. //STF_VOID STFHAL_ISP_TIL_1_SetWindowSize(
  376. // STF_U8 u8IspIdx,
  377. // ST_TIL_RDMA *pstTilRdma
  378. // );
  379. //extern
  380. //STF_VOID STFHAL_ISP_TIL_1_SetReadBufAddr(
  381. // STF_U8 u8IspIdx,
  382. // ST_TIL_RDMA *pstTilRdma
  383. // );
  384. //extern
  385. //STF_VOID STFHAL_ISP_TIL_1_SetReadBufStride(
  386. // STF_U8 u8IspIdx,
  387. // ST_TIL_RDMA *pstTilRdma
  388. // );
  389. //extern
  390. //STF_VOID STFHAL_ISP_TIL_1_SetReadDataPath(
  391. // STF_U8 u8IspIdx,
  392. // ST_TIL_RDMA *pstTilRdma
  393. // );
  394. //extern
  395. //STF_VOID STFHAL_ISP_TIL_1_SetReadNv21(
  396. // STF_U8 u8IspIdx,
  397. // ST_TIL_RDMA *pstTilRdma
  398. // );
  399. //extern
  400. //STF_VOID STFHAL_ISP_TIL_1_SetReadDataFormat(
  401. // STF_U8 u8IspIdx,
  402. // ST_TIL_RDMA *pstTilRdma
  403. // );
  404. //extern
  405. //STF_VOID STFHAL_ISP_TIL_1_SetReadFlexibleBits(
  406. // STF_U8 u8IspIdx,
  407. // ST_TIL_RDMA *pstTilRdma
  408. // );
  409. //extern
  410. //STF_VOID STFHAL_ISP_TIL_1_SetReadIndependentRvi(
  411. // STF_U8 u8IspIdx,
  412. // ST_TIL_RDMA *pstTilRdma
  413. // );
  414. //extern
  415. //STF_VOID STFHAL_ISP_TIL_1_SetReadLineBufOff(
  416. // STF_U8 u8IspIdx,
  417. // ST_TIL_RDMA *pstTilRdma
  418. // );
  419. //extern
  420. //STF_VOID STFHAL_ISP_TIL_1_SetReadAxiId(
  421. // STF_U8 u8IspIdx,
  422. // ST_TIL_RDMA *pstTilRdma
  423. // );
  424. //extern
  425. //STF_VOID STFHAL_ISP_TIL_1_SetReadEnable(
  426. // STF_U8 u8IspIdx,
  427. // ST_TIL_RDMA *pstTilRdma
  428. // );
  429. //extern
  430. //STF_VOID STFHAL_ISP_TIL_1_SetWriteBufAddr(
  431. // STF_U8 u8IspIdx,
  432. // ST_TIL_RDMA *pstTilRdma
  433. // );
  434. //extern
  435. //STF_VOID STFHAL_ISP_TIL_1_SetWriteBufStride(
  436. // STF_U8 u8IspIdx,
  437. // ST_TIL_RDMA *pstTilRdma
  438. // );
  439. //extern
  440. //STF_VOID STFHAL_ISP_TIL_1_SetWriteDataPath(
  441. // STF_U8 u8IspIdx,
  442. // ST_TIL_RDMA *pstTilRdma
  443. // );
  444. //extern
  445. //STF_VOID STFHAL_ISP_TIL_1_SetWriteNv21(
  446. // STF_U8 u8IspIdx,
  447. // ST_TIL_RDMA *pstTilRdma
  448. // );
  449. //extern
  450. //STF_VOID STFHAL_ISP_TIL_1_SetWriteDataFormat(
  451. // STF_U8 u8IspIdx,
  452. // ST_TIL_RDMA *pstTilRdma
  453. // );
  454. //extern
  455. //STF_VOID STFHAL_ISP_TIL_1_SetWriteFlexibleBits(
  456. // STF_U8 u8IspIdx,
  457. // ST_TIL_RDMA *pstTilRdma
  458. // );
  459. //extern
  460. //STF_VOID STFHAL_ISP_TIL_1_SetWriteAxiId(
  461. // STF_U8 u8IspIdx,
  462. // ST_TIL_RDMA *pstTilRdma
  463. // );
  464. //extern
  465. //STF_VOID STFHAL_ISP_TIL_1_SetWriteEnable(
  466. // STF_U8 u8IspIdx,
  467. // ST_TIL_RDMA *pstTilRdma
  468. // );
  469. //extern
  470. //STF_VOID STFHAL_ISP_TIL_1_SetIspRaw10InDW(
  471. // STF_U8 u8IspIdx,
  472. // ST_TIL_RDMA *pstTilRdma
  473. // );
  474. //extern
  475. //STF_VOID STFHAL_ISP_TIL_1_SetLoopbackMode(
  476. // STF_U8 u8IspIdx,
  477. // ST_TIL_RDMA *pstTilRdma
  478. // );
  479. //extern
  480. //STF_VOID STFHAL_ISP_TIL_1_SetDmaMode(
  481. // STF_U8 u8IspIdx,
  482. // ST_TIL_RDMA *pstTilRdma
  483. // );
  484. ////-----------------------------------------------------------------------------
  485. //
  486. //
  487. #endif //__STF_ISP_TIL_RDMA_H__