wave5_regdefine.h 30 KB

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  1. /* SPDX-License-Identifier: LGPL-2.1 OR BSD-3-Clause */
  2. //--=========================================================================--
  3. // This file is a part of VPU Reference API project
  4. //-----------------------------------------------------------------------------
  5. //
  6. // This confidential and proprietary software may be used only
  7. // as authorized by a licensing agreement from Chips&Media Inc.
  8. // In the event of publication, the following notice is applicable:
  9. //
  10. // (C) COPYRIGHT 2006 - 2013 CHIPS&MEDIA INC.
  11. // ALL RIGHTS RESERVED
  12. //
  13. // The entire notice above must be reproduced on all authorized
  14. // copies.
  15. //
  16. //--=========================================================================--
  17. #ifndef __WAVE510_REGISTER_DEFINE_H__
  18. #define __WAVE510_REGISTER_DEFINE_H__
  19. enum {
  20. W5_INT_INIT_VPU = 0,
  21. W5_INT_WAKEUP_VPU = 1,
  22. W5_INT_SLEEP_VPU = 2,
  23. W5_INT_CREATE_INSTANCE = 3,
  24. W5_INT_FLUSH_INSTANCE = 4,
  25. W5_INT_DESTORY_INSTANCE = 5,
  26. W5_INT_INIT_SEQ = 6,
  27. W5_INT_SET_FRAMEBUF = 7,
  28. W5_INT_DEC_PIC = 8,
  29. W5_INT_ENC_PIC = 8,
  30. W5_INT_ENC_SET_PARAM = 9,
  31. W5_INT_DEC_QUERY = 14,
  32. W5_INT_BSBUF_EMPTY = 15,
  33. };
  34. typedef enum {
  35. W5_INIT_VPU = 0x0001,
  36. W5_WAKEUP_VPU = 0x0002,
  37. W5_SLEEP_VPU = 0x0004,
  38. W5_CREATE_INSTANCE = 0x0008, /* queuing command */
  39. W5_FLUSH_INSTANCE = 0x0010,
  40. W5_DESTROY_INSTANCE= 0x0020, /* queuing command */
  41. W5_INIT_SEQ = 0x0040, /* queuing command */
  42. W5_SET_FB = 0x0080,
  43. W5_DEC_PIC = 0x0100, /* queuing command */
  44. W5_ENC_PIC = 0x0100, /* queuing command */
  45. W5_ENC_SET_PARAM = 0x0200, /* queuing command */
  46. W5_QUERY = 0x4000,
  47. W5_UPDATE_BS = 0x8000,
  48. W5_RESET_VPU = 0x10000,
  49. W5_MAX_VPU_COMD = 0x10000,
  50. } W5_VPU_COMMAND;
  51. typedef enum {
  52. GET_VPU_INFO = 0,
  53. SET_WRITE_PROT = 1,
  54. GET_RESULT = 2,
  55. UPDATE_DISP_FLAG = 3,
  56. GET_BW_REPORT = 4
  57. } QUERY_OPT;
  58. #define W5_REG_BASE 0x00000000
  59. #define W5_CMD_REG_BASE 0x00000100
  60. #define W5_CMD_REG_END 0x00000200
  61. #define WAVE5_AXI_ID 0x0
  62. /*
  63. * Common
  64. */
  65. /* Power On Configuration
  66. * PO_DEBUG_MODE [0] 1 - Power On with debug mode
  67. * USE_PO_CONF [3] 1 - Use Power-On-Configuration
  68. */
  69. #define W5_PO_CONF (W5_REG_BASE + 0x0000)
  70. #define W5_VCPU_CUR_PC (W5_REG_BASE + 0x0004)
  71. #define W5_VPU_PDBG_CTRL (W5_REG_BASE + 0x0010) // vCPU debugger ctrl register
  72. #define W5_VPU_PDBG_IDX_REG (W5_REG_BASE + 0x0014) // vCPU debugger index register
  73. #define W5_VPU_PDBG_WDATA_REG (W5_REG_BASE + 0x0018) // vCPU debugger write data register
  74. #define W5_VPU_PDBG_RDATA_REG (W5_REG_BASE + 0x001C) // vCPU debugger read data register
  75. #define W5_VPU_FIO_CTRL_ADDR (W5_REG_BASE + 0x0020)
  76. #define W5_VPU_FIO_DATA (W5_REG_BASE + 0x0024)
  77. #define W5_VPU_VINT_REASON_USR (W5_REG_BASE + 0x0030)
  78. #define W5_VPU_VINT_REASON_CLR (W5_REG_BASE + 0x0034)
  79. #define W5_VPU_HOST_INT_REQ (W5_REG_BASE + 0x0038)
  80. #define W5_VPU_VINT_CLEAR (W5_REG_BASE + 0x003C)
  81. #define W5_VPU_HINT_CLEAR (W5_REG_BASE + 0x0040)
  82. #define W5_VPU_VPU_INT_STS (W5_REG_BASE + 0x0044)
  83. #define W5_VPU_VINT_ENABLE (W5_REG_BASE + 0x0048)
  84. #define W5_VPU_VINT_REASON (W5_REG_BASE + 0x004C)
  85. #define W5_VPU_RESET_REQ (W5_REG_BASE + 0x0050)
  86. #define W5_RST_BLOCK_CCLK(_core) (1<<_core)
  87. #define W5_RST_BLOCK_CCLK_ALL (0xff)
  88. #define W5_RST_BLOCK_BCLK(_core) (0x100<<_core)
  89. #define W5_RST_BLOCK_BCLK_ALL (0xff00)
  90. #define W5_RST_BLOCK_ACLK(_core) (0x10000<<_core)
  91. #define W5_RST_BLOCK_ACLK_ALL (0xff0000)
  92. #define W5_RST_BLOCK_VCPU (0x1000000)
  93. #define W5_RST_BLOCK_VCLK (0x2000000)
  94. #define W5_RST_BLOCK_MCLK (0x4000000)
  95. #define W5_RST_BLOCK_ALL (0xfffffff)
  96. #define W5_VPU_RESET_STATUS (W5_REG_BASE + 0x0054)
  97. #define W5_VCPU_RESTART (W5_REG_BASE + 0x0058)
  98. #define W5_VPU_CLK_MASK (W5_REG_BASE + 0x005C)
  99. /* REMAP_CTRL
  100. * PAGE SIZE: [8:0] 0x001 - 4K
  101. * 0x002 - 8K
  102. * 0x004 - 16K
  103. * ...
  104. * 0x100 - 1M
  105. * REGION ATTR1 [10] 0 - Normal
  106. * 1 - Make Bus error for the region
  107. * REGION ATTR2 [11] 0 - Normal
  108. * 1 - Bypass region
  109. * REMAP INDEX [15:12] - 0 ~ 3 , 0 - Code, 1-Stack
  110. * ENDIAN [19:16] - See EndianMode in vdi.h
  111. * AXI-ID [23:20] - Upper AXI-ID
  112. * BUS_ERROR [29] 0 - bypass
  113. * 1 - Make BUS_ERROR for unmapped region
  114. * BYPASS_ALL [30] 1 - Bypass all
  115. * ENABLE [31] 1 - Update control register[30:16]
  116. */
  117. enum {
  118. W5_REMAP_CODE_INDEX=0,
  119. };
  120. #define W5_VPU_REMAP_CTRL (W5_REG_BASE + 0x0060)
  121. #define W5_VPU_REMAP_VADDR (W5_REG_BASE + 0x0064)
  122. #define W5_VPU_REMAP_PADDR (W5_REG_BASE + 0x0068)
  123. #define W5_VPU_REMAP_CORE_START (W5_REG_BASE + 0x006C)
  124. #define W5_VPU_BUSY_STATUS (W5_REG_BASE + 0x0070)
  125. #define W5_VPU_HALT_STATUS (W5_REG_BASE + 0x0074)
  126. /************************************************************************/
  127. /* DECODER/ENCODER COMMON */
  128. /************************************************************************/
  129. #define W5_COMMAND (W5_REG_BASE + 0x0100)
  130. #define W5_COMMAND_OPTION (W5_REG_BASE + 0x0104)
  131. #define W5_QUERY_OPTION (W5_REG_BASE + 0x0104)
  132. #define W5_RET_SUCCESS (W5_REG_BASE + 0x0108)
  133. #define W5_RET_FAIL_REASON (W5_REG_BASE + 0x010C)
  134. #define W5_CMD_INSTANCE_INFO (W5_REG_BASE + 0x0110)
  135. #define W5_RET_QUEUE_STATUS (W5_REG_BASE + 0x01E0)
  136. #define W5_RET_BS_EMPTY_INST (W5_REG_BASE + 0x01E4)
  137. #define W5_RET_QUEUE_CMD_DONE_INST (W5_REG_BASE + 0x01E8)
  138. #define W5_RET_STAGE0_INSTANCE_INFO (W5_REG_BASE + 0x01EC)
  139. #define W5_RET_STAGE1_INSTANCE_INFO (W5_REG_BASE + 0x01F0)
  140. #define W5_RET_STAGE2_INSTANCE_INFO (W5_REG_BASE + 0x01F4)
  141. #define W5_RET_DONE_INSTANCE_INFO (W5_REG_BASE + 0x01FC)
  142. #define W5_BS_RD_PTR (W5_REG_BASE + 0x0118)
  143. #define W5_BS_WR_PTR (W5_REG_BASE + 0x011C)
  144. #define W5_BS_OPTION (W5_REG_BASE + 0x0120)
  145. /************************************************************************/
  146. /* DECODER - INIT_VPU */
  147. /************************************************************************/
  148. /* Note: W5_ADDR_CODE_BASE should be aligned to 4KB */
  149. #define W5_ADDR_CODE_BASE (W5_REG_BASE + 0x0110)
  150. #define W5_CODE_SIZE (W5_REG_BASE + 0x0114)
  151. #define W5_CODE_PARAM (W5_REG_BASE + 0x0118)
  152. #define W5_ADDR_TEMP_BASE (W5_REG_BASE + 0x011C)
  153. #define W5_TEMP_SIZE (W5_REG_BASE + 0x0120)
  154. #define W5_ADDR_SEC_AXI (W5_REG_BASE + 0x0124)
  155. #define W5_SEC_AXI_SIZE (W5_REG_BASE + 0x0128)
  156. #define W5_HW_OPTION (W5_REG_BASE + 0x012C)
  157. #define W5_TIMEOUT_CNT (W5_REG_BASE + 0x0130)
  158. #define W5_CMD_INIT_NUM_TASK_BUF (W5_REG_BASE + 0x0134)
  159. #define W5_CMD_INIT_ADDR_TASK_BUF0 (W5_REG_BASE + 0x0138)
  160. #define W5_CMD_INIT_ADDR_TASK_BUF1 (W5_REG_BASE + 0x013C)
  161. #define W5_CMD_INIT_ADDR_TASK_BUF2 (W5_REG_BASE + 0x0140)
  162. #define W5_CMD_INIT_ADDR_TASK_BUF3 (W5_REG_BASE + 0x0144)
  163. #define W5_CMD_INIT_ADDR_TASK_BUF4 (W5_REG_BASE + 0x0148)
  164. #define W5_CMD_INIT_ADDR_TASK_BUF5 (W5_REG_BASE + 0x014C)
  165. #define W5_CMD_INIT_ADDR_TASK_BUF6 (W5_REG_BASE + 0x0150)
  166. #define W5_CMD_INIT_ADDR_TASK_BUF7 (W5_REG_BASE + 0x0154)
  167. #define W5_CMD_INIT_ADDR_TASK_BUF8 (W5_REG_BASE + 0x0158)
  168. #define W5_CMD_INIT_ADDR_TASK_BUF9 (W5_REG_BASE + 0x015C)
  169. #define W5_CMD_INIT_ADDR_TASK_BUFA (W5_REG_BASE + 0x0160)
  170. #define W5_CMD_INIT_ADDR_TASK_BUFB (W5_REG_BASE + 0x0164)
  171. #define W5_CMD_INIT_ADDR_TASK_BUFC (W5_REG_BASE + 0x0168)
  172. #define W5_CMD_INIT_ADDR_TASK_BUFD (W5_REG_BASE + 0x016C)
  173. #define W5_CMD_INIT_ADDR_TASK_BUFE (W5_REG_BASE + 0x0170)
  174. #define W5_CMD_INIT_ADDR_TASK_BUFF (W5_REG_BASE + 0x0174)
  175. #define W5_CMD_INIT_TASK_BUF_SIZE (W5_REG_BASE + 0x0178)
  176. /************************************************************************/
  177. /* CREATE_INSTANCE - COMMON */
  178. /************************************************************************/
  179. #define W5_ADDR_WORK_BASE (W5_REG_BASE + 0x0114)
  180. #define W5_WORK_SIZE (W5_REG_BASE + 0x0118)
  181. #define W5_CMD_DEC_BS_START_ADDR (W5_REG_BASE + 0x011C)
  182. #define W5_CMD_DEC_BS_SIZE (W5_REG_BASE + 0x0120)
  183. #define W5_CMD_BS_PARAM (W5_REG_BASE + 0x0124)
  184. /************************************************************************/
  185. /* DECODER - INIT_SEQ */
  186. /************************************************************************/
  187. /************************************************************************/
  188. /* SET_FRAME_BUF */
  189. /************************************************************************/
  190. /* SET_FB_OPTION 0x00 REGISTER FRAMEBUFFERS
  191. 0x01 UPDATE FRAMEBUFFER, just one framebuffer(linear, fbc and mvcol)
  192. */
  193. #define W5_SFB_OPTION (W5_REG_BASE + 0x0104)
  194. #define W5_COMMON_PIC_INFO (W5_REG_BASE + 0x0118)
  195. #define W5_PIC_SIZE (W5_REG_BASE + 0x011C)
  196. #define W5_SET_FB_NUM (W5_REG_BASE + 0x0120)
  197. #define W5_ADDR_LUMA_BASE0 (W5_REG_BASE + 0x0134)
  198. #define W5_ADDR_CB_BASE0 (W5_REG_BASE + 0x0138)
  199. #define W5_ADDR_CR_BASE0 (W5_REG_BASE + 0x013C)
  200. #define W5_ADDR_FBC_Y_OFFSET0 (W5_REG_BASE + 0x013C) // Compression offset table for Luma
  201. #define W5_ADDR_FBC_C_OFFSET0 (W5_REG_BASE + 0x0140) // Compression offset table for Chroma
  202. #define W5_ADDR_LUMA_BASE1 (W5_REG_BASE + 0x0144)
  203. #define W5_ADDR_CB_ADDR1 (W5_REG_BASE + 0x0148)
  204. #define W5_ADDR_CR_ADDR1 (W5_REG_BASE + 0x014C)
  205. #define W5_ADDR_FBC_Y_OFFSET1 (W5_REG_BASE + 0x014C) // Compression offset table for Luma
  206. #define W5_ADDR_FBC_C_OFFSET1 (W5_REG_BASE + 0x0150) // Compression offset table for Chroma
  207. #define W5_ADDR_LUMA_BASE2 (W5_REG_BASE + 0x0154)
  208. #define W5_ADDR_CB_ADDR2 (W5_REG_BASE + 0x0158)
  209. #define W5_ADDR_CR_ADDR2 (W5_REG_BASE + 0x015C)
  210. #define W5_ADDR_FBC_Y_OFFSET2 (W5_REG_BASE + 0x015C) // Compression offset table for Luma
  211. #define W5_ADDR_FBC_C_OFFSET2 (W5_REG_BASE + 0x0160) // Compression offset table for Chroma
  212. #define W5_ADDR_LUMA_BASE3 (W5_REG_BASE + 0x0164)
  213. #define W5_ADDR_CB_ADDR3 (W5_REG_BASE + 0x0168)
  214. #define W5_ADDR_CR_ADDR3 (W5_REG_BASE + 0x016C)
  215. #define W5_ADDR_FBC_Y_OFFSET3 (W5_REG_BASE + 0x016C) // Compression offset table for Luma
  216. #define W5_ADDR_FBC_C_OFFSET3 (W5_REG_BASE + 0x0170) // Compression offset table for Chroma
  217. #define W5_ADDR_LUMA_BASE4 (W5_REG_BASE + 0x0174)
  218. #define W5_ADDR_CB_ADDR4 (W5_REG_BASE + 0x0178)
  219. #define W5_ADDR_CR_ADDR4 (W5_REG_BASE + 0x017C)
  220. #define W5_ADDR_FBC_Y_OFFSET4 (W5_REG_BASE + 0x017C) // Compression offset table for Luma
  221. #define W5_ADDR_FBC_C_OFFSET4 (W5_REG_BASE + 0x0180) // Compression offset table for Chroma
  222. #define W5_ADDR_LUMA_BASE5 (W5_REG_BASE + 0x0184)
  223. #define W5_ADDR_CB_ADDR5 (W5_REG_BASE + 0x0188)
  224. #define W5_ADDR_CR_ADDR5 (W5_REG_BASE + 0x018C)
  225. #define W5_ADDR_FBC_Y_OFFSET5 (W5_REG_BASE + 0x018C) // Compression offset table for Luma
  226. #define W5_ADDR_FBC_C_OFFSET5 (W5_REG_BASE + 0x0190) // Compression offset table for Chroma
  227. #define W5_ADDR_LUMA_BASE6 (W5_REG_BASE + 0x0194)
  228. #define W5_ADDR_CB_ADDR6 (W5_REG_BASE + 0x0198)
  229. #define W5_ADDR_CR_ADDR6 (W5_REG_BASE + 0x019C)
  230. #define W5_ADDR_FBC_Y_OFFSET6 (W5_REG_BASE + 0x019C) // Compression offset table for Luma
  231. #define W5_ADDR_FBC_C_OFFSET6 (W5_REG_BASE + 0x01A0) // Compression offset table for Chroma
  232. #define W5_ADDR_LUMA_BASE7 (W5_REG_BASE + 0x01A4)
  233. #define W5_ADDR_CB_ADDR7 (W5_REG_BASE + 0x01A8)
  234. #define W5_ADDR_CR_ADDR7 (W5_REG_BASE + 0x01AC)
  235. #define W5_ADDR_FBC_Y_OFFSET7 (W5_REG_BASE + 0x01AC) // Compression offset table for Luma
  236. #define W5_ADDR_FBC_C_OFFSET7 (W5_REG_BASE + 0x01B0) // Compression offset table for Chroma
  237. #define W5_ADDR_MV_COL0 (W5_REG_BASE + 0x01B4)
  238. #define W5_ADDR_MV_COL1 (W5_REG_BASE + 0x01B8)
  239. #define W5_ADDR_MV_COL2 (W5_REG_BASE + 0x01BC)
  240. #define W5_ADDR_MV_COL3 (W5_REG_BASE + 0x01C0)
  241. #define W5_ADDR_MV_COL4 (W5_REG_BASE + 0x01C4)
  242. #define W5_ADDR_MV_COL5 (W5_REG_BASE + 0x01C8)
  243. #define W5_ADDR_MV_COL6 (W5_REG_BASE + 0x01CC)
  244. #define W5_ADDR_MV_COL7 (W5_REG_BASE + 0x01D0)
  245. /* UPDATE_FB */
  246. /* CMD_SET_FB_STRIDE [15:0] - FBC framebuffer stride
  247. [31:15] - Linear framebuffer stride
  248. */
  249. #define W5_CMD_SET_FB_STRIDE (W5_REG_BASE + 0x0118)
  250. #define W5_CMD_SET_FB_INDEX (W5_REG_BASE + 0x0120)
  251. #define W5_ADDR_LUMA_BASE (W5_REG_BASE + 0x0134)
  252. #define W5_ADDR_CB_BASE (W5_REG_BASE + 0x0138)
  253. #define W5_ADDR_CR_BASE (W5_REG_BASE + 0x013C)
  254. #define W5_ADDR_MV_COL (W5_REG_BASE + 0x0140)
  255. #define W5_ADDR_FBC_Y_BASE (W5_REG_BASE + 0x0144)
  256. #define W5_ADDR_FBC_C_BASE (W5_REG_BASE + 0x0148)
  257. #define W5_ADDR_FBC_Y_OFFSET (W5_REG_BASE + 0x014C)
  258. #define W5_ADDR_FBC_C_OFFSET (W5_REG_BASE + 0x0150)
  259. /************************************************************************/
  260. /* DECODER - DEC_PIC */
  261. /************************************************************************/
  262. #define W5_CMD_DEC_VCORE_LIMIT (W5_REG_BASE + 0x0124)
  263. /* Sequence change enable mask register
  264. * CMD_SEQ_CHANGE_ENABLE_FLAG [5] profile_idc
  265. * [16] pic_width/height_in_luma_sample
  266. * [19] sps_max_dec_pic_buffering, max_num_reorder, max_latency_increase
  267. */
  268. #define W5_CMD_SEQ_CHANGE_ENABLE_FLAG (W5_REG_BASE + 0x0128)
  269. #define W5_CMD_DEC_USER_MASK (W5_REG_BASE + 0x012C)
  270. #define W5_CMD_DEC_TEMPORAL_ID_PLUS1 (W5_REG_BASE + 0x0130)
  271. #define W5_CMD_DEC_FORCE_FB_LATENCY_PLUS1 (W5_REG_BASE + 0x0134)
  272. #define W5_USE_SEC_AXI (W5_REG_BASE + 0x0138)
  273. /************************************************************************/
  274. /* DECODER - QUERY : GET_VPU_INFO */
  275. /************************************************************************/
  276. #define W5_RET_FW_VERSION (W5_REG_BASE + 0x0118)
  277. #define W5_RET_PRODUCT_NAME (W5_REG_BASE + 0x011C)
  278. #define W5_RET_PRODUCT_VERSION (W5_REG_BASE + 0x0120)
  279. #define W5_RET_STD_DEF0 (W5_REG_BASE + 0x0124)
  280. #define W5_RET_STD_DEF1 (W5_REG_BASE + 0x0128)
  281. #define W5_RET_CONF_FEATURE (W5_REG_BASE + 0x012C)
  282. #define W5_RET_CONF_DATE (W5_REG_BASE + 0x0130)
  283. #define W5_RET_CONF_REVISION (W5_REG_BASE + 0x0134)
  284. #define W5_RET_CONF_TYPE (W5_REG_BASE + 0x0138)
  285. #define W5_RET_PRODUCT_ID (W5_REG_BASE + 0x013C)
  286. #define W5_RET_CUSTOMER_ID (W5_REG_BASE + 0x0140)
  287. /************************************************************************/
  288. /* DECODER - QUERY : GET_RESULT */
  289. /************************************************************************/
  290. #define W5_CMD_DEC_ADDR_REPORT_BASE (W5_REG_BASE + 0x0114)
  291. #define W5_CMD_DEC_REPORT_SIZE (W5_REG_BASE + 0x0118)
  292. #define W5_CMD_DEC_REPORT_PARAM (W5_REG_BASE + 0x011C)
  293. #define W5_RET_DEC_BS_RD_PTR (W5_REG_BASE + 0x011C)
  294. #define W5_RET_DEC_SEQ_PARAM (W5_REG_BASE + 0x0120)
  295. #define W5_RET_DEC_COLOR_SAMPLE_INFO (W5_REG_BASE + 0x0124)
  296. #define W5_RET_DEC_ASPECT_RATIO (W5_REG_BASE + 0x0128)
  297. #define W5_RET_DEC_BIT_RATE (W5_REG_BASE + 0x012C)
  298. #define W5_RET_DEC_FRAME_RATE_NR (W5_REG_BASE + 0x0130)
  299. #define W5_RET_DEC_FRAME_RATE_DR (W5_REG_BASE + 0x0134)
  300. #define W5_RET_DEC_FRAMEBUF_NEEDED (W5_REG_BASE + 0x0138)
  301. #define W5_RET_DEC_NUM_REORDER_DELAY (W5_REG_BASE + 0x013C)
  302. #define W5_RET_DEC_SUB_LAYER_INFO (W5_REG_BASE + 0x0140)
  303. #define W5_RET_DEC_NOTIFICATION (W5_REG_BASE + 0x0144)
  304. #define W5_RET_DEC_USERDATA_IDC (W5_REG_BASE + 0x0148)
  305. #define W5_RET_DEC_PIC_SIZE (W5_REG_BASE + 0x014C)
  306. #define W5_RET_DEC_CROP_TOP_BOTTOM (W5_REG_BASE + 0x0150)
  307. #define W5_RET_DEC_CROP_LEFT_RIGHT (W5_REG_BASE + 0x0154)
  308. #define W5_RET_DEC_AU_START_POS (W5_REG_BASE + 0x0158)
  309. #define W5_RET_DEC_AU_END_POS (W5_REG_BASE + 0x015C)
  310. #define W5_RET_DEC_PIC_TYPE (W5_REG_BASE + 0x0160)
  311. #define W5_RET_DEC_PIC_POC (W5_REG_BASE + 0x0164)
  312. #define W5_RET_DEC_RECOVERY_POINT (W5_REG_BASE + 0x0168)
  313. #define W5_RET_DEC_DEBUG_INDEX (W5_REG_BASE + 0x016C)
  314. #define W5_RET_DEC_DECODED_INDEX (W5_REG_BASE + 0x0170)
  315. #define W5_RET_DEC_DISPLAY_INDEX (W5_REG_BASE + 0x0174)
  316. #define W5_RET_DEC_REALLOC_INDEX (W5_REG_BASE + 0x0178)
  317. #define W5_RET_DEC_DISP_FLAG (W5_REG_BASE + 0x017C)
  318. #define W5_RET_DEC_ERR_CTB_NUM (W5_REG_BASE + 0x0180)
  319. #define W5_RET_DEC_SEEK_CYCLE (W5_REG_BASE + 0x01C0)
  320. #define W5_RET_DEC_PARSING_CYCLE (W5_REG_BASE + 0x01C4)
  321. #define W5_RET_DEC_DECODING_CYCLE (W5_REG_BASE + 0x01C8)
  322. #define W5_FRAME_CYCLE (W5_REG_BASE + 0x01D0)
  323. #define W5_RET_DEC_WARN_INFO (W5_REG_BASE + 0x01D4)
  324. #define W5_RET_DEC_ERR_INFO (W5_REG_BASE + 0x01D8)
  325. #define W5_RET_DEC_DECODING_SUCCESS (W5_REG_BASE + 0x01DC)
  326. /************************************************************************/
  327. /* DECODER - FLUSH_INSTANCE */
  328. /************************************************************************/
  329. #define W5_CMD_FLUSH_INST_OPT (W5_REG_BASE + 0x104)
  330. /************************************************************************/
  331. /* DECODER - QUERY : UPDATE_DISP_FLAG */
  332. /************************************************************************/
  333. #define W5_CMD_DEC_SET_DISP_IDC (W5_REG_BASE + 0x0118)
  334. #define W5_CMD_DEC_CLR_DISP_IDC (W5_REG_BASE + 0x011C)
  335. #define W5_RET_DEC_DISP_IDC (W5_REG_BASE + 0x017C)
  336. /************************************************************************/
  337. /* GDI register for Debugging */
  338. /************************************************************************/
  339. #define W5_GDI_BASE 0x8800 // FIX ME
  340. #define W5_GDI_BUS_CTRL (W5_GDI_BASE + 0x0F0)
  341. #define W5_GDI_BUS_STATUS (W5_GDI_BASE + 0x0F4)
  342. #define W5_ENC_GDI_BASE 0xFE00
  343. #define W5_ENC_GDI_BUS_CTRL (W5_ENC_GDI_BASE + 0x010)
  344. #define W5_ENC_GDI_BUS_STATUS (W5_ENC_GDI_BASE + 0x014)
  345. /************************************************************************/
  346. /* */
  347. /* For ENCODER */
  348. /* */
  349. /************************************************************************/
  350. #define W5_RET_STAGE3_INSTANCE_INFO (W5_REG_BASE + 0x1F8)
  351. /************************************************************************/
  352. /* ENCODER - CREATE_INSTANCE */
  353. /************************************************************************/
  354. // 0x114 ~ 0x124 : defined above (CREATE_INSTANCE COMMON)
  355. #define W5_CMD_ENC_VCORE_LIMIT (W5_REG_BASE + 0x128)
  356. /************************************************************************/
  357. /* ENCODER - SET_FB */
  358. /************************************************************************/
  359. #define W5_FBC_STRIDE (W5_REG_BASE + 0x128)
  360. #define W5_ADDR_SUB_SAMPLED_FB_BASE (W5_REG_BASE + 0x12C)
  361. #define W5_SUB_SAMPLED_ONE_FB_SIZE (W5_REG_BASE + 0x130)
  362. /************************************************************************/
  363. /* ENCODER - ENC_SET_PARAM (COMMON & CHANGE_PARAM) */
  364. /************************************************************************/
  365. #define W5_CMD_ENC_SEQ_SET_PARAM_OPTION (W5_REG_BASE + 0x104)
  366. #define W5_CMD_ENC_SEQ_SET_PARAM_ENABLE (W5_REG_BASE + 0x118)
  367. #define W5_CMD_ENC_SEQ_SRC_SIZE (W5_REG_BASE + 0x11C)
  368. #define W5_CMD_ENC_SEQ_CUSTOM_MAP_ENDIAN (W5_REG_BASE + 0x120)
  369. #define W5_CMD_ENC_SEQ_SYNTAX_SPS_PARAM (W5_REG_BASE + 0x124)
  370. #define W5_CMD_ENC_SEQ_SYNTAX_PPS_PARAM (W5_REG_BASE + 0x128)
  371. #define W5_CMD_ENC_SEQ_GOP_PARAM (W5_REG_BASE + 0x12C)
  372. #define W5_CMD_ENC_SEQ_INTRA_PARAM (W5_REG_BASE + 0x130)
  373. #define W5_CMD_ENC_SEQ_CONF_WIN_TOP_BOT (W5_REG_BASE + 0x134)
  374. #define W5_CMD_ENC_SEQ_CONF_WIN_LEFT_RIGHT (W5_REG_BASE + 0x138)
  375. #define W5_CMD_ENC_SEQ_RDO_PARAM (W5_REG_BASE + 0x13C)
  376. #define W5_CMD_ENC_SEQ_INDEPENDENT_SLICE (W5_REG_BASE + 0x140)
  377. #define W5_CMD_ENC_SEQ_DEPENDENT_SLICE (W5_REG_BASE + 0x144)
  378. #define W5_CMD_ENC_SEQ_INTRA_REFRESH (W5_REG_BASE + 0x148)
  379. #define W5_CMD_ENC_SEQ_RC_FRAME_RATE (W5_REG_BASE + 0x150)
  380. #define W5_CMD_ENC_SEQ_RC_TARGET_RATE (W5_REG_BASE + 0x154)
  381. #define W5_CMD_ENC_SEQ_RC_PARAM (W5_REG_BASE + 0x158)
  382. #define W5_CMD_ENC_SEQ_RC_MIN_MAX_QP (W5_REG_BASE + 0x15C)
  383. #define W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_0_3 (W5_REG_BASE + 0x160)
  384. #define W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_4_7 (W5_REG_BASE + 0x164)
  385. #define W5_CMD_ENC_SEQ_ROT_PARAM (W5_REG_BASE + 0x170)
  386. #define W5_CMD_ENC_SEQ_NUM_UNITS_IN_TICK (W5_REG_BASE + 0x174)
  387. #define W5_CMD_ENC_SEQ_TIME_SCALE (W5_REG_BASE + 0x178)
  388. #define W5_CMD_ENC_SEQ_NUM_TICKS_POC_DIFF_ONE (W5_REG_BASE + 0x17C)
  389. #define W5_CMD_ENC_SEQ_CUSTOM_MD_PU04 (W5_REG_BASE + 0x184)
  390. #define W5_CMD_ENC_SEQ_CUSTOM_MD_PU08 (W5_REG_BASE + 0x188)
  391. #define W5_CMD_ENC_SEQ_CUSTOM_MD_PU16 (W5_REG_BASE + 0x18C)
  392. #define W5_CMD_ENC_SEQ_CUSTOM_MD_PU32 (W5_REG_BASE + 0x190)
  393. #define W5_CMD_ENC_SEQ_CUSTOM_MD_CU08 (W5_REG_BASE + 0x194)
  394. #define W5_CMD_ENC_SEQ_CUSTOM_MD_CU16 (W5_REG_BASE + 0x198)
  395. #define W5_CMD_ENC_SEQ_CUSTOM_MD_CU32 (W5_REG_BASE + 0x19C)
  396. #define W5_CMD_ENC_SEQ_NR_PARAM (W5_REG_BASE + 0x1A0)
  397. #define W5_CMD_ENC_SEQ_NR_WEIGHT (W5_REG_BASE + 0x1A4)
  398. #define W5_CMD_ENC_SEQ_BG_PARAM (W5_REG_BASE + 0x1A8)
  399. #define W5_CMD_ENC_SEQ_CUSTOM_LAMBDA_ADDR (W5_REG_BASE + 0x1AC)
  400. #define W5_CMD_ENC_SEQ_USER_SCALING_LIST_ADDR (W5_REG_BASE + 0x1B0)
  401. /************************************************************************/
  402. /* ENCODER - ENC_SET_PARAM (CUSTOM_GOP) */
  403. /************************************************************************/
  404. #define W5_CMD_ENC_CUSTOM_GOP_PARAM (W5_REG_BASE + 0x11C)
  405. #define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_0 (W5_REG_BASE + 0x120)
  406. #define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_1 (W5_REG_BASE + 0x124)
  407. #define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_2 (W5_REG_BASE + 0x128)
  408. #define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_3 (W5_REG_BASE + 0x12C)
  409. #define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_4 (W5_REG_BASE + 0x130)
  410. #define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_5 (W5_REG_BASE + 0x134)
  411. #define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_6 (W5_REG_BASE + 0x138)
  412. #define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_7 (W5_REG_BASE + 0x13C)
  413. /************************************************************************/
  414. /* ENCODER - ENC_PIC */
  415. /************************************************************************/
  416. #define W5_CMD_ENC_BS_START_ADDR (W5_REG_BASE + 0x118)
  417. #define W5_CMD_ENC_BS_SIZE (W5_REG_BASE + 0x11C)
  418. #define W5_CMD_ENC_PIC_USE_SEC_AXI (W5_REG_BASE + 0x124)
  419. #define W5_CMD_ENC_PIC_REPORT_PARAM (W5_REG_BASE + 0x128)
  420. #define W5_CMD_ENC_PIC_REPORT_ENDIAN (W5_REG_BASE + 0x12C)
  421. #define W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_PARAM (W5_REG_BASE + 0x138)
  422. #define W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_ADDR (W5_REG_BASE + 0x13C)
  423. #define W5_CMD_ENC_PIC_SRC_PIC_IDX (W5_REG_BASE + 0x144)
  424. #define W5_CMD_ENC_PIC_SRC_ADDR_Y (W5_REG_BASE + 0x148)
  425. #define W5_CMD_ENC_PIC_SRC_ADDR_U (W5_REG_BASE + 0x14C)
  426. #define W5_CMD_ENC_PIC_SRC_ADDR_V (W5_REG_BASE + 0x150)
  427. #define W5_CMD_ENC_PIC_SRC_STRIDE (W5_REG_BASE + 0x154)
  428. #define W5_CMD_ENC_PIC_SRC_FORMAT (W5_REG_BASE + 0x158)
  429. #define W5_CMD_ENC_PIC_CODE_OPTION (W5_REG_BASE + 0x164)
  430. #define W5_CMD_ENC_PIC_PIC_PARAM (W5_REG_BASE + 0x168)
  431. #define W5_CMD_ENC_PIC_LONGTERM_PIC (W5_REG_BASE + 0x16C)
  432. #define W5_CMD_ENC_PIC_WP_PIXEL_VAR_Y (W5_REG_BASE + 0x170)
  433. #define W5_CMD_ENC_PIC_WP_PIXEL_VAR_CB (W5_REG_BASE + 0x174)
  434. #define W5_CMD_ENC_PIC_WP_PIXEL_VAR_CR (W5_REG_BASE + 0x178)
  435. #define W5_CMD_ENC_PIC_WP_PIXEL_MEAN (W5_REG_BASE + 0x17C)
  436. /************************************************************************/
  437. /* ENCODER - QUERY (GET_RESULT) */
  438. /************************************************************************/
  439. #define W5_RET_ENC_RD_PTR (W5_REG_BASE + 0x114)
  440. #define W5_RET_ENC_WR_PTR (W5_REG_BASE + 0x118)
  441. #define W5_RET_ENC_MIN_FB_NUM (W5_REG_BASE + 0x11C)
  442. #define W5_RET_ENC_MIN_SRC_BUF_NUM (W5_REG_BASE + 0x120)
  443. #define W5_RET_ENC_PIC_TYPE (W5_REG_BASE + 0x124)
  444. #define W5_RET_ENC_PIC_POC (W5_REG_BASE + 0x128)
  445. #define W5_RET_ENC_PIC_IDX (W5_REG_BASE + 0x12C)
  446. #define W5_RET_ENC_PIC_SLICE_NUM (W5_REG_BASE + 0x130)
  447. #define W5_RET_ENC_PIC_SKIP (W5_REG_BASE + 0x134)
  448. #define W5_RET_ENC_PIC_NUM_INTRA (W5_REG_BASE + 0x138)
  449. #define W5_RET_ENC_PIC_NUM_MERGE (W5_REG_BASE + 0x13C)
  450. #define W5_RET_ENC_PIC_NUM_SKIP (W5_REG_BASE + 0x144)
  451. #define W5_RET_ENC_PIC_AVG_CTU_QP (W5_REG_BASE + 0x148)
  452. #define W5_RET_ENC_PIC_BYTE (W5_REG_BASE + 0x14C)
  453. #define W5_RET_ENC_GOP_PIC_IDX (W5_REG_BASE + 0x150)
  454. #define W5_RET_ENC_USED_SRC_IDX (W5_REG_BASE + 0x154)
  455. #define W5_RET_ENC_PIC_NUM (W5_REG_BASE + 0x158)
  456. #define W5_RET_ENC_VCL_NUT (W5_REG_BASE + 0x15C)
  457. #define W5_RET_ENC_PREPARE_CYCLE (W5_REG_BASE + 0x1C0)
  458. #define W5_RET_ENC_PROCESSING_CYCLE (W5_REG_BASE + 0x1C4)
  459. #define W5_RET_ENC_ENCODING_CYCLE (W5_REG_BASE + 0x1C8)
  460. #define W5_RET_ENC_WARN_INFO (W5_REG_BASE + 0x1D4)
  461. #define W5_RET_ENC_ERR_INFO (W5_REG_BASE + 0x1D8)
  462. #define W5_RET_ENC_ENCODING_SUCCESS (W5_REG_BASE + 0x1DC)
  463. #define W5_CMD_QUERY_REPORT_BASE (W5_REG_BASE + 0x17C) // FIX ME
  464. /************************************************************************/
  465. /* ENCODER - QUERY (GET_BW_REPORT) */
  466. /************************************************************************/
  467. #define RET_QUERY_BW_PRP_AXI_READ (W5_REG_BASE + 0x118)
  468. #define RET_QUERY_BW_PRP_AXI_WRITE (W5_REG_BASE + 0x11C)
  469. #define RET_QUERY_BW_FBD_Y_AXI_READ (W5_REG_BASE + 0x120)
  470. #define RET_QUERY_BW_FBC_Y_AXI_WRITE (W5_REG_BASE + 0x124)
  471. #define RET_QUERY_BW_FBD_C_AXI_READ (W5_REG_BASE + 0x128)
  472. #define RET_QUERY_BW_FBC_C_AXI_WRITE (W5_REG_BASE + 0x12C)
  473. #define RET_QUERY_BW_PRI_AXI_READ (W5_REG_BASE + 0x130)
  474. #define RET_QUERY_BW_PRI_AXI_WRITE (W5_REG_BASE + 0x134)
  475. #define RET_QUERY_BW_SEC_AXI_READ (W5_REG_BASE + 0x138)
  476. #define RET_QUERY_BW_SEC_AXI_WRITE (W5_REG_BASE + 0x13C)
  477. #define RET_QUERY_BW_PROC_AXI_READ (W5_REG_BASE + 0x140)
  478. #define RET_QUERY_BW_PROC_AXI_WRITE (W5_REG_BASE + 0x144)
  479. #endif /* __WAVE510_REGISTER_DEFINE_H__ */