wave5.c 111 KB

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  1. // SPDX-License-Identifier: LGPL-2.1 OR BSD-3-Clause
  2. #include "product.h"
  3. #include "wave/common/common.h"
  4. #include "wave/common/common_vpuconfig.h"
  5. #include "wave/wave5/wave5.h"
  6. #include "vpuerror.h"
  7. #include "wave/wave5/wave5_regdefine.h"
  8. void Wave5BitIssueCommand(CodecInst* instance, Uint32 cmd)
  9. {
  10. Uint32 instanceIndex = 0;
  11. Uint32 codecMode = 0;
  12. Uint32 coreIdx;
  13. if (instance != NULL) {
  14. instanceIndex = instance->instIndex;
  15. codecMode = instance->codecMode;
  16. }
  17. coreIdx = instance->coreIdx;
  18. VpuWriteReg(coreIdx, W5_CMD_INSTANCE_INFO, (codecMode<<16)|(instanceIndex&0xffff));
  19. VpuWriteReg(coreIdx, W5_VPU_BUSY_STATUS, 1);
  20. VpuWriteReg(coreIdx, W5_COMMAND, cmd);
  21. if ((instance != NULL && instance->loggingEnable))
  22. vdi_log(coreIdx, cmd, 1);
  23. VpuWriteReg(coreIdx, W5_VPU_HOST_INT_REQ, 1);
  24. return;
  25. }
  26. static RetCode SendQuery(CodecInst* instance, QUERY_OPT queryOpt)
  27. {
  28. // Send QUERY cmd
  29. VpuWriteReg(instance->coreIdx, W5_QUERY_OPTION, queryOpt);
  30. VpuWriteReg(instance->coreIdx, W5_VPU_BUSY_STATUS, 1);
  31. Wave5BitIssueCommand(instance, W5_QUERY);
  32. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) {
  33. if (instance->loggingEnable)
  34. vdi_log(instance->coreIdx, W5_QUERY, 2);
  35. return RETCODE_VPU_RESPONSE_TIMEOUT;
  36. }
  37. if (VpuReadReg(instance->coreIdx, W5_RET_SUCCESS) == FALSE)
  38. return RETCODE_FAILURE;
  39. return RETCODE_SUCCESS;
  40. }
  41. static RetCode SetupWave5Properties(Uint32 coreIdx)
  42. {
  43. VpuAttr* pAttr = &g_VpuCoreAttributes[coreIdx];
  44. Uint32 regVal;
  45. Uint8* str;
  46. RetCode ret = RETCODE_SUCCESS;
  47. VpuWriteReg(coreIdx, W5_QUERY_OPTION, GET_VPU_INFO);
  48. VpuWriteReg(coreIdx, W5_VPU_BUSY_STATUS, 1);
  49. VpuWriteReg(coreIdx, W5_COMMAND, W5_QUERY);
  50. VpuWriteReg(coreIdx, W5_VPU_HOST_INT_REQ, 1);
  51. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) {
  52. return RETCODE_VPU_RESPONSE_TIMEOUT;
  53. }
  54. if (VpuReadReg(coreIdx, W5_RET_SUCCESS) == FALSE) {
  55. ret = RETCODE_QUERY_FAILURE;
  56. }
  57. else {
  58. regVal = VpuReadReg(coreIdx, W5_RET_PRODUCT_NAME);
  59. str = (Uint8*)&regVal;
  60. pAttr->productName[0] = str[3];
  61. pAttr->productName[1] = str[2];
  62. pAttr->productName[2] = str[1];
  63. pAttr->productName[3] = str[0];
  64. pAttr->productName[4] = 0;
  65. pAttr->productNumber = VpuReadReg(coreIdx, W5_RET_PRODUCT_VERSION);
  66. switch (pAttr->productNumber) {
  67. case WAVE510_CODE: pAttr->productId = PRODUCT_ID_510; break;
  68. case WAVE512_CODE: pAttr->productId = PRODUCT_ID_512; break;
  69. case WAVE515_CODE: pAttr->productId = PRODUCT_ID_515; break;
  70. case WAVE520_CODE: pAttr->productId = PRODUCT_ID_520; break;
  71. default: pAttr->productId = PRODUCT_ID_NONE; break;
  72. }
  73. pAttr->hwConfigDef0 = VpuReadReg(coreIdx, W5_RET_STD_DEF0);
  74. pAttr->hwConfigDef1 = VpuReadReg(coreIdx, W5_RET_STD_DEF1);
  75. pAttr->hwConfigFeature = VpuReadReg(coreIdx, W5_RET_CONF_FEATURE);
  76. pAttr->hwConfigDate = VpuReadReg(coreIdx, W5_RET_CONF_DATE);
  77. pAttr->hwConfigRev = VpuReadReg(coreIdx, W5_RET_CONF_REVISION);
  78. pAttr->hwConfigType = VpuReadReg(coreIdx, W5_RET_CONF_TYPE);
  79. pAttr->supportGDIHW = TRUE;
  80. pAttr->supportDecoders = (1<<STD_HEVC);
  81. if (pAttr->productId == PRODUCT_ID_512) {
  82. pAttr->supportDecoders |= (1<<STD_VP9);
  83. }
  84. pAttr->supportEncoders = 0;
  85. if (pAttr->productId == PRODUCT_ID_520) {
  86. pAttr->supportEncoders |= (1<<STD_HEVC);
  87. }
  88. pAttr->supportCommandQueue = TRUE;
  89. pAttr->supportFBCBWOptimization = (BOOL)((pAttr->hwConfigDef1>>15)&0x01);
  90. if (pAttr->productId == PRODUCT_ID_520)
  91. pAttr->supportWTL = FALSE;
  92. else
  93. pAttr->supportWTL = TRUE;
  94. pAttr->supportTiled2Linear = FALSE;
  95. pAttr->supportMapTypes = FALSE;
  96. pAttr->support128bitBus = TRUE;
  97. pAttr->supportThumbnailMode = TRUE;
  98. pAttr->supportEndianMask = (Uint32)((1<<VDI_LITTLE_ENDIAN) | (1<<VDI_BIG_ENDIAN) | (1<<VDI_32BIT_LITTLE_ENDIAN) | (1<<VDI_32BIT_BIG_ENDIAN) | (0xffff<<16));
  99. pAttr->supportBitstreamMode = (1<<BS_MODE_INTERRUPT) | (1<<BS_MODE_PIC_END);
  100. pAttr->framebufferCacheType = FramebufCacheNone;
  101. pAttr->bitstreamBufferMargin = 0;
  102. pAttr->numberOfVCores = MAX_NUM_VCORE;
  103. pAttr->numberOfMemProtectRgns = 10;
  104. }
  105. return ret;
  106. }
  107. RetCode Wave5VpuGetVersion(Uint32 coreIdx, Uint32* versionInfo, Uint32* revision)
  108. {
  109. Uint32 regVal;
  110. VpuWriteReg(coreIdx, W5_QUERY_OPTION, GET_VPU_INFO);
  111. VpuWriteReg(coreIdx, W5_VPU_BUSY_STATUS, 1);
  112. VpuWriteReg(coreIdx, W5_COMMAND, W5_QUERY);
  113. VpuWriteReg(coreIdx, W5_VPU_HOST_INT_REQ, 1);
  114. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) {
  115. return RETCODE_VPU_RESPONSE_TIMEOUT;
  116. }
  117. if (VpuReadReg(coreIdx, W5_RET_SUCCESS) == FALSE)
  118. return RETCODE_QUERY_FAILURE;
  119. regVal = VpuReadReg(coreIdx, W5_RET_FW_VERSION);
  120. if (versionInfo != NULL) {
  121. *versionInfo = 0;
  122. }
  123. if (revision != NULL) {
  124. *revision = regVal;
  125. }
  126. return RETCODE_SUCCESS;
  127. }
  128. RetCode Wave5VpuGetProductInfo(Uint32 coreIdx, ProductInfo *productInfo)
  129. {
  130. /* GET FIRMWARE&HARDWARE INFORMATION */
  131. VpuWriteReg(coreIdx, W5_QUERY_OPTION, GET_VPU_INFO);
  132. VpuWriteReg(coreIdx, W5_VPU_BUSY_STATUS, 1);
  133. VpuWriteReg(coreIdx, W5_COMMAND, W5_QUERY);
  134. VpuWriteReg(coreIdx, W5_VPU_HOST_INT_REQ, 1);
  135. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) {
  136. return RETCODE_VPU_RESPONSE_TIMEOUT;
  137. }
  138. if (VpuReadReg(coreIdx, W5_RET_SUCCESS) == FALSE) {
  139. return RETCODE_QUERY_FAILURE;
  140. }
  141. productInfo->fwVersion = VpuReadReg(coreIdx, W5_RET_FW_VERSION);
  142. productInfo->productName = VpuReadReg(coreIdx, W5_RET_PRODUCT_NAME);
  143. productInfo->productVersion = VpuReadReg(coreIdx, W5_RET_PRODUCT_VERSION);
  144. productInfo->customerId = VpuReadReg(coreIdx, W5_RET_CUSTOMER_ID);
  145. productInfo->stdDef0 = VpuReadReg(coreIdx, W5_RET_STD_DEF0);
  146. productInfo->stdDef1 = VpuReadReg(coreIdx, W5_RET_STD_DEF1);
  147. productInfo->confFeature = VpuReadReg(coreIdx, W5_RET_CONF_FEATURE);
  148. productInfo->configDate = VpuReadReg(coreIdx, W5_RET_CONF_DATE);
  149. productInfo->configRevision = VpuReadReg(coreIdx, W5_RET_CONF_REVISION);
  150. productInfo->configType = VpuReadReg(coreIdx, W5_RET_CONF_TYPE);
  151. productInfo->configVcore[0] = 0;
  152. productInfo->configVcore[1] = 0;
  153. productInfo->configVcore[2] = 0;
  154. productInfo->configVcore[3] = 0;
  155. return RETCODE_SUCCESS;
  156. }
  157. RetCode Wave5VpuInit(Uint32 coreIdx, void* firmware, Uint32 size)
  158. {
  159. vpu_buffer_t vb;
  160. PhysicalAddress codeBase, tempBase;
  161. PhysicalAddress taskBufBase;
  162. Uint32 codeSize, tempSize;
  163. Uint32 i, regVal, remapSize;
  164. Uint32 hwOption = 0;
  165. RetCode ret = RETCODE_SUCCESS;
  166. CodecInstHeader hdr;
  167. osal_memset((void *)&hdr, 0x00, sizeof(CodecInstHeader));
  168. vdi_get_common_memory(coreIdx, &vb);
  169. codeBase = vb.phys_addr;
  170. /* ALIGN TO 4KB */
  171. codeSize = (WAVE5_MAX_CODE_BUF_SIZE&~0xfff);
  172. if (codeSize < size*2) {
  173. return RETCODE_INSUFFICIENT_RESOURCE;
  174. }
  175. tempBase = vb.phys_addr + WAVE5_TEMPBUF_OFFSET;
  176. tempSize = WAVE5_TEMPBUF_SIZE;
  177. VLOG(INFO, "\nVPU INIT Start!!!\n");
  178. VpuWriteMem(coreIdx, codeBase, (unsigned char*)firmware, size*2, VDI_128BIT_LITTLE_ENDIAN);
  179. vdi_set_bit_firmware_to_pm(coreIdx, (Uint16*)firmware);
  180. regVal = 0;
  181. VpuWriteReg(coreIdx, W5_PO_CONF, regVal);
  182. /* Reset All blocks */
  183. regVal = 0x7ffffff;
  184. VpuWriteReg(coreIdx, W5_VPU_RESET_REQ, regVal); // Reset All blocks
  185. /* Waiting reset done */
  186. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_RESET_STATUS) == -1) {
  187. VLOG(ERR, "VPU init(W5_VPU_RESET_REQ) timeout\n");
  188. VpuWriteReg(coreIdx, W5_VPU_RESET_REQ, 0);
  189. return RETCODE_VPU_RESPONSE_TIMEOUT;
  190. }
  191. VpuWriteReg(coreIdx, W5_VPU_RESET_REQ, 0);
  192. /* clear registers */
  193. for (i=W5_CMD_REG_BASE; i<W5_CMD_REG_END; i+=4)
  194. VpuWriteReg(coreIdx, i, 0x00);
  195. /* remap page size */
  196. remapSize = (codeSize >> 12) &0x1ff;
  197. regVal = 0x80000000 | (WAVE5_AXI_ID<<20) | (0 << 16) | (W5_REMAP_CODE_INDEX<<12) | (1<<11) | remapSize;
  198. VpuWriteReg(coreIdx, W5_VPU_REMAP_CTRL, regVal);
  199. VpuWriteReg(coreIdx, W5_VPU_REMAP_VADDR, 0x00000000); /* DO NOT CHANGE! */
  200. VpuWriteReg(coreIdx, W5_VPU_REMAP_PADDR, codeBase);
  201. VpuWriteReg(coreIdx, W5_ADDR_CODE_BASE, codeBase);
  202. VpuWriteReg(coreIdx, W5_CODE_SIZE, codeSize);
  203. VpuWriteReg(coreIdx, W5_CODE_PARAM, (WAVE5_AXI_ID<<4) | 0);
  204. VpuWriteReg(coreIdx, W5_ADDR_TEMP_BASE, tempBase);
  205. VpuWriteReg(coreIdx, W5_TEMP_SIZE, tempSize);
  206. VpuWriteReg(coreIdx, W5_TIMEOUT_CNT, 0xffff);
  207. VpuWriteReg(coreIdx, W5_HW_OPTION, hwOption);
  208. /* Interrupt */
  209. // decoder
  210. regVal = (1<<W5_INT_INIT_SEQ);
  211. regVal |= (1<<W5_INT_DEC_PIC);
  212. regVal |= (1<<W5_INT_BSBUF_EMPTY);
  213. VpuWriteReg(coreIdx, W5_VPU_VINT_ENABLE, regVal);
  214. VpuWriteReg(coreIdx, W5_CMD_INIT_NUM_TASK_BUF, COMMAND_QUEUE_DEPTH);
  215. VpuWriteReg(coreIdx, W5_CMD_INIT_TASK_BUF_SIZE, ONE_TASKBUF_SIZE_FOR_CQ);
  216. vdi_get_common_memory(coreIdx, &vb);
  217. for (i = 0; i < COMMAND_QUEUE_DEPTH; i++) {
  218. taskBufBase = vb.phys_addr + WAVE5_TASK_BUF_OFFSET + (i*ONE_TASKBUF_SIZE_FOR_CQ);
  219. VpuWriteReg(coreIdx, W5_CMD_INIT_ADDR_TASK_BUF0 + (i*4), taskBufBase);
  220. }
  221. if (vdi_get_sram_memory(coreIdx, &vb) < 0) // get SRAM base/size
  222. return RETCODE_INSUFFICIENT_RESOURCE;
  223. VpuWriteReg(coreIdx, W5_ADDR_SEC_AXI, vb.phys_addr);
  224. VpuWriteReg(coreIdx, W5_SEC_AXI_SIZE, vb.size);
  225. hdr.coreIdx = coreIdx;
  226. VpuWriteReg(coreIdx, W5_VPU_BUSY_STATUS, 1);
  227. VpuWriteReg(coreIdx, W5_COMMAND, W5_INIT_VPU);
  228. VpuWriteReg(coreIdx, W5_VPU_REMAP_CORE_START, 1);
  229. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) {
  230. VLOG(ERR, "VPU init(W5_VPU_REMAP_CORE_START) timeout\n");
  231. return RETCODE_VPU_RESPONSE_TIMEOUT;
  232. }
  233. regVal = VpuReadReg(coreIdx, W5_RET_SUCCESS);
  234. if (regVal == 0) {
  235. Uint32 reasonCode = VpuReadReg(coreIdx, W5_RET_FAIL_REASON);
  236. VLOG(ERR, "VPU init(W5_RET_SUCCESS) failed(%d) REASON CODE(%08x)\n", regVal, reasonCode);
  237. return RETCODE_FAILURE;
  238. }
  239. ret = SetupWave5Properties(coreIdx);
  240. return ret;
  241. }
  242. RetCode Wave5VpuBuildUpDecParam(CodecInst* instance, DecOpenParam* param)
  243. {
  244. RetCode ret = RETCODE_SUCCESS;
  245. DecInfo* pDecInfo;
  246. VpuAttr* pAttr = &g_VpuCoreAttributes[instance->coreIdx];
  247. Uint32 bsEndian = 0;
  248. pDecInfo = VPU_HANDLE_TO_DECINFO(instance);
  249. pDecInfo->streamRdPtrRegAddr = W5_RET_DEC_BS_RD_PTR;
  250. pDecInfo->streamWrPtrRegAddr = W5_BS_WR_PTR;
  251. pDecInfo->frameDisplayFlagRegAddr = W5_RET_DEC_DISP_FLAG;
  252. pDecInfo->currentPC = W5_VCPU_CUR_PC;
  253. pDecInfo->busyFlagAddr = W5_VPU_BUSY_STATUS;
  254. if ((pAttr->supportDecoders&(1<<param->bitstreamFormat)) == 0)
  255. return RETCODE_NOT_SUPPORTED_FEATURE;
  256. pDecInfo->seqChangeMask = param->bitstreamFormat == STD_HEVC ?
  257. SEQ_CHANGE_ENABLE_ALL_HEVC : SEQ_CHANGE_ENABLE_ALL_VP9;
  258. pDecInfo->targetSubLayerId = HEVC_MAX_SUB_LAYER_ID;
  259. if (param->vbWork.size > 0) {
  260. pDecInfo->vbWork = param->vbWork;
  261. pDecInfo->workBufferAllocExt = TRUE;
  262. vdi_attach_dma_memory(instance->coreIdx, &param->vbWork);
  263. }
  264. else {
  265. if (instance->productId == PRODUCT_ID_512) {
  266. pDecInfo->vbWork.size = WAVE512DEC_WORKBUF_SIZE;
  267. }
  268. else {
  269. pDecInfo->vbWork.size = WAVE510DEC_WORKBUF_SIZE;
  270. }
  271. pDecInfo->workBufferAllocExt = FALSE;
  272. if (vdi_allocate_dma_memory(instance->coreIdx, &pDecInfo->vbWork) < 0) {
  273. pDecInfo->vbWork.base = 0;
  274. pDecInfo->vbWork.phys_addr = 0;
  275. pDecInfo->vbWork.size = 0;
  276. pDecInfo->vbWork.virt_addr = 0;
  277. return RETCODE_INSUFFICIENT_RESOURCE;
  278. }
  279. }
  280. vdi_clear_memory(instance->coreIdx, pDecInfo->vbWork.phys_addr, pDecInfo->vbWork.size, 0);
  281. VpuWriteReg(instance->coreIdx, W5_ADDR_WORK_BASE, pDecInfo->vbWork.phys_addr);
  282. VpuWriteReg(instance->coreIdx, W5_WORK_SIZE, pDecInfo->vbWork.size);
  283. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_BS_START_ADDR, pDecInfo->streamBufStartAddr);
  284. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_BS_SIZE, pDecInfo->streamBufSize);
  285. bsEndian = vdi_convert_endian(instance->coreIdx, param->streamEndian);
  286. /* NOTE: When endian mode is 0, SDMA reads MSB first */
  287. bsEndian = (~bsEndian&VDI_128BIT_ENDIAN_MASK);
  288. VpuWriteReg(instance->coreIdx, W5_CMD_BS_PARAM, bsEndian);
  289. VpuWriteReg(instance->coreIdx, W5_VPU_BUSY_STATUS, 1);
  290. VpuWriteReg(instance->coreIdx, W5_RET_SUCCESS, 0); //for debug
  291. Wave5BitIssueCommand(instance, W5_CREATE_INSTANCE);
  292. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) { // Check QUEUE_DONE
  293. if (instance->loggingEnable)
  294. vdi_log(instance->coreIdx, W5_CREATE_INSTANCE, 2);
  295. vdi_free_dma_memory(instance->coreIdx, &pDecInfo->vbWork);
  296. return RETCODE_VPU_RESPONSE_TIMEOUT;
  297. }
  298. if (VpuReadReg(instance->coreIdx, W5_RET_SUCCESS) == FALSE) { // FAILED for adding into VCPU QUEUE
  299. vdi_free_dma_memory(instance->coreIdx, &pDecInfo->vbWork);
  300. ret = RETCODE_FAILURE;
  301. }
  302. return ret;
  303. }
  304. RetCode Wave5VpuDecInitSeq(CodecInst* instance)
  305. {
  306. RetCode ret = RETCODE_SUCCESS;
  307. DecInfo* pDecInfo;
  308. Uint32 cmdOption = INIT_SEQ_NORMAL, bsOption;
  309. Uint32 regVal;
  310. if (instance == NULL)
  311. return RETCODE_INVALID_PARAM;
  312. pDecInfo = VPU_HANDLE_TO_DECINFO(instance);
  313. if (pDecInfo->thumbnailMode)
  314. cmdOption = INIT_SEQ_W_THUMBNAIL;
  315. /* Set attributes of bitstream buffer controller */
  316. bsOption = 0;
  317. switch (pDecInfo->openParam.bitstreamMode) {
  318. case BS_MODE_INTERRUPT:
  319. if(pDecInfo->seqInitEscape == TRUE)
  320. bsOption = BSOPTION_ENABLE_EXPLICIT_END;
  321. break;
  322. case BS_MODE_PIC_END:
  323. bsOption = BSOPTION_ENABLE_EXPLICIT_END;
  324. break;
  325. default:
  326. return RETCODE_INVALID_PARAM;
  327. }
  328. if (pDecInfo->streamEndflag == 1)
  329. bsOption = 3;
  330. VpuWriteReg(instance->coreIdx, W5_BS_RD_PTR, pDecInfo->streamRdPtr);
  331. VpuWriteReg(instance->coreIdx, W5_BS_WR_PTR, pDecInfo->streamWrPtr);
  332. VpuWriteReg(instance->coreIdx, W5_BS_OPTION, (1<<31) | bsOption);
  333. VpuWriteReg(instance->coreIdx, W5_COMMAND_OPTION, cmdOption);
  334. Wave5BitIssueCommand(instance, W5_INIT_SEQ);
  335. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) { // Check QUEUE_DONE
  336. if (instance->loggingEnable)
  337. vdi_log(instance->coreIdx, W5_INIT_SEQ, 2);
  338. return RETCODE_VPU_RESPONSE_TIMEOUT;
  339. }
  340. regVal = VpuReadReg(instance->coreIdx, W5_RET_QUEUE_STATUS);
  341. pDecInfo->instanceQueueCount = (regVal>>16)&0xff;
  342. pDecInfo->totalQueueCount = (regVal & 0xffff);
  343. if (VpuReadReg(instance->coreIdx, W5_RET_SUCCESS) == FALSE) { // FAILED for adding a command into VCPU QUEUE
  344. if (VpuReadReg(instance->coreIdx, W5_RET_FAIL_REASON) == 1)
  345. ret = RETCODE_QUEUEING_FAILURE;
  346. else
  347. ret = RETCODE_FAILURE;
  348. }
  349. return ret;
  350. }
  351. static void GetDecSequenceResult(CodecInst* instance, DecInitialInfo* info)
  352. {
  353. DecInfo* pDecInfo = &instance->CodecInfo->decInfo;
  354. Uint32 regVal;
  355. Uint32 profileCompatibilityFlag;
  356. Uint32 left, right, top, bottom;
  357. info->rdPtr = VpuReadReg(instance->coreIdx, W5_RET_DEC_BS_RD_PTR);
  358. //info->wrPtr = VpuReadReg(instance->coreIdx, W4_BS_WR_PTR);
  359. pDecInfo->streamRdPtr = VpuReadReg(instance->coreIdx, W5_RET_DEC_BS_RD_PTR);
  360. pDecInfo->frameDisplayFlag = VpuReadReg(instance->coreIdx, W5_RET_DEC_DISP_FLAG);
  361. /*regVal = VpuReadReg(instance->coreIdx, W4_BS_OPTION);
  362. pDecInfo->streamEndflag = (regVal&0x02) ? TRUE : FALSE;*/
  363. regVal = VpuReadReg(instance->coreIdx, W5_RET_DEC_PIC_SIZE);
  364. info->picWidth = ( (regVal >> 16) & 0xffff );
  365. info->picHeight = ( regVal & 0xffff );
  366. info->minFrameBufferCount = VpuReadReg(instance->coreIdx, W5_RET_DEC_FRAMEBUF_NEEDED);
  367. info->frameBufDelay = VpuReadReg(instance->coreIdx, W5_RET_DEC_NUM_REORDER_DELAY);
  368. regVal = VpuReadReg(instance->coreIdx, W5_RET_DEC_CROP_LEFT_RIGHT);
  369. left = (regVal >> 16) & 0xffff;
  370. right = regVal & 0xffff;
  371. regVal = VpuReadReg(instance->coreIdx, W5_RET_DEC_CROP_TOP_BOTTOM);
  372. top = (regVal >> 16) & 0xffff;
  373. bottom = regVal & 0xffff;
  374. info->picCropRect.left = left;
  375. info->picCropRect.right = info->picWidth - right;
  376. info->picCropRect.top = top;
  377. info->picCropRect.bottom = info->picHeight - bottom;
  378. regVal = VpuReadReg(instance->coreIdx, W5_RET_DEC_SEQ_PARAM);
  379. profileCompatibilityFlag = (regVal>>12)&0xff;
  380. info->profile = (regVal >> 24)&0x1f;
  381. info->level = regVal & 0xff;
  382. info->tier = (regVal >> 29)&0x01;
  383. info->maxSubLayers = (regVal >> 21)&0x07;
  384. info->fRateNumerator = VpuReadReg(instance->coreIdx, W5_RET_DEC_FRAME_RATE_NR);
  385. info->fRateDenominator = VpuReadReg(instance->coreIdx, W5_RET_DEC_FRAME_RATE_DR);
  386. regVal = VpuReadReg(instance->coreIdx, W5_RET_DEC_COLOR_SAMPLE_INFO);
  387. info->chromaFormatIDC = (regVal>>8)&0x0f;
  388. info->lumaBitdepth = (regVal>>0)&0x0f;
  389. info->chromaBitdepth = (regVal>>4)&0x0f;
  390. info->aspectRateInfo = (regVal>>16)&0xff;
  391. info->isExtSAR = (info->aspectRateInfo == 255 ? TRUE : FALSE);
  392. if (info->isExtSAR == TRUE) {
  393. info->aspectRateInfo = VpuReadReg(instance->coreIdx, W5_RET_DEC_ASPECT_RATIO); /* [0:15] - vertical size, [16:31] - horizontal size */
  394. }
  395. info->bitRate = VpuReadReg(instance->coreIdx, W5_RET_DEC_BIT_RATE);
  396. if ( instance->codecMode == C7_HEVC_DEC ) {
  397. /* Guessing Profile */
  398. if (info->profile == 0) {
  399. if ((profileCompatibilityFlag&0x06) == 0x06) info->profile = 1; /* Main profile */
  400. else if ((profileCompatibilityFlag&0x04) == 0x04) info->profile = 2; /* Main10 profile */
  401. else if ((profileCompatibilityFlag&0x08) == 0x08) info->profile = 3; /* Main Still Picture profile */
  402. else info->profile = 1; /* For old version HM */
  403. }
  404. }
  405. return;
  406. }
  407. RetCode Wave5VpuDecGetSeqInfo(CodecInst* instance, DecInitialInfo* info)
  408. {
  409. RetCode ret = RETCODE_SUCCESS;
  410. Uint32 regVal, i;
  411. DecInfo* pDecInfo;
  412. pDecInfo = VPU_HANDLE_TO_DECINFO(instance);
  413. // Send QUERY cmd
  414. ret = SendQuery(instance, GET_RESULT);
  415. if (ret != RETCODE_SUCCESS) {
  416. if (VpuReadReg(instance->coreIdx, W5_RET_FAIL_REASON) == WAVE5_RESULT_NOT_READY)
  417. return RETCODE_REPORT_NOT_READY;
  418. else
  419. return RETCODE_QUERY_FAILURE;
  420. }
  421. if (instance->loggingEnable)
  422. vdi_log(instance->coreIdx, W5_INIT_SEQ, 0);
  423. regVal = VpuReadReg(instance->coreIdx, W5_RET_QUEUE_STATUS);
  424. pDecInfo->instanceQueueCount = (regVal>>16)&0xff;
  425. pDecInfo->totalQueueCount = (regVal & 0xffff);
  426. if (VpuReadReg(instance->coreIdx, W5_RET_DEC_DECODING_SUCCESS) != 1) {
  427. info->seqInitErrReason = VpuReadReg(instance->coreIdx, W5_RET_DEC_ERR_INFO);
  428. if (info->seqInitErrReason == WAVE5_SYSERR_ACCESS_VIOLATION_HW)
  429. ret = RETCODE_MEMORY_ACCESS_VIOLATION;
  430. else
  431. ret = RETCODE_FAILURE;
  432. }
  433. // Get Sequence Info
  434. info->userDataSize = 0;
  435. info->userDataNum = 0;
  436. info->userDataHeader = VpuReadReg(instance->coreIdx, W5_RET_DEC_USERDATA_IDC);
  437. if (info->userDataHeader != 0) {
  438. regVal = info->userDataHeader;
  439. for (i=0; i<32; i++) {
  440. if (regVal & (1<<i)) {
  441. info->userDataNum++;
  442. }
  443. }
  444. info->userDataSize = pDecInfo->userDataBufSize;
  445. }
  446. regVal = VpuReadReg(instance->coreIdx, W5_RET_DONE_INSTANCE_INFO);
  447. GetDecSequenceResult(instance, info);
  448. return ret;
  449. }
  450. RetCode Wave5VpuDecRegisterFramebuffer(CodecInst* inst, FrameBuffer* fbArr, TiledMapType mapType, Uint32 count)
  451. {
  452. RetCode ret = RETCODE_SUCCESS;
  453. DecInfo* pDecInfo = &inst->CodecInfo->decInfo;
  454. DecInitialInfo* sequenceInfo = &inst->CodecInfo->decInfo.initialInfo;
  455. Int32 q, j, i, remain, idx;
  456. Uint32 mvCount;
  457. Uint32 k;
  458. Int32 coreIdx, startNo, endNo;
  459. Uint32 regVal, cbcrInterleave, nv21, picSize;
  460. Uint32 endian, yuvFormat = 0;
  461. Uint32 addrY, addrCb, addrCr;
  462. Uint32 mvColSize, fbcYTblSize, fbcCTblSize;
  463. vpu_buffer_t vbBuffer;
  464. Uint32 stride;
  465. Uint32 colorFormat = 0;
  466. Uint32 outputFormat = 0;
  467. Uint32 axiID;
  468. coreIdx = inst->coreIdx;
  469. axiID = pDecInfo->openParam.virtAxiID;
  470. cbcrInterleave = pDecInfo->openParam.cbcrInterleave;
  471. nv21 = pDecInfo->openParam.nv21;
  472. mvColSize = fbcYTblSize = fbcCTblSize = 0;
  473. if (mapType == COMPRESSED_FRAME_MAP) {
  474. cbcrInterleave = 0;
  475. nv21 = 0;
  476. if (inst->codecMode == C7_HEVC_DEC) {
  477. mvColSize = WAVE4_DEC_HEVC_MVCOL_BUF_SIZE(pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight);
  478. }
  479. else if(inst->codecMode == C7_VP9_DEC) {
  480. mvColSize = WAVE4_DEC_VP9_MVCOL_BUF_SIZE(pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight);
  481. }
  482. else {
  483. /* Unknown codec */
  484. return RETCODE_NOT_SUPPORTED_FEATURE;
  485. }
  486. mvColSize = VPU_ALIGN16(mvColSize);
  487. vbBuffer.phys_addr = 0;
  488. if (inst->codecMode == HEVC_DEC || inst->codecMode == C7_HEVC_DEC || inst->codecMode == C7_VP9_DEC) {
  489. vbBuffer.size = ((mvColSize+4095)&~4095)+4096; /* 4096 is a margin */
  490. mvCount = count;
  491. for (k=0 ; k<mvCount ; k++) {
  492. if ( pDecInfo->vbMV[k].size == 0) {
  493. if (vdi_allocate_dma_memory(inst->coreIdx, &vbBuffer) < 0)
  494. return RETCODE_INSUFFICIENT_RESOURCE;
  495. pDecInfo->vbMV[k] = vbBuffer;
  496. }
  497. }
  498. }
  499. //VP9 Decoded size : 64 aligned.
  500. if (inst->codecMode == C7_HEVC_DEC){
  501. fbcYTblSize = WAVE4_FBC_LUMA_TABLE_SIZE(pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight);
  502. }
  503. else if (inst->codecMode == C7_VP9_DEC) {
  504. fbcYTblSize = WAVE4_FBC_LUMA_TABLE_SIZE(VPU_ALIGN64(pDecInfo->initialInfo.picWidth), VPU_ALIGN64(pDecInfo->initialInfo.picHeight));
  505. }
  506. else {
  507. /* Unknown codec */
  508. return RETCODE_NOT_SUPPORTED_FEATURE;
  509. }
  510. fbcYTblSize = VPU_ALIGN16(fbcYTblSize);
  511. vbBuffer.phys_addr = 0;
  512. vbBuffer.size = ((fbcYTblSize+4095)&~4095)+4096;
  513. for (k=0 ; k<count ; k++) {
  514. if ( pDecInfo->vbFbcYTbl[k].size == 0) {
  515. if (vdi_allocate_dma_memory(inst->coreIdx, &vbBuffer) < 0)
  516. return RETCODE_INSUFFICIENT_RESOURCE;
  517. pDecInfo->vbFbcYTbl[k] = vbBuffer;
  518. }
  519. }
  520. if (inst->codecMode == C7_HEVC_DEC) {
  521. fbcCTblSize = WAVE4_FBC_CHROMA_TABLE_SIZE(pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight);
  522. }
  523. else if (inst->codecMode == C7_VP9_DEC) {
  524. fbcCTblSize = WAVE4_FBC_CHROMA_TABLE_SIZE(VPU_ALIGN64(pDecInfo->initialInfo.picWidth), VPU_ALIGN64(pDecInfo->initialInfo.picHeight));
  525. }
  526. else {
  527. /* Unknown codec */
  528. return RETCODE_NOT_SUPPORTED_FEATURE;
  529. }
  530. fbcCTblSize = VPU_ALIGN16(fbcCTblSize);
  531. vbBuffer.phys_addr = 0;
  532. vbBuffer.size = ((fbcCTblSize+4095)&~4095)+4096;
  533. for (k=0 ; k<count ; k++) {
  534. if ( pDecInfo->vbFbcCTbl[k].size == 0) {
  535. if (vdi_allocate_dma_memory(inst->coreIdx, &vbBuffer) < 0)
  536. return RETCODE_INSUFFICIENT_RESOURCE;
  537. pDecInfo->vbFbcCTbl[k] = vbBuffer;
  538. }
  539. }
  540. picSize = (pDecInfo->initialInfo.picWidth<<16)|(pDecInfo->initialInfo.picHeight);
  541. }
  542. else
  543. {
  544. picSize = (pDecInfo->initialInfo.picWidth<<16)|(pDecInfo->initialInfo.picHeight);
  545. }
  546. endian = vdi_convert_endian(coreIdx, fbArr[0].endian) & VDI_128BIT_ENDIAN_MASK;
  547. VpuWriteReg(coreIdx, W5_PIC_SIZE, picSize);
  548. yuvFormat = 0; /* YUV420 8bit */
  549. if (mapType == LINEAR_FRAME_MAP) {
  550. BOOL justified = W4_WTL_RIGHT_JUSTIFIED;
  551. Uint32 formatNo = W4_WTL_PIXEL_8BIT;
  552. switch (pDecInfo->wtlFormat) {
  553. case FORMAT_420_P10_16BIT_MSB:
  554. justified = W4_WTL_RIGHT_JUSTIFIED;
  555. formatNo = W4_WTL_PIXEL_16BIT;
  556. break;
  557. case FORMAT_420_P10_16BIT_LSB:
  558. justified = W4_WTL_LEFT_JUSTIFIED;
  559. formatNo = W4_WTL_PIXEL_16BIT;
  560. break;
  561. case FORMAT_420_P10_32BIT_MSB:
  562. justified = W4_WTL_RIGHT_JUSTIFIED;
  563. formatNo = W4_WTL_PIXEL_32BIT;
  564. break;
  565. case FORMAT_420_P10_32BIT_LSB:
  566. justified = W4_WTL_LEFT_JUSTIFIED;
  567. formatNo = W4_WTL_PIXEL_32BIT;
  568. break;
  569. default:
  570. break;
  571. }
  572. yuvFormat = justified<<2 | formatNo;
  573. }
  574. stride = fbArr[0].stride;
  575. if (mapType == COMPRESSED_FRAME_MAP) {
  576. if ( pDecInfo->chFbcFrameIdx != -1 )
  577. stride = fbArr[pDecInfo->chFbcFrameIdx].stride;
  578. } else {
  579. if ( pDecInfo->chBwbFrameIdx != -1 )
  580. stride = fbArr[pDecInfo->chBwbFrameIdx].stride;
  581. }
  582. if (mapType == LINEAR_FRAME_MAP) {
  583. outputFormat = 0;
  584. outputFormat |= (nv21 << 1);
  585. outputFormat |= (cbcrInterleave << 0);
  586. }
  587. regVal =
  588. ((mapType == LINEAR_FRAME_MAP) << 28) |
  589. (axiID << 24) |
  590. (1<< 23) | /* PIXEL ORDER in 128bit. first pixel in low address */
  591. (yuvFormat << 20) |
  592. (colorFormat << 19) |
  593. (outputFormat << 16) |
  594. (stride);
  595. VpuWriteReg(coreIdx, W5_COMMON_PIC_INFO, regVal);
  596. remain = count;
  597. q = (remain+7)/8;
  598. idx = 0;
  599. for (j=0; j<q; j++) {
  600. regVal = (pDecInfo->openParam.fbc_mode<<20)|(endian<<16) | (j==q-1)<<4 | ((j==0)<<3) ;
  601. VpuWriteReg(coreIdx, W5_SFB_OPTION, regVal);
  602. startNo = j*8;
  603. endNo = startNo + (remain>=8 ? 8 : remain) - 1;
  604. VpuWriteReg(coreIdx, W5_SET_FB_NUM, (startNo<<8)|endNo);
  605. for (i=0; i<8 && i<remain; i++) {
  606. if (mapType == LINEAR_FRAME_MAP && pDecInfo->openParam.cbcrOrder == CBCR_ORDER_REVERSED) {
  607. addrY = fbArr[i+startNo].bufY;
  608. addrCb = fbArr[i+startNo].bufCr;
  609. addrCr = fbArr[i+startNo].bufCb;
  610. }
  611. else {
  612. addrY = fbArr[i+startNo].bufY;
  613. addrCb = fbArr[i+startNo].bufCb;
  614. addrCr = fbArr[i+startNo].bufCr;
  615. }
  616. VpuWriteReg(coreIdx, W5_ADDR_LUMA_BASE0 + (i<<4), addrY);
  617. VpuWriteReg(coreIdx, W5_ADDR_CB_BASE0 + (i<<4), addrCb);
  618. APIDPRINT("REGISTER FB[%02d] Y(0x%08x), Cb(0x%08x) ", i, addrY, addrCb);
  619. if (mapType == COMPRESSED_FRAME_MAP) {
  620. VpuWriteReg(coreIdx, W5_ADDR_FBC_Y_OFFSET0 + (i<<4), pDecInfo->vbFbcYTbl[idx].phys_addr); /* Luma FBC offset table */
  621. VpuWriteReg(coreIdx, W5_ADDR_FBC_C_OFFSET0 + (i<<4), pDecInfo->vbFbcCTbl[idx].phys_addr); /* Chroma FBC offset table */
  622. VpuWriteReg(coreIdx, W5_ADDR_MV_COL0 + (i<<2), pDecInfo->vbMV[idx].phys_addr);
  623. APIDPRINT("Yo(0x%08x) Co(0x%08x), Mv(0x%08x)\n",
  624. pDecInfo->vbFbcYTbl[idx].phys_addr,
  625. pDecInfo->vbFbcCTbl[idx].phys_addr,
  626. pDecInfo->vbMV[idx].phys_addr);
  627. }
  628. else {
  629. VpuWriteReg(coreIdx, W5_ADDR_CR_BASE0 + (i<<4), addrCr);
  630. VpuWriteReg(coreIdx, W5_ADDR_FBC_C_OFFSET0 + (i<<4), 0);
  631. VpuWriteReg(coreIdx, W5_ADDR_MV_COL0 + (i<<2), 0);
  632. APIDPRINT("Cr(0x%08x)\n", addrCr);
  633. }
  634. idx++;
  635. }
  636. remain -= i;
  637. Wave5BitIssueCommand(inst, W5_SET_FB);
  638. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) {
  639. return RETCODE_VPU_RESPONSE_TIMEOUT;
  640. }
  641. }
  642. regVal = VpuReadReg(coreIdx, W5_RET_SUCCESS);
  643. if (regVal == 0) {
  644. return RETCODE_FAILURE;
  645. }
  646. if (ConfigSecAXIWave(coreIdx, inst->codecMode,
  647. &pDecInfo->secAxiInfo, pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight,
  648. sequenceInfo->profile, sequenceInfo->level) == 0) {
  649. return RETCODE_INSUFFICIENT_RESOURCE;
  650. }
  651. return ret;
  652. }
  653. RetCode Wave5VpuDecUpdateFramebuffer(CodecInst* inst, FrameBuffer* fbcFb, FrameBuffer* linearFb, Int32 mvIndex, Int32 picWidth, Int32 picHeight)
  654. {
  655. RetCode ret = RETCODE_SUCCESS;
  656. DecInfo* pDecInfo = &inst->CodecInfo->decInfo;
  657. DecInitialInfo* sequenceInfo = &inst->CodecInfo->decInfo.initialInfo;
  658. Int8 fbcIndex, linearIndex;
  659. Uint32 coreIdx, regVal;
  660. Uint32 mvColSize, fbcYTblSize, fbcCTblSize;
  661. Uint32 linearStride, fbcStride;
  662. vpu_buffer_t* pvbMv = NULL;
  663. vpu_buffer_t* pvbFbcYOffset;
  664. vpu_buffer_t* pvbFbcCOffset;
  665. CodStd codec;
  666. coreIdx = inst->coreIdx;
  667. fbcIndex = (fbcFb == NULL) ? -1 : fbcFb->myIndex;
  668. linearIndex = (linearFb == NULL) ? -1 : linearFb->myIndex - pDecInfo->numFbsForDecoding;
  669. mvColSize = fbcYTblSize = fbcCTblSize = 0;
  670. codec = pDecInfo->openParam.bitstreamFormat;
  671. if (codec == STD_HEVC) {
  672. return RETCODE_NOT_SUPPORTED_FEATURE;
  673. }
  674. if (codec == STD_HEVC) {
  675. mvColSize = WAVE4_DEC_HEVC_MVCOL_BUF_SIZE(picWidth, picHeight);
  676. }
  677. else if(codec == STD_VP9) {
  678. mvColSize = WAVE4_DEC_VP9_MVCOL_BUF_SIZE(picWidth, picHeight);
  679. }
  680. else {
  681. return RETCODE_NOT_SUPPORTED_FEATURE;
  682. }
  683. if (fbcFb != NULL) {
  684. pDecInfo->frameBufPool[fbcIndex] = *fbcFb;
  685. }
  686. if (linearFb != NULL) {
  687. pDecInfo->frameBufPool[pDecInfo->numFbsForDecoding + linearIndex] = *linearFb;
  688. }
  689. if (mvIndex >= 0) {
  690. pvbMv = &pDecInfo->vbMV[mvIndex];
  691. vdi_free_dma_memory(inst->coreIdx, pvbMv);
  692. pvbMv->size = ((mvColSize+4095)&~4095) + 4096;
  693. if (vdi_allocate_dma_memory(inst->coreIdx, pvbMv) < 0) {
  694. return RETCODE_INSUFFICIENT_RESOURCE;
  695. }
  696. }
  697. /* Reallocate FBC offset tables */
  698. if (codec == STD_HEVC){
  699. fbcYTblSize = WAVE4_FBC_LUMA_TABLE_SIZE(picWidth, picHeight);
  700. }
  701. else if (codec == STD_VP9) {
  702. //VP9 Decoded size : 64 aligned.
  703. fbcYTblSize = WAVE4_FBC_LUMA_TABLE_SIZE(VPU_ALIGN64(picWidth), VPU_ALIGN64(picHeight));
  704. }
  705. else {
  706. /* Unknown codec */
  707. return RETCODE_NOT_SUPPORTED_FEATURE;
  708. }
  709. if (fbcFb != NULL) {
  710. pvbFbcYOffset = &pDecInfo->vbFbcYTbl[fbcIndex];
  711. vdi_free_dma_memory(inst->coreIdx, pvbFbcYOffset);
  712. pvbFbcYOffset->phys_addr = 0;
  713. pvbFbcYOffset->size = ((fbcYTblSize+4095)&~4095)+4096;
  714. if (vdi_allocate_dma_memory(inst->coreIdx, pvbFbcYOffset) < 0) {
  715. return RETCODE_INSUFFICIENT_RESOURCE;
  716. }
  717. }
  718. if (codec == STD_HEVC) {
  719. fbcCTblSize = WAVE4_FBC_CHROMA_TABLE_SIZE(picWidth, picHeight);
  720. }
  721. else if (codec == STD_VP9) {
  722. fbcCTblSize = WAVE4_FBC_CHROMA_TABLE_SIZE(VPU_ALIGN64(picWidth), VPU_ALIGN64(picHeight));
  723. }
  724. else {
  725. /* Unknown codec */
  726. return RETCODE_NOT_SUPPORTED_FEATURE;
  727. }
  728. if (fbcFb != NULL) {
  729. pvbFbcCOffset = &pDecInfo->vbFbcCTbl[fbcIndex];
  730. vdi_free_dma_memory(inst->coreIdx, pvbFbcCOffset);
  731. pvbFbcCOffset->phys_addr = 0;
  732. pvbFbcCOffset->size = ((fbcCTblSize+4095)&~4095)+4096;
  733. if (vdi_allocate_dma_memory(inst->coreIdx, pvbFbcCOffset) < 0) {
  734. return RETCODE_INSUFFICIENT_RESOURCE;
  735. }
  736. }
  737. linearStride = linearFb == NULL ? 0 : linearFb->stride;
  738. fbcStride = fbcFb == NULL ? 0 : fbcFb->stride;
  739. regVal = linearStride<<16 | fbcStride;
  740. VpuWriteReg(coreIdx, W5_CMD_SET_FB_STRIDE, regVal);
  741. regVal = (picWidth<<16) | picHeight;
  742. VpuWriteReg(coreIdx, W5_PIC_SIZE, regVal);
  743. VLOG(INFO, "fbcIndex(%d), linearIndex(%d), mvIndex(%d)\n", fbcIndex, linearIndex, mvIndex);
  744. regVal = (mvIndex&0xff) << 16 | (linearIndex&0xff) << 8 | (fbcIndex&0xff);
  745. VpuWriteReg(coreIdx, W5_CMD_SET_FB_INDEX, regVal);
  746. VpuWriteReg(coreIdx, W5_ADDR_LUMA_BASE, linearFb == NULL ? 0 : linearFb->bufY);
  747. VpuWriteReg(coreIdx, W5_ADDR_CB_BASE, linearFb == NULL ? 0 : linearFb->bufCb);
  748. VpuWriteReg(coreIdx, W5_ADDR_CR_BASE, linearFb == NULL ? 0 : linearFb->bufCr);
  749. VpuWriteReg(coreIdx, W5_ADDR_MV_COL, pvbMv == NULL ? 0 : pvbMv->phys_addr);
  750. VpuWriteReg(coreIdx, W5_ADDR_FBC_Y_BASE, fbcFb == NULL ? 0 : fbcFb->bufY);
  751. VpuWriteReg(coreIdx, W5_ADDR_FBC_C_BASE, fbcFb == NULL ? 0 : fbcFb->bufCb);
  752. VpuWriteReg(coreIdx, W5_ADDR_FBC_Y_OFFSET, fbcFb == NULL ? 0 : pvbFbcYOffset->phys_addr);
  753. VpuWriteReg(coreIdx, W5_ADDR_FBC_C_OFFSET, fbcFb == NULL ? 0 : pvbFbcCOffset->phys_addr);
  754. VpuWriteReg(coreIdx, W5_SFB_OPTION, 1); /* UPDATE FRAMEBUFFER */
  755. Wave5BitIssueCommand(inst, W5_SET_FB);
  756. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) {
  757. return RETCODE_VPU_RESPONSE_TIMEOUT;
  758. }
  759. regVal = VpuReadReg(coreIdx, W5_RET_SUCCESS);
  760. if (regVal == 0) {
  761. return RETCODE_FAILURE;
  762. }
  763. if (ConfigSecAXIWave(coreIdx, inst->codecMode,
  764. &pDecInfo->secAxiInfo, pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight,
  765. sequenceInfo->profile, sequenceInfo->level) == 0) {
  766. return RETCODE_INSUFFICIENT_RESOURCE;
  767. }
  768. return ret;
  769. }
  770. RetCode Wave5VpuDecode(CodecInst* instance, DecParam* option)
  771. {
  772. Uint32 modeOption = DEC_PIC_NORMAL, bsOption, regVal;
  773. DecOpenParam* pOpenParam;
  774. Int32 forceLatency = -1;
  775. Int32 rdptr_valid = 0;
  776. DecInfo* pDecInfo = &instance->CodecInfo->decInfo;
  777. pOpenParam = &pDecInfo->openParam;
  778. if (pDecInfo->thumbnailMode) {
  779. modeOption = DEC_PIC_W_THUMBNAIL;
  780. }
  781. else if (option->skipframeMode) {
  782. switch (option->skipframeMode) {
  783. case 1:
  784. modeOption = SKIP_NON_IRAP;
  785. forceLatency = 0;
  786. break;
  787. case 2:
  788. modeOption = SKIP_NON_REF_PIC;
  789. break;
  790. default:
  791. // skip off
  792. break;
  793. }
  794. }
  795. if (pDecInfo->targetSubLayerId < (pDecInfo->initialInfo.maxSubLayers-1)) {
  796. modeOption = SKIP_TEMPORAL_LAYER;
  797. }
  798. if (option->craAsBlaFlag == TRUE) {
  799. modeOption |= (1<<1);
  800. }
  801. // set disable reorder
  802. if (pDecInfo->reorderEnable == FALSE) {
  803. forceLatency = 0;
  804. }
  805. // Bandwidth optimization
  806. modeOption |= (pDecInfo->openParam.bwOptimization<< 31);
  807. /* Set attributes of bitstream buffer controller */
  808. bsOption = 0;
  809. regVal = 0;
  810. switch (pOpenParam->bitstreamMode) {
  811. case BS_MODE_INTERRUPT:
  812. bsOption = 0;
  813. break;
  814. case BS_MODE_PIC_END:
  815. bsOption = BSOPTION_ENABLE_EXPLICIT_END;
  816. break;
  817. default:
  818. return RETCODE_INVALID_PARAM;
  819. }
  820. VpuWriteReg(instance->coreIdx, W5_BS_RD_PTR, pDecInfo->streamRdPtr);
  821. VpuWriteReg(instance->coreIdx, W5_BS_WR_PTR, pDecInfo->streamWrPtr);
  822. if (pDecInfo->streamEndflag == 1)
  823. bsOption = 3; // (streamEndFlag<<1) | EXPLICIT_END
  824. if (pOpenParam->bitstreamMode == BS_MODE_PIC_END || pDecInfo->rdPtrValidFlag == TRUE)
  825. rdptr_valid = 1;
  826. VpuWriteReg(instance->coreIdx, W5_BS_OPTION, (rdptr_valid<<31) | bsOption);
  827. pDecInfo->rdPtrValidFlag = FALSE; // reset rdptrValidFlag.
  828. /* Secondary AXI */
  829. regVal = (pDecInfo->secAxiInfo.u.wave4.useBitEnable<<0) |
  830. (pDecInfo->secAxiInfo.u.wave4.useIpEnable<<9) |
  831. (pDecInfo->secAxiInfo.u.wave4.useLfRowEnable<<15);
  832. VpuWriteReg(instance->coreIdx, W5_USE_SEC_AXI, regVal);
  833. /* Set attributes of User buffer */
  834. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_USER_MASK, pDecInfo->userDataEnable);
  835. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_VCORE_LIMIT, 1);
  836. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_TEMPORAL_ID_PLUS1, pDecInfo->targetSubLayerId+1);
  837. VpuWriteReg(instance->coreIdx, W5_CMD_SEQ_CHANGE_ENABLE_FLAG, pDecInfo->seqChangeMask);
  838. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_FORCE_FB_LATENCY_PLUS1, forceLatency+1);
  839. VpuWriteReg(instance->coreIdx, W5_COMMAND_OPTION, modeOption);
  840. Wave5BitIssueCommand(instance, W5_DEC_PIC);
  841. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) { // Check QUEUE_DONE
  842. if (instance->loggingEnable)
  843. vdi_log(instance->coreIdx, W5_DEC_PIC, 2);
  844. return RETCODE_VPU_RESPONSE_TIMEOUT;
  845. }
  846. regVal = VpuReadReg(instance->coreIdx, W5_RET_QUEUE_STATUS);
  847. pDecInfo->instanceQueueCount = (regVal>>16)&0xff;
  848. pDecInfo->totalQueueCount = (regVal & 0xffff);
  849. if (VpuReadReg(instance->coreIdx, W5_RET_SUCCESS) == FALSE) { // FAILED for adding a command into VCPU QUEUE
  850. if (VpuReadReg(instance->coreIdx, W5_RET_FAIL_REASON) == 1)
  851. return RETCODE_QUEUEING_FAILURE;
  852. else
  853. return RETCODE_FAILURE;
  854. }
  855. return RETCODE_SUCCESS;
  856. }
  857. RetCode Wave5VpuDecGetResult(CodecInst* instance, DecOutputInfo* result)
  858. {
  859. RetCode ret = RETCODE_SUCCESS;
  860. Uint32 regVal, index, nalUnitType;
  861. DecInfo* pDecInfo;
  862. pDecInfo = VPU_HANDLE_TO_DECINFO(instance);
  863. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_ADDR_REPORT_BASE, pDecInfo->userDataBufAddr);
  864. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_REPORT_SIZE, pDecInfo->userDataBufSize);
  865. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_REPORT_PARAM, VPU_USER_DATA_ENDIAN&VDI_128BIT_ENDIAN_MASK);
  866. // Send QUERY cmd
  867. ret = SendQuery(instance, GET_RESULT);
  868. if (ret != RETCODE_SUCCESS) {
  869. if (VpuReadReg(instance->coreIdx, W5_RET_FAIL_REASON) == WAVE5_RESULT_NOT_READY)
  870. return RETCODE_REPORT_NOT_READY;
  871. else
  872. return RETCODE_QUERY_FAILURE;
  873. }
  874. if (instance->loggingEnable)
  875. vdi_log(instance->coreIdx, W5_DEC_PIC, 0);
  876. regVal = VpuReadReg(instance->coreIdx, W5_RET_QUEUE_STATUS);
  877. pDecInfo->instanceQueueCount = (regVal>>16)&0xff;
  878. pDecInfo->totalQueueCount = (regVal & 0xffff);
  879. result->decodingSuccess = VpuReadReg(instance->coreIdx, W5_RET_DEC_DECODING_SUCCESS);
  880. if (result->decodingSuccess == FALSE) {
  881. result->errorReason = VpuReadReg(instance->coreIdx, W5_RET_DEC_ERR_INFO);
  882. if (result->errorReason == WAVE5_SYSERR_ACCESS_VIOLATION_HW) {
  883. return RETCODE_MEMORY_ACCESS_VIOLATION;
  884. }
  885. else if (result->errorReason == WAVE5_CODEC_ERROR) {
  886. result->errorReasonExt = VpuReadReg(instance->coreIdx, W5_RET_DEC_ERR_INFO);
  887. }
  888. }
  889. else {
  890. result->warnInfo = VpuReadReg(instance->coreIdx, W5_RET_DEC_WARN_INFO);
  891. }
  892. result->decOutputExtData.userDataSize = 0;
  893. result->decOutputExtData.userDataNum = 0;
  894. result->decOutputExtData.userDataHeader = VpuReadReg(instance->coreIdx, W5_RET_DEC_USERDATA_IDC);
  895. if (result->decOutputExtData.userDataHeader != 0) {
  896. regVal = result->decOutputExtData.userDataHeader;
  897. for (index=0; index<32; index++) {
  898. if (regVal & (1<<index)) {
  899. result->decOutputExtData.userDataNum++;
  900. }
  901. }
  902. result->decOutputExtData.userDataSize = pDecInfo->userDataBufSize;
  903. }
  904. result->frameCycle = VpuReadReg(instance->coreIdx, W5_FRAME_CYCLE);
  905. result->seekCycle = VpuReadReg(instance->coreIdx, W5_RET_DEC_SEEK_CYCLE);
  906. result->parseCycle = VpuReadReg(instance->coreIdx, W5_RET_DEC_PARSING_CYCLE);
  907. result->decodeCycle = VpuReadReg(instance->coreIdx, W5_RET_DEC_DECODING_CYCLE);
  908. regVal = VpuReadReg(instance->coreIdx, W5_RET_DEC_PIC_TYPE);
  909. if (instance->codecMode == C7_VP9_DEC) {
  910. if (regVal&0x01) result->picType = PIC_TYPE_I;
  911. else if (regVal&0x02) result->picType = PIC_TYPE_P;
  912. else if (regVal&0x04) result->picType = PIC_TYPE_REPEAT;
  913. else result->picType = PIC_TYPE_MAX;
  914. }
  915. else { // HEVC
  916. if (regVal&0x04) result->picType = PIC_TYPE_B;
  917. else if (regVal&0x02) result->picType = PIC_TYPE_P;
  918. else if (regVal&0x01) result->picType = PIC_TYPE_I;
  919. else result->picType = PIC_TYPE_MAX;
  920. }
  921. result->outputFlag = (regVal>>31)&0x1;
  922. nalUnitType = (regVal & 0x3f0) >> 4;
  923. if ((nalUnitType == 19 || nalUnitType == 20) && result->picType == PIC_TYPE_I) {
  924. /* IDR_W_RADL, IDR_N_LP */
  925. result->picType = PIC_TYPE_IDR;
  926. }
  927. result->nalType = nalUnitType;
  928. result->ctuSize = 16<<((regVal>>10)&0x3);
  929. index = VpuReadReg(instance->coreIdx, W5_RET_DEC_DISPLAY_INDEX);
  930. result->indexFrameDisplay = index;
  931. result->indexFrameDisplayForTiled = index;
  932. index = VpuReadReg(instance->coreIdx, W5_RET_DEC_DECODED_INDEX);
  933. result->indexFrameDecoded = index;
  934. result->indexFrameDecodedForTiled = index;
  935. if (instance->codecMode != C7_VP9_DEC) {
  936. result->h265Info.decodedPOC = -1;
  937. result->h265Info.displayPOC = -1;
  938. if (result->indexFrameDecoded >= 0)
  939. result->h265Info.decodedPOC = VpuReadReg(instance->coreIdx, W5_RET_DEC_PIC_POC);
  940. result->h265Info.temporalId = VpuReadReg(instance->coreIdx, W5_RET_DEC_SUB_LAYER_INFO) & 0xff;
  941. }
  942. result->sequenceChanged = VpuReadReg(instance->coreIdx, W5_RET_DEC_NOTIFICATION);
  943. /*
  944. * If current picture is the last of the current sequence and sequence-change flag is not 0, then
  945. * the width and height of the current picture is set to the width and height of the current sequence.
  946. */
  947. if (result->sequenceChanged == 0) {
  948. regVal = VpuReadReg(instance->coreIdx, W5_RET_DEC_PIC_SIZE);
  949. result->decPicWidth = regVal>>16;
  950. result->decPicHeight = regVal&0xffff;
  951. }
  952. else {
  953. if (result->indexFrameDecoded < 0) {
  954. result->decPicWidth = 0;
  955. result->decPicHeight = 0;
  956. }
  957. else {
  958. result->decPicWidth = pDecInfo->initialInfo.picWidth;
  959. result->decPicHeight = pDecInfo->initialInfo.picHeight;
  960. }
  961. if ( instance->codecMode == C7_VP9_DEC ) {
  962. if ( result->sequenceChanged & SEQ_CHANGE_INTER_RES_CHANGE) {
  963. regVal = VpuReadReg(instance->coreIdx, W5_RET_DEC_PIC_SIZE);
  964. result->decPicWidth = regVal>>16;
  965. result->decPicHeight = regVal&0xffff;
  966. result->indexInterFrameDecoded = VpuReadReg(instance->coreIdx, W5_RET_DEC_REALLOC_INDEX);
  967. }
  968. }
  969. osal_memcpy((void*)&pDecInfo->newSeqInfo, (void*)&pDecInfo->initialInfo, sizeof(DecInitialInfo));
  970. GetDecSequenceResult(instance, &pDecInfo->newSeqInfo);
  971. }
  972. result->numOfErrMBs = VpuReadReg(instance->coreIdx, W5_RET_DEC_ERR_CTB_NUM)>>16;
  973. result->numOfTotMBs = VpuReadReg(instance->coreIdx, W5_RET_DEC_ERR_CTB_NUM)&0xffff;
  974. result->bytePosFrameStart = VpuReadReg(instance->coreIdx, W5_RET_DEC_AU_START_POS);
  975. result->bytePosFrameEnd = VpuReadReg(instance->coreIdx, W5_RET_DEC_AU_END_POS);
  976. pDecInfo->prevFrameEndPos = result->bytePosFrameEnd;
  977. regVal = VpuReadReg(instance->coreIdx, W5_RET_DEC_RECOVERY_POINT);
  978. result->h265RpSei.recoveryPocCnt = regVal & 0xFFFF; // [15:0]
  979. result->h265RpSei.exactMatchFlag = (regVal >> 16)&0x01; // [16]
  980. result->h265RpSei.brokenLinkFlag = (regVal >> 17)&0x01; // [17]
  981. result->h265RpSei.exist = (regVal >> 18)&0x01; // [18]
  982. if(result->h265RpSei.exist == 0) {
  983. result->h265RpSei.recoveryPocCnt = 0;
  984. result->h265RpSei.exactMatchFlag = 0;
  985. result->h265RpSei.brokenLinkFlag = 0;
  986. }
  987. return RETCODE_SUCCESS;
  988. }
  989. RetCode Wave5VpuDecFlush(CodecInst* instance, FramebufferIndex* framebufferIndexes, Uint32 size)
  990. {
  991. RetCode ret = RETCODE_SUCCESS;
  992. Wave5BitIssueCommand(instance, W5_FLUSH_INSTANCE);
  993. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1)
  994. return RETCODE_VPU_RESPONSE_TIMEOUT;
  995. if (VpuReadReg(instance->coreIdx, W5_RET_SUCCESS) == FALSE) {
  996. if (VpuReadReg(instance->coreIdx, W5_RET_FAIL_REASON) == WAVE5_VPU_STILL_RUNNING)
  997. ret = RETCODE_VPU_STILL_RUNNING;
  998. else
  999. ret = RETCODE_FAILURE;
  1000. }
  1001. return ret;
  1002. }
  1003. RetCode Wave5VpuReInit(Uint32 coreIdx, void* firmware, Uint32 size)
  1004. {
  1005. vpu_buffer_t vb;
  1006. PhysicalAddress codeBase, tempBase, taskBufBase;
  1007. PhysicalAddress oldCodeBase, tempSize;
  1008. Uint32 codeSize;
  1009. Uint32 regVal, remapSize, i=0;
  1010. CodecInstHeader hdr;
  1011. osal_memset((void *)&hdr, 0x00, sizeof(CodecInstHeader));
  1012. vdi_get_common_memory(coreIdx, &vb);
  1013. codeBase = vb.phys_addr;
  1014. /* ALIGN TO 4KB */
  1015. codeSize = (WAVE5_MAX_CODE_BUF_SIZE&~0xfff);
  1016. if (codeSize < size*2) {
  1017. return RETCODE_INSUFFICIENT_RESOURCE;
  1018. }
  1019. tempBase = vb.phys_addr + WAVE5_TEMPBUF_OFFSET;
  1020. tempSize = WAVE5_TEMPBUF_SIZE;
  1021. oldCodeBase = VpuReadReg(coreIdx, W5_VPU_REMAP_PADDR);
  1022. if (oldCodeBase != codeBase) {
  1023. VpuWriteMem(coreIdx, codeBase, (unsigned char*)firmware, size*2, VDI_128BIT_LITTLE_ENDIAN);
  1024. vdi_set_bit_firmware_to_pm(coreIdx, (Uint16*)firmware);
  1025. regVal = 0;
  1026. VpuWriteReg(coreIdx, W5_PO_CONF, regVal);
  1027. // Step1 : disable request
  1028. vdi_fio_write_register(coreIdx, W5_GDI_BUS_CTRL, 0x100);
  1029. // Step2 : Waiting for completion of bus transaction
  1030. if (vdi_wait_bus_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_GDI_BUS_STATUS) == -1) {
  1031. vdi_fio_write_register(coreIdx, W5_GDI_BUS_CTRL, 0x00);
  1032. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1033. }
  1034. /* Reset All blocks */
  1035. regVal = 0x7ffffff;
  1036. VpuWriteReg(coreIdx, W5_VPU_RESET_REQ, regVal); // Reset All blocks
  1037. /* Waiting reset done */
  1038. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_RESET_STATUS) == -1) {
  1039. VpuWriteReg(coreIdx, W5_VPU_RESET_REQ, 0);
  1040. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1041. }
  1042. VpuWriteReg(coreIdx, W5_VPU_RESET_REQ, 0);
  1043. // Step3 : must clear GDI_BUS_CTRL after done SW_RESET
  1044. vdi_fio_write_register(coreIdx, W5_GDI_BUS_CTRL, 0x00);
  1045. /* remap page size */
  1046. remapSize = (codeSize >> 12) &0x1ff;
  1047. regVal = 0x80000000 | (WAVE5_AXI_ID<<20) | (W5_REMAP_CODE_INDEX<<12) | (0 << 16) | (1<<11) | remapSize;
  1048. VpuWriteReg(coreIdx, W5_VPU_REMAP_CTRL, regVal);
  1049. VpuWriteReg(coreIdx, W5_VPU_REMAP_VADDR, 0x00000000); /* DO NOT CHANGE! */
  1050. VpuWriteReg(coreIdx, W5_VPU_REMAP_PADDR, codeBase);
  1051. VpuWriteReg(coreIdx, W5_ADDR_CODE_BASE, codeBase);
  1052. VpuWriteReg(coreIdx, W5_CODE_SIZE, codeSize);
  1053. VpuWriteReg(coreIdx, W5_CODE_PARAM, (WAVE5_AXI_ID<<4) | 0);
  1054. VpuWriteReg(coreIdx, W5_ADDR_TEMP_BASE, tempBase);
  1055. VpuWriteReg(coreIdx, W5_TEMP_SIZE, tempSize);
  1056. VpuWriteReg(coreIdx, W5_TIMEOUT_CNT, 0);
  1057. VpuWriteReg(coreIdx, W5_HW_OPTION, 0);
  1058. /* Interrupt */
  1059. regVal = (1<<W5_INT_INIT_SEQ);
  1060. regVal |= (1<<W5_INT_DEC_PIC);
  1061. regVal |= (1<<W5_INT_BSBUF_EMPTY);
  1062. VpuWriteReg(coreIdx, W5_VPU_VINT_ENABLE, regVal);
  1063. VpuWriteReg(coreIdx,W5_CMD_INIT_NUM_TASK_BUF, COMMAND_QUEUE_DEPTH);
  1064. vdi_get_common_memory(coreIdx, &vb);
  1065. for (i = 0; i < COMMAND_QUEUE_DEPTH; i++) {
  1066. taskBufBase = vb.phys_addr + WAVE5_TASK_BUF_OFFSET + (i*ONE_TASKBUF_SIZE_FOR_CQ);
  1067. VpuWriteReg(coreIdx, W5_CMD_INIT_ADDR_TASK_BUF0 + (i*4), taskBufBase);
  1068. }
  1069. if (vdi_get_sram_memory(coreIdx, &vb) < 0) // get SRAM base/size
  1070. return RETCODE_INSUFFICIENT_RESOURCE;
  1071. VpuWriteReg(coreIdx, W5_ADDR_SEC_AXI, vb.phys_addr);
  1072. VpuWriteReg(coreIdx, W5_SEC_AXI_SIZE, vb.size);
  1073. hdr.coreIdx = coreIdx;
  1074. VpuWriteReg(coreIdx, W5_VPU_BUSY_STATUS, 1);
  1075. VpuWriteReg(coreIdx, W5_COMMAND, W5_INIT_VPU);
  1076. VpuWriteReg(coreIdx, W5_VPU_HOST_INT_REQ, 1);
  1077. VpuWriteReg(coreIdx, W5_VPU_REMAP_CORE_START, 1);
  1078. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) {
  1079. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1080. }
  1081. regVal = VpuReadReg(coreIdx, W5_RET_SUCCESS);
  1082. if (regVal == 0)
  1083. return RETCODE_FAILURE;
  1084. }
  1085. SetupWave5Properties(coreIdx);
  1086. return RETCODE_SUCCESS;
  1087. }
  1088. RetCode Wave5VpuSleepWake(Uint32 coreIdx, int iSleepWake, const Uint16* code, Uint32 size, BOOL reset)
  1089. {
  1090. CodecInstHeader hdr;
  1091. Uint32 regVal;
  1092. vpu_buffer_t vb;
  1093. PhysicalAddress codeBase, tempBase;
  1094. Uint32 codeSize, tempSize;
  1095. Uint32 remapSize;
  1096. osal_memset((void *)&hdr, 0x00, sizeof(CodecInstHeader));
  1097. hdr.coreIdx = coreIdx;
  1098. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) {
  1099. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1100. }
  1101. if(iSleepWake==1) //saves
  1102. {
  1103. VpuWriteReg(coreIdx, W5_VPU_BUSY_STATUS, 1);
  1104. VpuWriteReg(coreIdx, W5_COMMAND, W5_SLEEP_VPU);
  1105. VpuWriteReg(coreIdx, W5_VPU_HOST_INT_REQ, 1);
  1106. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1)
  1107. {
  1108. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1109. }
  1110. regVal = VpuReadReg(coreIdx, W5_RET_SUCCESS);
  1111. if (regVal == 0)
  1112. {
  1113. APIDPRINT("SLEEP_VPU failed [0x%x]", VpuReadReg(coreIdx, W5_RET_FAIL_REASON));
  1114. return RETCODE_FAILURE;
  1115. }
  1116. }
  1117. else //restore
  1118. {
  1119. Uint32 hwOption = 0;
  1120. Uint32 i;
  1121. PhysicalAddress taskBufBase;
  1122. vdi_get_common_memory(coreIdx, &vb);
  1123. codeBase = vb.phys_addr;
  1124. /* ALIGN TO 4KB */
  1125. codeSize = (WAVE5_MAX_CODE_BUF_SIZE&~0xfff);
  1126. if (codeSize < size*2) {
  1127. return RETCODE_INSUFFICIENT_RESOURCE;
  1128. }
  1129. tempBase = vb.phys_addr + WAVE5_TEMPBUF_OFFSET;
  1130. tempSize = WAVE5_TEMPBUF_SIZE;
  1131. regVal = 0;
  1132. VpuWriteReg(coreIdx, W5_PO_CONF, regVal);
  1133. /* SW_RESET_SAFETY */
  1134. regVal = W5_RST_BLOCK_ALL;
  1135. VpuWriteReg(coreIdx, W5_VPU_RESET_REQ, regVal); // Reset All blocks
  1136. /* Waiting reset done */
  1137. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_RESET_STATUS) == -1) {
  1138. VpuWriteReg(coreIdx, W5_VPU_RESET_REQ, 0);
  1139. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1140. }
  1141. VpuWriteReg(coreIdx, W5_VPU_RESET_REQ, 0);
  1142. /* remap page size */
  1143. remapSize = (codeSize >> 12) &0x1ff;
  1144. regVal = 0x80000000 | (WAVE5_AXI_ID<<20) | (W5_REMAP_CODE_INDEX<<12) | (0 << 16) | (1<<11) | remapSize;
  1145. VpuWriteReg(coreIdx, W5_VPU_REMAP_CTRL, regVal);
  1146. VpuWriteReg(coreIdx, W5_VPU_REMAP_VADDR, 0x00000000); /* DO NOT CHANGE! */
  1147. VpuWriteReg(coreIdx, W5_VPU_REMAP_PADDR, codeBase);
  1148. VpuWriteReg(coreIdx, W5_ADDR_CODE_BASE, codeBase);
  1149. VpuWriteReg(coreIdx, W5_CODE_SIZE, codeSize);
  1150. VpuWriteReg(coreIdx, W5_CODE_PARAM, (WAVE5_AXI_ID<<4) | 0);
  1151. VpuWriteReg(coreIdx, W5_ADDR_TEMP_BASE, tempBase);
  1152. VpuWriteReg(coreIdx, W5_TEMP_SIZE, tempSize);
  1153. VpuWriteReg(coreIdx, W5_TIMEOUT_CNT, 0);
  1154. VpuWriteReg(coreIdx, W5_HW_OPTION, hwOption);
  1155. /* Interrupt */
  1156. regVal = (1<<W5_INT_INIT_SEQ);
  1157. regVal |= (1<<W5_INT_DEC_PIC);
  1158. regVal |= (1<<W5_INT_BSBUF_EMPTY);
  1159. VpuWriteReg(coreIdx, W5_VPU_VINT_ENABLE, regVal);
  1160. VpuWriteReg(coreIdx, W5_CMD_INIT_NUM_TASK_BUF, COMMAND_QUEUE_DEPTH);
  1161. VpuWriteReg(coreIdx, W5_CMD_INIT_TASK_BUF_SIZE, ONE_TASKBUF_SIZE_FOR_CQ);
  1162. vdi_get_common_memory(coreIdx, &vb);
  1163. for (i = 0; i < COMMAND_QUEUE_DEPTH; i++) {
  1164. taskBufBase = vb.phys_addr + WAVE5_TASK_BUF_OFFSET + (i*ONE_TASKBUF_SIZE_FOR_CQ);
  1165. VpuWriteReg(coreIdx, W5_CMD_INIT_ADDR_TASK_BUF0 + (i*4), taskBufBase);
  1166. }
  1167. if (vdi_get_sram_memory(coreIdx, &vb) < 0) // get SRAM base/size
  1168. return RETCODE_INSUFFICIENT_RESOURCE;
  1169. VpuWriteReg(coreIdx, W5_ADDR_SEC_AXI, vb.phys_addr);
  1170. VpuWriteReg(coreIdx, W5_SEC_AXI_SIZE, vb.size);
  1171. VpuWriteReg(coreIdx, W5_VPU_BUSY_STATUS, 1);
  1172. VpuWriteReg(coreIdx, W5_COMMAND, (reset==TRUE ? W5_INIT_VPU : W5_WAKEUP_VPU));
  1173. VpuWriteReg(coreIdx, W5_VPU_REMAP_CORE_START, 1);
  1174. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) {
  1175. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1176. }
  1177. regVal = VpuReadReg(coreIdx, W5_RET_SUCCESS);
  1178. if (regVal == 0) {
  1179. return RETCODE_FAILURE;
  1180. }
  1181. VpuWriteReg(coreIdx, W5_VPU_VINT_REASON_CLR, 0xffff);
  1182. VpuWriteReg(coreIdx, W5_VPU_VINT_REASON_USR, 0);
  1183. VpuWriteReg(coreIdx, W5_VPU_VINT_CLEAR, 0x1);
  1184. }
  1185. return RETCODE_SUCCESS;
  1186. }
  1187. RetCode Wave5VpuReset(Uint32 coreIdx, SWResetMode resetMode)
  1188. {
  1189. Uint32 val = 0;
  1190. RetCode ret = RETCODE_SUCCESS;
  1191. // VPU doesn't send response. Force to set BUSY flag to 0.
  1192. VpuWriteReg(coreIdx, W5_VPU_BUSY_STATUS, 0);
  1193. // Waiting for completion of bus transaction
  1194. // Step1 : disable request
  1195. vdi_fio_write_register(coreIdx, W5_GDI_BUS_CTRL, 0x100);
  1196. // Step2 : Waiting for completion of bus transaction
  1197. if (vdi_wait_bus_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_GDI_BUS_STATUS) == -1) {
  1198. vdi_fio_write_register(coreIdx, W5_GDI_BUS_CTRL, 0x00);
  1199. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1200. }
  1201. if (resetMode == SW_RESET_SAFETY) {
  1202. if ((ret=Wave5VpuSleepWake(coreIdx, TRUE, NULL, 0, TRUE)) != RETCODE_SUCCESS) {
  1203. return ret;
  1204. }
  1205. }
  1206. switch (resetMode) {
  1207. case SW_RESET_ON_BOOT:
  1208. case SW_RESET_FORCE:
  1209. case SW_RESET_SAFETY:
  1210. val = W5_RST_BLOCK_ALL;
  1211. break;
  1212. default:
  1213. return RETCODE_INVALID_PARAM;
  1214. }
  1215. if (val) {
  1216. VpuWriteReg(coreIdx, W5_VPU_RESET_REQ, val);
  1217. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_RESET_STATUS) == -1) {
  1218. VpuWriteReg(coreIdx, W5_VPU_RESET_REQ, 0);
  1219. vdi_log(coreIdx, W5_RESET_VPU, 2);
  1220. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1221. }
  1222. VpuWriteReg(coreIdx, W5_VPU_RESET_REQ, 0);
  1223. }
  1224. // Step3 : must clear GDI_BUS_CTRL after done SW_RESET
  1225. vdi_fio_write_register(coreIdx, W5_GDI_BUS_CTRL, 0x00);
  1226. if (resetMode == SW_RESET_SAFETY || resetMode == SW_RESET_FORCE ) {
  1227. ret = Wave5VpuSleepWake(coreIdx, FALSE, NULL, 0, TRUE);
  1228. }
  1229. return ret;
  1230. }
  1231. RetCode Wave5VpuDecFiniSeq(CodecInst* instance)
  1232. {
  1233. RetCode ret = RETCODE_SUCCESS;
  1234. Wave5BitIssueCommand(instance, W5_DESTROY_INSTANCE);
  1235. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1)
  1236. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1237. if (VpuReadReg(instance->coreIdx, W5_RET_SUCCESS) == FALSE) {
  1238. if (VpuReadReg(instance->coreIdx, W5_RET_FAIL_REASON) == WAVE5_VPU_STILL_RUNNING)
  1239. ret = RETCODE_VPU_STILL_RUNNING;
  1240. else
  1241. ret = RETCODE_FAILURE;
  1242. }
  1243. return ret;
  1244. }
  1245. RetCode Wave5VpuDecSetBitstreamFlag(CodecInst* instance, BOOL running, BOOL eos, BOOL explictEnd)
  1246. {
  1247. DecInfo* pDecInfo = &instance->CodecInfo->decInfo;
  1248. BitStreamMode bsMode = (BitStreamMode)pDecInfo->openParam.bitstreamMode;
  1249. pDecInfo->streamEndflag = (eos == 1) ? TRUE : FALSE;
  1250. if (bsMode == BS_MODE_INTERRUPT) {
  1251. if (pDecInfo->streamEndflag == TRUE) explictEnd = TRUE;
  1252. VpuWriteReg(instance->coreIdx, W5_BS_OPTION, (pDecInfo->streamEndflag<<1) | explictEnd);
  1253. VpuWriteReg(instance->coreIdx, W5_BS_WR_PTR, pDecInfo->streamWrPtr);
  1254. Wave5BitIssueCommand(instance, W5_UPDATE_BS);
  1255. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) {
  1256. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1257. }
  1258. if (VpuReadReg(instance->coreIdx, W5_RET_SUCCESS) == 0) {
  1259. return RETCODE_FAILURE;
  1260. }
  1261. }
  1262. return RETCODE_SUCCESS;
  1263. }
  1264. RetCode Wave5DecClrDispFlag(CodecInst* instance, Uint32 index)
  1265. {
  1266. RetCode ret = RETCODE_SUCCESS;
  1267. DecInfo * pDecInfo;
  1268. pDecInfo = &instance->CodecInfo->decInfo;
  1269. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_CLR_DISP_IDC, (1<<index));
  1270. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_SET_DISP_IDC, 0);
  1271. ret = SendQuery(instance, UPDATE_DISP_FLAG);
  1272. if (ret != RETCODE_SUCCESS)
  1273. return RETCODE_QUERY_FAILURE;
  1274. pDecInfo->frameDisplayFlag = VpuReadReg(instance->coreIdx, pDecInfo->frameDisplayFlagRegAddr);
  1275. return RETCODE_SUCCESS;
  1276. }
  1277. RetCode Wave5DecSetDispFlag(CodecInst* instance, Uint32 index)
  1278. {
  1279. RetCode ret = RETCODE_SUCCESS;
  1280. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_CLR_DISP_IDC, 0);
  1281. VpuWriteReg(instance->coreIdx, W5_CMD_DEC_SET_DISP_IDC, (1<<index));
  1282. ret = SendQuery(instance, UPDATE_DISP_FLAG);
  1283. return ret;
  1284. }
  1285. Int32 Wave5VpuWaitInterrupt(CodecInst* instance, Int32 timeout, BOOL pending)
  1286. {
  1287. Int32 reason = -1;
  1288. Int32 remain_intr = -1; // to set VPU_VINT_REASON for remain interrupt.
  1289. Int32 ownInt = 0;
  1290. Uint32 regVal;
  1291. Uint32 IntrMask = ((1 << INT_WAVE5_BSBUF_EMPTY) | (1 << INT_WAVE5_DEC_PIC) | (1 << INT_WAVE5_INIT_SEQ) | (1 << INT_WAVE5_ENC_SET_PARAM));
  1292. EnterLock(instance->coreIdx);
  1293. // check one interrupt for current instance even if the number of interrupt triggered more than one.
  1294. if ((reason = vdi_wait_interrupt(instance->coreIdx, timeout, W5_VPU_VINT_REASON_USR)) > 0) {
  1295. remain_intr = VpuReadReg(instance->coreIdx, W5_VPU_VINT_REASON_USR);
  1296. if (reason & (1 << INT_WAVE5_BSBUF_EMPTY)) {
  1297. regVal = VpuReadReg(instance->coreIdx, W5_RET_BS_EMPTY_INST);
  1298. if (regVal & (1 << instance->instIndex)) {
  1299. ownInt = 1;
  1300. reason = (1 << INT_WAVE5_BSBUF_EMPTY);
  1301. remain_intr &= ~reason;
  1302. }
  1303. }
  1304. if (reason & (1 << INT_WAVE5_DEC_PIC)) {
  1305. regVal = VpuReadReg(instance->coreIdx, W5_RET_QUEUE_CMD_DONE_INST);
  1306. if (regVal & (1 << instance->instIndex)) {
  1307. ownInt = 1;
  1308. reason = (1 << INT_WAVE5_DEC_PIC);
  1309. remain_intr &= ~reason;
  1310. }
  1311. }
  1312. if (reason & (1 << INT_WAVE5_INIT_SEQ)) {
  1313. regVal = VpuReadReg(instance->coreIdx, W5_RET_QUEUE_CMD_DONE_INST);
  1314. if (regVal & (1 << instance->instIndex)) {
  1315. ownInt = 1;
  1316. reason = (1 << INT_WAVE5_INIT_SEQ);
  1317. remain_intr &= ~reason;
  1318. }
  1319. }
  1320. if (reason & (1 << INT_WAVE5_ENC_SET_PARAM)) {
  1321. regVal = VpuReadReg(instance->coreIdx, W5_RET_QUEUE_CMD_DONE_INST);
  1322. if (regVal & (1 << instance->instIndex)) {
  1323. ownInt = 1;
  1324. reason = (1 << INT_WAVE5_ENC_SET_PARAM);
  1325. remain_intr &= ~reason;
  1326. }
  1327. }
  1328. if (reason & ~IntrMask) { // when interrupt is not for empty, dec_pic, init_seq.
  1329. regVal = VpuReadReg(instance->coreIdx, W5_RET_DONE_INSTANCE_INFO)&0xFF;
  1330. if (regVal == instance->instIndex) {
  1331. ownInt = 1;
  1332. reason = (reason & ~IntrMask);
  1333. remain_intr &= ~reason;
  1334. }
  1335. }
  1336. VpuWriteReg(instance->coreIdx, W5_VPU_VINT_REASON, remain_intr); // set remain interrupt flag to trigger interrupt next time.
  1337. if (!ownInt)
  1338. reason = -1; // if there was no interrupt for current instance id, reason should be -1;
  1339. }
  1340. LeaveLock(instance->coreIdx);
  1341. return reason;
  1342. }
  1343. RetCode Wave5VpuClearInterrupt(Uint32 coreIdx, Uint32 flags)
  1344. {
  1345. Uint32 interruptReason;
  1346. interruptReason = VpuReadReg(coreIdx, W5_VPU_VINT_REASON_USR);
  1347. interruptReason &= ~flags;
  1348. VpuWriteReg(coreIdx, W5_VPU_VINT_REASON_USR, interruptReason);
  1349. return RETCODE_SUCCESS;
  1350. }
  1351. /************************************************************************/
  1352. /* ENCODER functions */
  1353. /************************************************************************/
  1354. RetCode Wave5VpuBuildUpEncParam(CodecInst* instance, EncOpenParam* param)
  1355. {
  1356. RetCode ret = RETCODE_SUCCESS;
  1357. EncInfo* pEncInfo;
  1358. VpuAttr* pAttr = &g_VpuCoreAttributes[instance->coreIdx];
  1359. pEncInfo = VPU_HANDLE_TO_ENCINFO(instance);
  1360. pEncInfo->streamRdPtrRegAddr = W5_RET_ENC_RD_PTR;
  1361. pEncInfo->streamWrPtrRegAddr = W5_RET_ENC_WR_PTR;
  1362. pEncInfo->currentPC = W5_VCPU_CUR_PC;
  1363. pEncInfo->busyFlagAddr = W5_VPU_BUSY_STATUS;
  1364. if ((pAttr->supportEncoders&(1<<param->bitstreamFormat)) == 0)
  1365. return RETCODE_NOT_SUPPORTED_FEATURE;
  1366. if (param->bitstreamFormat == STD_HEVC)
  1367. instance->codecMode = HEVC_ENC;
  1368. pEncInfo->vbWork.size = WAVE5ENC_WORKBUF_SIZE;
  1369. if (vdi_allocate_dma_memory(instance->coreIdx, &pEncInfo->vbWork) < 0) {
  1370. pEncInfo->vbWork.base = 0;
  1371. pEncInfo->vbWork.phys_addr = 0;
  1372. pEncInfo->vbWork.size = 0;
  1373. pEncInfo->vbWork.virt_addr = 0;
  1374. return RETCODE_INSUFFICIENT_RESOURCE;
  1375. }
  1376. vdi_clear_memory(instance->coreIdx, pEncInfo->vbWork.phys_addr, pEncInfo->vbWork.size, 0);
  1377. VpuWriteReg(instance->coreIdx, W5_ADDR_WORK_BASE, pEncInfo->vbWork.phys_addr);
  1378. VpuWriteReg(instance->coreIdx, W5_WORK_SIZE, pEncInfo->vbWork.size);
  1379. VpuWriteReg(instance->coreIdx, W5_VPU_BUSY_STATUS, 1);
  1380. VpuWriteReg(instance->coreIdx, W5_RET_SUCCESS, 0); //for debug
  1381. VpuWriteReg(instance->coreIdx, W5_CMD_ENC_VCORE_LIMIT, 1);
  1382. Wave5BitIssueCommand(instance, W5_CREATE_INSTANCE);
  1383. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) { // Check QUEUE_DONE
  1384. if (instance->loggingEnable)
  1385. vdi_log(instance->coreIdx, W5_CREATE_INSTANCE, 2);
  1386. vdi_free_dma_memory(instance->coreIdx, &pEncInfo->vbWork);
  1387. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1388. }
  1389. if (VpuReadReg(instance->coreIdx, W5_RET_SUCCESS) == FALSE) { // FAILED for adding into VCPU QUEUE
  1390. vdi_free_dma_memory(instance->coreIdx, &pEncInfo->vbWork);
  1391. ret = RETCODE_FAILURE;
  1392. }
  1393. pEncInfo->streamRdPtr = param->bitstreamBuffer;
  1394. pEncInfo->streamWrPtr = param->bitstreamBuffer;
  1395. pEncInfo->lineBufIntEn = param->lineBufIntEn;
  1396. pEncInfo->streamBufStartAddr = param->bitstreamBuffer;
  1397. pEncInfo->streamBufSize = param->bitstreamBufferSize;
  1398. pEncInfo->streamBufEndAddr = param->bitstreamBuffer + param->bitstreamBufferSize;
  1399. pEncInfo->stride = 0;
  1400. pEncInfo->vbFrame.size = 0;
  1401. pEncInfo->vbPPU.size = 0;
  1402. pEncInfo->frameAllocExt = 0;
  1403. pEncInfo->ppuAllocExt = 0;
  1404. pEncInfo->initialInfoObtained = 0;
  1405. return ret;
  1406. }
  1407. RetCode Wave5VpuEncInitSeq(CodecInst* instance)
  1408. {
  1409. Int32 coreIdx, width32 = 0, height32=0;
  1410. Uint32 regVal = 0, rotMirMode;
  1411. EncInfo* pEncInfo;
  1412. EncOpenParam* pOpenParam;
  1413. EncHevcParam* pHevc;
  1414. coreIdx = instance->coreIdx;
  1415. pEncInfo = &instance->CodecInfo->encInfo;
  1416. pOpenParam = &pEncInfo->openParam;
  1417. pHevc = &pOpenParam->EncStdParam.hevcParam;
  1418. /*==============================================*/
  1419. /* OPT_CUSTOM_GOP */
  1420. /*==============================================*/
  1421. /*
  1422. * SET_PARAM + CUSTOM_GOP
  1423. * only when gopPresetIdx == custom_gop, custom_gop related registers should be set
  1424. */
  1425. if (pHevc->gopPresetIdx == PRESET_IDX_CUSTOM_GOP) {
  1426. int i=0, j = 0;
  1427. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_SET_PARAM_OPTION, OPT_CUSTOM_GOP);
  1428. VpuWriteReg(coreIdx, W5_CMD_ENC_CUSTOM_GOP_PARAM, pHevc->gopParam.customGopSize);
  1429. for (i=0 ; i<pHevc->gopParam.customGopSize; i++) {
  1430. VpuWriteReg(coreIdx, W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_0 + (i*4), (pHevc->gopParam.picParam[i].picType<<0) |
  1431. (pHevc->gopParam.picParam[i].pocOffset<<2) |
  1432. (pHevc->gopParam.picParam[i].picQp<<6) |
  1433. (pHevc->gopParam.picParam[i].numRefPicL0<<12) |
  1434. ((pHevc->gopParam.picParam[i].refPocL0&0x1F)<<14) |
  1435. ((pHevc->gopParam.picParam[i].refPocL1&0x1F)<<19) |
  1436. (pHevc->gopParam.picParam[i].temporalId<<24));
  1437. }
  1438. for (j = i; j < MAX_GOP_NUM; j++) {
  1439. VpuWriteReg(coreIdx, W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_0 + (j*4), 0);
  1440. }
  1441. Wave5BitIssueCommand(instance, W5_ENC_SET_PARAM);
  1442. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) {
  1443. if (instance->loggingEnable)
  1444. vdi_log(coreIdx, W5_ENC_SET_PARAM, 2);
  1445. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1446. }
  1447. }
  1448. /*======================================================================*/
  1449. /* OPT_COMMON */
  1450. /* : the last SET_PARAM command should be called with OPT_COMMON */
  1451. /*======================================================================*/
  1452. rotMirMode = 0;
  1453. /* CMD_ENC_ROT_MODE :
  1454. * | hor_mir | ver_mir | rot_angle | rot_en |
  1455. * [4] [3] [2:1] [0]
  1456. */
  1457. if (pEncInfo->rotationEnable == TRUE) {
  1458. switch (pEncInfo->rotationAngle) {
  1459. case 0:
  1460. rotMirMode |= 0x0;
  1461. break;
  1462. case 90:
  1463. rotMirMode |= 0x3;
  1464. break;
  1465. case 180:
  1466. rotMirMode |= 0x5;
  1467. break;
  1468. case 270:
  1469. rotMirMode |= 0x7;
  1470. break;
  1471. }
  1472. }
  1473. if (pEncInfo->mirrorEnable == TRUE) {
  1474. switch (pEncInfo->mirrorDirection) {
  1475. case MIRDIR_NONE :
  1476. rotMirMode |= 0x0;
  1477. break;
  1478. case MIRDIR_VER :
  1479. rotMirMode |= 0x9;
  1480. break;
  1481. case MIRDIR_HOR :
  1482. rotMirMode |= 0x11;
  1483. break;
  1484. case MIRDIR_HOR_VER :
  1485. rotMirMode |= 0x19;
  1486. break;
  1487. }
  1488. }
  1489. width32 = (pOpenParam->picWidth + 31) & ~31;
  1490. height32= (pOpenParam->picHeight+ 31) & ~31;
  1491. if (((rotMirMode != 0) && !((pEncInfo->rotationAngle == 180) && (pEncInfo->mirrorDirection == MIRDIR_HOR_VER))) && ((pOpenParam->picWidth != width32) || (pOpenParam->picHeight != height32))) // if rot/mir enable && pic size is not 32-aligned, set crop info.
  1492. CalcEncCropInfo(pHevc, rotMirMode, pOpenParam->picWidth, pOpenParam->picHeight);
  1493. /* SET_PARAM + COMMON */
  1494. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_SET_PARAM_OPTION, OPT_COMMON);
  1495. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_SET_PARAM_ENABLE, (unsigned int)ENC_CHANGE_SET_PARAM_ALL); // it doesn't need to set for WAVE520
  1496. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_SRC_SIZE, pOpenParam->picHeight<<16 | pOpenParam->picWidth);
  1497. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_MAP_ENDIAN, VDI_LITTLE_ENDIAN); // [fix me]
  1498. regVal = (pHevc->profile<<0) |
  1499. (pHevc->level<<3) |
  1500. (pHevc->tier<<12) |
  1501. (pHevc->internalBitDepth<<14) |
  1502. (pHevc->useLongTerm<<21) |
  1503. (pHevc->scalingListEnable<<22) |
  1504. (pHevc->tmvpEnable<<23) |
  1505. (pHevc->saoEnable<<24) |
  1506. (pHevc->skipIntraTrans<<25) |
  1507. (pHevc->strongIntraSmoothEnable<<27);
  1508. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_SYNTAX_SPS_PARAM, regVal);
  1509. regVal = (pHevc->losslessEnable) |
  1510. (pHevc->constIntraPredFlag<<1) |
  1511. (pHevc->lfCrossSliceBoundaryEnable<<2) |
  1512. (pHevc->weightPredEnable<<3) |
  1513. (pHevc->wppEnable<<4) |
  1514. (pHevc->disableDeblk<<5) |
  1515. ((pHevc->betaOffsetDiv2&0xF)<<6) |
  1516. ((pHevc->tcOffsetDiv2&0xF)<<10);
  1517. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_SYNTAX_PPS_PARAM, regVal);
  1518. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_GOP_PARAM, pHevc->gopPresetIdx);
  1519. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_INTRA_PARAM, (pHevc->decodingRefreshType<<0) | (pHevc->intraQP<<3) | (pHevc->intraPeriod<<16));
  1520. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CONF_WIN_TOP_BOT, pHevc->confWinBot<<16 | pHevc->confWinTop);
  1521. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CONF_WIN_LEFT_RIGHT, pHevc->confWinRight<<16 | pHevc->confWinLeft);
  1522. regVal = (pHevc->useRecommendEncParam) |
  1523. (pHevc->coefClearDisable<<4) |
  1524. (pHevc->cuSizeMode<<5) |
  1525. (pHevc->intraNxNEnable<<8) |
  1526. (pHevc->maxNumMerge<<18) |
  1527. (pHevc->customMDEnable<<20) |
  1528. (pHevc->customLambdaEnable<<21) |
  1529. (pHevc->monochromeEnable<<22);
  1530. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RDO_PARAM, regVal);
  1531. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_INDEPENDENT_SLICE, pHevc->independSliceModeArg<<16 | pHevc->independSliceMode);
  1532. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_DEPENDENT_SLICE, pHevc->dependSliceModeArg<<16 | pHevc->dependSliceMode);
  1533. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_INTRA_REFRESH, pHevc->intraRefreshArg<<16 | pHevc->intraRefreshMode);
  1534. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RC_FRAME_RATE, pOpenParam->frameRateInfo);
  1535. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RC_TARGET_RATE, pOpenParam->bitRate);
  1536. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RC_PARAM, (pOpenParam->rcEnable<<0) |
  1537. (pHevc->cuLevelRCEnable<<1) |
  1538. (pHevc->hvsQPEnable<<2) |
  1539. (pHevc->hvsQpScaleEnable<<3) |
  1540. (pHevc->hvsQpScale<<4) |
  1541. (pHevc->bitAllocMode<<8) |
  1542. (pHevc->ctuOptParam.roiEnable<<13) |
  1543. ((pHevc->initialRcQp&0x3F)<<14) |
  1544. (pOpenParam->initialDelay<<20));
  1545. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RC_MIN_MAX_QP, (pHevc->minQp<<0) |
  1546. (pHevc->maxQp<<6) |
  1547. (pHevc->maxDeltaQp<<12) |
  1548. ((pHevc->chromaCbQpOffset&0x1F)<<18) |
  1549. ((pHevc->chromaCrQpOffset&0x1F)<<23));
  1550. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_0_3, (pHevc->fixedBitRatio[0]<<0) |
  1551. (pHevc->fixedBitRatio[1]<<8) |
  1552. (pHevc->fixedBitRatio[2]<<16) |
  1553. (pHevc->fixedBitRatio[3]<<24));
  1554. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_4_7, (pHevc->fixedBitRatio[4]<<0) |
  1555. (pHevc->fixedBitRatio[5]<<8) |
  1556. (pHevc->fixedBitRatio[6]<<16) |
  1557. (pHevc->fixedBitRatio[7]<<24));
  1558. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_ROT_PARAM, rotMirMode);
  1559. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_NUM_UNITS_IN_TICK, pHevc->numUnitsInTick);
  1560. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_TIME_SCALE, pHevc->timeScale);
  1561. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_NUM_TICKS_POC_DIFF_ONE, pHevc->numTicksPocDiffOne);
  1562. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_MD_PU04, (pHevc->pu04DeltaRate&0xFF) |
  1563. ((pHevc->pu04IntraPlanarDeltaRate&0xFF)<<8) |
  1564. ((pHevc->pu04IntraDcDeltaRate&0xFF)<<16) |
  1565. ((pHevc->pu04IntraAngleDeltaRate&0xFF)<<24));
  1566. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_MD_PU08, (pHevc->pu08DeltaRate&0xFF) |
  1567. ((pHevc->pu08IntraPlanarDeltaRate&0xFF)<<8) |
  1568. ((pHevc->pu08IntraDcDeltaRate&0xFF)<<16) |
  1569. ((pHevc->pu08IntraAngleDeltaRate&0xFF)<<24));
  1570. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_MD_PU16, (pHevc->pu16DeltaRate&0xFF) |
  1571. ((pHevc->pu16IntraPlanarDeltaRate&0xFF)<<8) |
  1572. ((pHevc->pu16IntraDcDeltaRate&0xFF)<<16) |
  1573. ((pHevc->pu16IntraAngleDeltaRate&0xFF)<<24));
  1574. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_MD_PU32, (pHevc->pu32DeltaRate&0xFF) |
  1575. ((pHevc->pu32IntraPlanarDeltaRate&0xFF)<<8) |
  1576. ((pHevc->pu32IntraDcDeltaRate&0xFF)<<16) |
  1577. ((pHevc->pu32IntraAngleDeltaRate&0xFF)<<24));
  1578. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_MD_CU08, (pHevc->cu08IntraDeltaRate&0xFF) |
  1579. ((pHevc->cu08InterDeltaRate&0xFF)<<8) |
  1580. ((pHevc->cu08MergeDeltaRate&0xFF)<<16));
  1581. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_MD_CU16, (pHevc->cu16IntraDeltaRate&0xFF) |
  1582. ((pHevc->cu16InterDeltaRate&0xFF)<<8) |
  1583. ((pHevc->cu16MergeDeltaRate&0xFF)<<16));
  1584. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_MD_CU32, (pHevc->cu32IntraDeltaRate&0xFF) |
  1585. ((pHevc->cu32InterDeltaRate&0xFF)<<8) |
  1586. ((pHevc->cu32MergeDeltaRate&0xFF)<<16));
  1587. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_NR_PARAM, (pHevc->nrYEnable<<0) |
  1588. (pHevc->nrCbEnable<<1) |
  1589. (pHevc->nrCrEnable<<2) |
  1590. (pHevc->nrNoiseEstEnable<<3)|
  1591. (pHevc->nrNoiseSigmaY<<4) |
  1592. (pHevc->nrNoiseSigmaCb<<11) |
  1593. (pHevc->nrNoiseSigmaCr<<18));
  1594. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_NR_WEIGHT, (pHevc->nrIntraWeightY<<0) |
  1595. (pHevc->nrIntraWeightCb<<5) |
  1596. (pHevc->nrIntraWeightCr<<10)|
  1597. (pHevc->nrInterWeightY<<15) |
  1598. (pHevc->nrInterWeightCb<<20)|
  1599. (pHevc->nrInterWeightCr<<25));
  1600. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_BG_PARAM, (pHevc->bgDetectEnable) |
  1601. (pHevc->bgThrDiff<<1) |
  1602. (pHevc->bgThrMeanDiff<<10) |
  1603. (pHevc->bgLambdaQp<<18) |
  1604. ((pHevc->bgDeltaQp&0x1F)<<24));
  1605. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_LAMBDA_ADDR, pHevc->customLambdaAddr);
  1606. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_USER_SCALING_LIST_ADDR, pHevc->userScalingListAddr);
  1607. Wave5BitIssueCommand(instance, W5_ENC_SET_PARAM);
  1608. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) {
  1609. if (instance->loggingEnable)
  1610. vdi_log(coreIdx, W5_ENC_SET_PARAM, 2);
  1611. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1612. }
  1613. if (VpuReadReg(coreIdx, W5_RET_SUCCESS) == 0) {
  1614. if (VpuReadReg(coreIdx, W5_RET_FAIL_REASON) == 1) {
  1615. return RETCODE_QUEUEING_FAILURE;
  1616. }
  1617. return RETCODE_FAILURE;
  1618. }
  1619. return RETCODE_SUCCESS;
  1620. }
  1621. RetCode Wave5VpuEncGetSeqInfo(CodecInst* instance, EncInitialInfo* info)
  1622. {
  1623. RetCode ret = RETCODE_SUCCESS;
  1624. Uint32 regVal, seqInitErrReason;
  1625. EncInfo* pEncInfo;
  1626. pEncInfo = VPU_HANDLE_TO_ENCINFO(instance);
  1627. // Send QUERY cmd
  1628. ret = SendQuery(instance, GET_RESULT);
  1629. if (ret != RETCODE_SUCCESS) {
  1630. return RETCODE_QUERY_FAILURE;
  1631. }
  1632. if (instance->loggingEnable)
  1633. vdi_log(instance->coreIdx, W5_INIT_SEQ, 0);
  1634. regVal = VpuReadReg(instance->coreIdx, W5_RET_QUEUE_STATUS);
  1635. pEncInfo->instanceQueueCount = (regVal>>16)&0xff;
  1636. pEncInfo->totalQueueCount = (regVal & 0xffff);
  1637. if (VpuReadReg(instance->coreIdx, W5_RET_ENC_ENCODING_SUCCESS) != 1) {
  1638. seqInitErrReason = VpuReadReg(instance->coreIdx, W5_RET_ENC_ERR_INFO);
  1639. if (seqInitErrReason == WAVE5_SYSERR_ACCESS_VIOLATION_HW)
  1640. ret = RETCODE_MEMORY_ACCESS_VIOLATION;
  1641. else
  1642. ret = RETCODE_FAILURE;
  1643. }
  1644. regVal = VpuReadReg(instance->coreIdx, W5_RET_DONE_INSTANCE_INFO);
  1645. info->minFrameBufferCount = VpuReadReg(instance->coreIdx, W5_RET_ENC_MIN_FB_NUM);
  1646. info->minSrcFrameCount = VpuReadReg(instance->coreIdx, W5_RET_ENC_MIN_SRC_BUF_NUM);
  1647. return ret;
  1648. }
  1649. RetCode Wave5VpuEncRegisterFramebuffer(CodecInst* inst, FrameBuffer* fbArr, TiledMapType mapType, Uint32 count)
  1650. {
  1651. RetCode ret = RETCODE_SUCCESS;
  1652. Int32 q, j, i, remain, idx, bufHeight = 0, bufWidth = 0, coreIdx, startNo, endNo, stride;
  1653. Uint32 regVal=0, picSize=0, mvColSize, fbcYTblSize, fbcCTblSize, subSampledSize;
  1654. Uint32 endian, nv21=0, cbcrInterleave = 0, lumaStride, chromaStride;
  1655. Uint32 addrY, addrCb, addrCr;
  1656. vpu_buffer_t vbBuffer;
  1657. EncOpenParam* pOpenParam;
  1658. EncInfo* pEncInfo = &inst->CodecInfo->encInfo;
  1659. pOpenParam = &pEncInfo->openParam;
  1660. coreIdx = inst->coreIdx;
  1661. mvColSize = fbcYTblSize = fbcCTblSize = 0;
  1662. stride = pEncInfo->stride;
  1663. bufWidth = VPU_ALIGN8(pOpenParam->picWidth);
  1664. bufHeight = VPU_ALIGN8(pOpenParam->picHeight);
  1665. if ((pEncInfo->rotationAngle != 0 || pEncInfo->mirrorDirection != 0) && !(pEncInfo->rotationAngle == 180 && pEncInfo->mirrorDirection == MIRDIR_HOR_VER)) {
  1666. bufWidth = VPU_ALIGN32(pOpenParam->picWidth);
  1667. bufHeight = VPU_ALIGN32(pOpenParam->picHeight);
  1668. }
  1669. if (pEncInfo->rotationAngle == 90 || pEncInfo->rotationAngle == 270) {
  1670. bufWidth = VPU_ALIGN32(pOpenParam->picHeight);
  1671. bufHeight = VPU_ALIGN32(pOpenParam->picWidth);
  1672. }
  1673. picSize = (bufWidth<<16) | bufHeight;
  1674. if (mapType == COMPRESSED_FRAME_MAP) {
  1675. nv21 = 0;
  1676. cbcrInterleave = 0;
  1677. mvColSize = WAVE5_ENC_HEVC_MVCOL_BUF_SIZE(bufWidth, bufHeight);
  1678. mvColSize = VPU_ALIGN16(mvColSize);
  1679. vbBuffer.phys_addr = 0;
  1680. vbBuffer.size = ((mvColSize*count+4095)&~4095)+4096; /* 4096 is a margin */
  1681. if (vdi_allocate_dma_memory(inst->coreIdx, &vbBuffer) < 0)
  1682. return RETCODE_INSUFFICIENT_RESOURCE;
  1683. pEncInfo->vbMV = vbBuffer;
  1684. fbcYTblSize = WAVE5_FBC_LUMA_TABLE_SIZE(bufWidth, bufHeight);
  1685. fbcYTblSize = VPU_ALIGN16(fbcYTblSize);
  1686. vbBuffer.phys_addr = 0;
  1687. vbBuffer.size = ((fbcYTblSize*count+4095)&~4095)+4096;
  1688. if (vdi_allocate_dma_memory(inst->coreIdx, &vbBuffer) < 0)
  1689. return RETCODE_INSUFFICIENT_RESOURCE;
  1690. pEncInfo->vbFbcYTbl = vbBuffer;
  1691. fbcCTblSize = WAVE5_FBC_CHROMA_TABLE_SIZE(bufWidth, bufHeight);
  1692. fbcCTblSize = VPU_ALIGN16(fbcCTblSize);
  1693. vbBuffer.phys_addr = 0;
  1694. vbBuffer.size = ((fbcCTblSize*count+4095)&~4095)+4096;
  1695. if (vdi_allocate_dma_memory(inst->coreIdx, &vbBuffer) < 0)
  1696. return RETCODE_INSUFFICIENT_RESOURCE;
  1697. pEncInfo->vbFbcCTbl = vbBuffer;
  1698. subSampledSize = WAVE5_SUBSAMPLED_ONE_SIZE(bufWidth, bufHeight);
  1699. vbBuffer.size = ((subSampledSize*count+4095)&~4095)+4096;
  1700. vbBuffer.phys_addr = 0;
  1701. if (vdi_allocate_dma_memory(coreIdx, &vbBuffer) < 0)
  1702. return RETCODE_INSUFFICIENT_RESOURCE;
  1703. pEncInfo->vbSubSamBuf = vbBuffer;
  1704. }
  1705. VpuWriteReg(coreIdx, W5_ADDR_SUB_SAMPLED_FB_BASE, pEncInfo->vbSubSamBuf.phys_addr); // set sub-sampled buffer base addr
  1706. VpuWriteReg(coreIdx, W5_SUB_SAMPLED_ONE_FB_SIZE, subSampledSize); // set sub-sampled buffer size for one frame
  1707. endian = vdi_convert_endian(coreIdx, fbArr[0].endian) & VDI_128BIT_ENDIAN_MASK;
  1708. VpuWriteReg(coreIdx, W5_PIC_SIZE, picSize);
  1709. // set stride of Luma/Chroma for compressed buffer
  1710. if ((pEncInfo->rotationAngle != 0 || pEncInfo->mirrorDirection != 0) && !(pEncInfo->rotationAngle == 180 && pEncInfo->mirrorDirection == MIRDIR_HOR_VER)){
  1711. lumaStride = VPU_ALIGN32(bufWidth)*(pOpenParam->EncStdParam.hevcParam.internalBitDepth >8 ? 5 : 4);
  1712. lumaStride = VPU_ALIGN32(lumaStride);
  1713. chromaStride = VPU_ALIGN16(bufWidth/2)*(pOpenParam->EncStdParam.hevcParam.internalBitDepth >8 ? 5 : 4);
  1714. chromaStride = VPU_ALIGN32(chromaStride);
  1715. }
  1716. else {
  1717. lumaStride = VPU_ALIGN16(pOpenParam->picWidth)*(pOpenParam->EncStdParam.hevcParam.internalBitDepth >8 ? 5 : 4);
  1718. lumaStride = VPU_ALIGN32(lumaStride);
  1719. chromaStride = VPU_ALIGN16(pOpenParam->picWidth/2)*(pOpenParam->EncStdParam.hevcParam.internalBitDepth >8 ? 5 : 4);
  1720. chromaStride = VPU_ALIGN32(chromaStride);
  1721. }
  1722. VpuWriteReg(coreIdx, W5_FBC_STRIDE, lumaStride<<16 | chromaStride);
  1723. cbcrInterleave = pOpenParam->cbcrInterleave;
  1724. stride = pEncInfo->stride;
  1725. regVal =(nv21 << 29) |
  1726. (cbcrInterleave << 16) |
  1727. (stride);
  1728. VpuWriteReg(coreIdx, W5_COMMON_PIC_INFO, regVal);
  1729. remain = count;
  1730. q = (remain+7)/8;
  1731. idx = 0;
  1732. for (j=0; j<q; j++) {
  1733. regVal = (endian<<16) | (j==q-1)<<4 | ((j==0)<<3) ;
  1734. VpuWriteReg(coreIdx, W5_SFB_OPTION, regVal);
  1735. startNo = j*8;
  1736. endNo = startNo + (remain>=8 ? 8 : remain) - 1;
  1737. VpuWriteReg(coreIdx, W5_SET_FB_NUM, (startNo<<8)|endNo);
  1738. for (i=0; i<8 && i<remain; i++) {
  1739. if (mapType == LINEAR_FRAME_MAP && pEncInfo->openParam.cbcrOrder == CBCR_ORDER_REVERSED) {
  1740. addrY = fbArr[i+startNo].bufY;
  1741. addrCb = fbArr[i+startNo].bufCr;
  1742. addrCr = fbArr[i+startNo].bufCb;
  1743. }
  1744. else {
  1745. addrY = fbArr[i+startNo].bufY;
  1746. addrCb = fbArr[i+startNo].bufCb;
  1747. addrCr = fbArr[i+startNo].bufCr;
  1748. }
  1749. VpuWriteReg(coreIdx, W5_ADDR_LUMA_BASE0 + (i<<4), addrY);
  1750. VpuWriteReg(coreIdx, W5_ADDR_CB_BASE0 + (i<<4), addrCb);
  1751. APIDPRINT("REGISTER FB[%02d] Y(0x%08x), Cb(0x%08x) ", i, addrY, addrCb);
  1752. if (mapType == COMPRESSED_FRAME_MAP) {
  1753. VpuWriteReg(coreIdx, W5_ADDR_FBC_Y_OFFSET0 + (i<<4), pEncInfo->vbFbcYTbl.phys_addr+idx*fbcYTblSize); /* Luma FBC offset table */
  1754. VpuWriteReg(coreIdx, W5_ADDR_FBC_C_OFFSET0 + (i<<4), pEncInfo->vbFbcCTbl.phys_addr+idx*fbcCTblSize); /* Chroma FBC offset table */
  1755. VpuWriteReg(coreIdx, W5_ADDR_MV_COL0 + (i<<2), pEncInfo->vbMV.phys_addr+idx*mvColSize);
  1756. APIDPRINT("Yo(0x%08x) Co(0x%08x), Mv(0x%08x)\n",
  1757. pEncInfo->vbFbcYTbl.phys_addr+idx*fbcYTblSize,
  1758. pEncInfo->vbFbcCTbl.phys_addr+idx*fbcCTblSize,
  1759. pEncInfo->vbMV.phys_addr+idx*mvColSize);
  1760. }
  1761. else {
  1762. VpuWriteReg(coreIdx, W5_ADDR_CR_BASE0 + (i<<4), addrCr);
  1763. VpuWriteReg(coreIdx, W5_ADDR_FBC_C_OFFSET0 + (i<<4), 0);
  1764. VpuWriteReg(coreIdx, W5_ADDR_MV_COL0 + (i<<2), 0);
  1765. APIDPRINT("Cr(0x%08x)\n", addrCr);
  1766. }
  1767. idx++;
  1768. }
  1769. remain -= i;
  1770. Wave5BitIssueCommand(inst, W5_SET_FB);
  1771. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) {
  1772. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1773. }
  1774. }
  1775. regVal = VpuReadReg(coreIdx, W5_RET_SUCCESS);
  1776. if (regVal == 0) {
  1777. return RETCODE_FAILURE;
  1778. }
  1779. if (ConfigSecAXIWave(coreIdx, inst->codecMode,
  1780. &pEncInfo->secAxiInfo, pOpenParam->picWidth, pOpenParam->picHeight,
  1781. pOpenParam->EncStdParam.hevcParam.profile, pOpenParam->EncStdParam.hevcParam.level) == 0) {
  1782. return RETCODE_INSUFFICIENT_RESOURCE;
  1783. }
  1784. return ret;
  1785. }
  1786. RetCode Wave5VpuEncode(CodecInst* instance, EncParam* option)
  1787. {
  1788. Int32 coreIdx, srcFrameFormat, srcPixelFormat, packedFormat;
  1789. Uint32 regVal = 0, bsEndian;
  1790. Uint32 srcStrideC = 0;
  1791. EncInfo* pEncInfo;
  1792. FrameBuffer* pSrcFrame;
  1793. EncOpenParam* pOpenParam;
  1794. BOOL justified = W4_WTL_RIGHT_JUSTIFIED;
  1795. Uint32 formatNo = W4_WTL_PIXEL_8BIT;
  1796. coreIdx = instance->coreIdx;
  1797. pEncInfo = VPU_HANDLE_TO_ENCINFO(instance);
  1798. pOpenParam = &pEncInfo->openParam;
  1799. pSrcFrame = option->sourceFrame;
  1800. switch (pOpenParam->srcFormat) {
  1801. case FORMAT_420_P10_16BIT_MSB:
  1802. case FORMAT_YUYV_P10_16BIT_MSB:
  1803. case FORMAT_YVYU_P10_16BIT_MSB:
  1804. case FORMAT_UYVY_P10_16BIT_MSB:
  1805. case FORMAT_VYUY_P10_16BIT_MSB:
  1806. justified = W4_WTL_RIGHT_JUSTIFIED;
  1807. formatNo = W4_WTL_PIXEL_16BIT;
  1808. break;
  1809. case FORMAT_420_P10_16BIT_LSB:
  1810. case FORMAT_YUYV_P10_16BIT_LSB:
  1811. case FORMAT_YVYU_P10_16BIT_LSB:
  1812. case FORMAT_UYVY_P10_16BIT_LSB:
  1813. case FORMAT_VYUY_P10_16BIT_LSB:
  1814. justified = W4_WTL_LEFT_JUSTIFIED;
  1815. formatNo = W4_WTL_PIXEL_16BIT;
  1816. break;
  1817. case FORMAT_420_P10_32BIT_MSB:
  1818. case FORMAT_YUYV_P10_32BIT_MSB:
  1819. case FORMAT_YVYU_P10_32BIT_MSB:
  1820. case FORMAT_UYVY_P10_32BIT_MSB:
  1821. case FORMAT_VYUY_P10_32BIT_MSB:
  1822. justified = W4_WTL_RIGHT_JUSTIFIED;
  1823. formatNo = W4_WTL_PIXEL_32BIT;
  1824. break;
  1825. case FORMAT_420_P10_32BIT_LSB:
  1826. case FORMAT_YUYV_P10_32BIT_LSB:
  1827. case FORMAT_YVYU_P10_32BIT_LSB:
  1828. case FORMAT_UYVY_P10_32BIT_LSB:
  1829. case FORMAT_VYUY_P10_32BIT_LSB:
  1830. justified = W4_WTL_LEFT_JUSTIFIED;
  1831. formatNo = W4_WTL_PIXEL_32BIT;
  1832. break;
  1833. case FORMAT_420:
  1834. case FORMAT_YUYV:
  1835. case FORMAT_YVYU:
  1836. case FORMAT_UYVY:
  1837. case FORMAT_VYUY:
  1838. justified = W4_WTL_LEFT_JUSTIFIED;
  1839. formatNo = W4_WTL_PIXEL_8BIT;
  1840. break;
  1841. }
  1842. packedFormat = (pOpenParam->packedFormat >= 1) ? 1 : 0;
  1843. srcFrameFormat = packedFormat<<2 |
  1844. pOpenParam->cbcrInterleave<<1 |
  1845. pOpenParam->nv21;
  1846. switch (pOpenParam->packedFormat) { // additional packed format (interleave & nv21 bit are used to present these modes)
  1847. case PACKED_YVYU:
  1848. srcFrameFormat = 0x5;
  1849. break;
  1850. case PACKED_UYVY:
  1851. srcFrameFormat = 0x6;
  1852. break;
  1853. case PACKED_VYUY:
  1854. srcFrameFormat = 0x7;
  1855. break;
  1856. default:
  1857. break;
  1858. }
  1859. srcPixelFormat = justified<<2 | formatNo;
  1860. regVal = vdi_convert_endian(coreIdx, pOpenParam->streamEndian);
  1861. /* NOTE: When endian mode is 0, SDMA reads MSB first */
  1862. bsEndian = (~regVal&VDI_128BIT_ENDIAN_MASK);
  1863. VpuWriteReg(coreIdx, W5_CMD_ENC_BS_START_ADDR, option->picStreamBufferAddr);
  1864. VpuWriteReg(coreIdx, W5_CMD_ENC_BS_SIZE, option->picStreamBufferSize);
  1865. pEncInfo->streamRdPtr = option->picStreamBufferAddr;
  1866. pEncInfo->streamWrPtr = option->picStreamBufferAddr;
  1867. pEncInfo->streamBufStartAddr = option->picStreamBufferAddr;
  1868. pEncInfo->streamBufSize = option->picStreamBufferSize;
  1869. pEncInfo->streamBufEndAddr = option->picStreamBufferAddr + option->picStreamBufferSize;
  1870. VpuWriteReg(coreIdx, W5_BS_OPTION, (pEncInfo->lineBufIntEn<<6) | bsEndian);
  1871. /* Secondary AXI */
  1872. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_USE_SEC_AXI, (pEncInfo->secAxiInfo.u.wave4.useEncRdoEnable<<11) | (pEncInfo->secAxiInfo.u.wave4.useEncLfEnable<<15));
  1873. //VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_REPORT_PARAM, ); // FIX ME
  1874. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_REPORT_ENDIAN, VDI_128BIT_LITTLE_ENDIAN); // FIX ME
  1875. if (option->codeOption.implicitHeaderEncode == 1) {
  1876. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_CODE_OPTION, CODEOPT_ENC_HEADER_IMPLICIT | CODEOPT_ENC_VCL | // implicitly encode a header(headers) for generating bitstream. (to encode a header only, use ENC_PUT_VIDEO_HEADER for GiveCommand)
  1877. (option->codeOption.encodeAUD<<5) |
  1878. (option->codeOption.encodeEOS<<6) |
  1879. (option->codeOption.encodeEOB<<7));
  1880. }
  1881. else {
  1882. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_CODE_OPTION, (option->codeOption.implicitHeaderEncode<<0) |
  1883. (option->codeOption.encodeVCL<<1) |
  1884. (option->codeOption.encodeVPS<<2) |
  1885. (option->codeOption.encodeSPS<<3) |
  1886. (option->codeOption.encodePPS<<4) |
  1887. (option->codeOption.encodeAUD<<5) |
  1888. (option->codeOption.encodeEOS<<6) |
  1889. (option->codeOption.encodeEOB<<7) |
  1890. (option->codeOption.encodeFiller<<8));
  1891. }
  1892. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_PIC_PARAM, (option->skipPicture<<0) |
  1893. (option->forcePicQpEnable<<1) |
  1894. (option->forcePicQpI<<2) |
  1895. (option->forcePicQpP<<8) |
  1896. (option->forcePicQpB<<14) |
  1897. (option->forcePicTypeEnable<<20) |
  1898. (option->forcePicType<<21) |
  1899. (option->forceAllCtuCoefDropEnable<<24));
  1900. if (option->srcEndFlag == 1)
  1901. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_SRC_PIC_IDX, 0xFFFFFFFF); // no more source image.
  1902. else
  1903. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_SRC_PIC_IDX, option->srcIdx);
  1904. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_SRC_ADDR_Y, pSrcFrame->bufY);
  1905. if (pOpenParam->cbcrOrder == CBCR_ORDER_NORMAL) {
  1906. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_SRC_ADDR_U, pSrcFrame->bufCb);
  1907. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_SRC_ADDR_V, pSrcFrame->bufCr);
  1908. }
  1909. else {
  1910. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_SRC_ADDR_U, pSrcFrame->bufCr);
  1911. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_SRC_ADDR_V, pSrcFrame->bufCb);
  1912. }
  1913. if (formatNo == W4_WTL_PIXEL_32BIT) {
  1914. srcStrideC = VPU_ALIGN16(pSrcFrame->stride/2)*(1<<pSrcFrame->cbcrInterleave);
  1915. if ( pSrcFrame->cbcrInterleave == 1)
  1916. srcStrideC = pSrcFrame->stride;
  1917. }
  1918. else {
  1919. srcStrideC = (pSrcFrame->cbcrInterleave == 1) ? pSrcFrame->stride : (pSrcFrame->stride>>1);
  1920. }
  1921. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_SRC_STRIDE, (pSrcFrame->stride<<16) | srcStrideC );
  1922. regVal = vdi_convert_endian(coreIdx, pOpenParam->sourceEndian);
  1923. bsEndian = (~regVal&VDI_128BIT_ENDIAN_MASK);
  1924. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_SRC_FORMAT, (srcFrameFormat<<0) |
  1925. (srcPixelFormat<<3) |
  1926. (bsEndian<<6));
  1927. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_ADDR, option->customMapOpt.addrCustomMap);
  1928. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_PARAM, (option->customMapOpt.customRoiMapEnable << 0) |
  1929. (option->customMapOpt.roiAvgQp << 1) |
  1930. (option->customMapOpt.customLambdaMapEnable<< 8) |
  1931. (option->customMapOpt.customModeMapEnable<< 9) |
  1932. (option->customMapOpt.customCoefDropEnable<< 10));
  1933. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_LONGTERM_PIC, (option->useCurSrcAsLongtermPic<<0) | (option->useLongtermRef<<1));
  1934. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_WP_PIXEL_VAR_Y, option->wpPixVarianceY);
  1935. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_WP_PIXEL_VAR_CB, option->wpPixVarianceCb);
  1936. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_WP_PIXEL_VAR_CR, option->wpPixVarianceCr);
  1937. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_WP_PIXEL_MEAN, (option->wpPixMeanCr<<20) | (option->wpPixMeanCb<<10) | option->wpPixMeanY);
  1938. Wave5BitIssueCommand(instance, W5_ENC_PIC);
  1939. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) { // Check QUEUE_DONE
  1940. if (instance->loggingEnable)
  1941. vdi_log(instance->coreIdx, W5_ENC_PIC, 2);
  1942. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1943. }
  1944. regVal = VpuReadReg(instance->coreIdx, W5_RET_QUEUE_STATUS);
  1945. pEncInfo->instanceQueueCount = (regVal>>16)&0xff;
  1946. pEncInfo->totalQueueCount = (regVal & 0xffff);
  1947. if (VpuReadReg(instance->coreIdx, W5_RET_SUCCESS) == FALSE) { // FAILED for adding a command into VCPU QUEUE
  1948. regVal = VpuReadReg(instance->coreIdx, W5_RET_FAIL_REASON);
  1949. if (regVal == 1) {
  1950. return RETCODE_QUEUEING_FAILURE;
  1951. }
  1952. else if ( regVal == 16) {
  1953. return RETCODE_CP0_EXCEPTION;
  1954. }
  1955. else {
  1956. return RETCODE_FAILURE;
  1957. }
  1958. }
  1959. return RETCODE_SUCCESS;
  1960. }
  1961. RetCode Wave5VpuEncGetResult(CodecInst* instance, EncOutputInfo* result)
  1962. {
  1963. RetCode ret = RETCODE_SUCCESS;
  1964. Uint32 encodingSuccess, errorReason = 0;
  1965. Uint32 regVal;
  1966. Int32 coreIdx;
  1967. EncInfo* pEncInfo = VPU_HANDLE_TO_ENCINFO(instance);
  1968. coreIdx = instance->coreIdx;
  1969. ret = SendQuery(instance, GET_RESULT);
  1970. if (ret != RETCODE_SUCCESS) {
  1971. if (VpuReadReg(coreIdx, W5_RET_FAIL_REASON) == WAVE5_RESULT_NOT_READY)
  1972. return RETCODE_REPORT_NOT_READY;
  1973. else
  1974. return RETCODE_QUERY_FAILURE;
  1975. }
  1976. if (instance->loggingEnable)
  1977. vdi_log(coreIdx, W5_ENC_PIC, 0);
  1978. regVal = VpuReadReg(coreIdx, W5_RET_QUEUE_STATUS);
  1979. pEncInfo->instanceQueueCount = (regVal>>16)&0xff;
  1980. pEncInfo->totalQueueCount = (regVal & 0xffff);
  1981. encodingSuccess = VpuReadReg(coreIdx, W5_RET_ENC_ENCODING_SUCCESS);
  1982. if (encodingSuccess == FALSE) {
  1983. errorReason = VpuReadReg(coreIdx, W5_RET_ENC_ERR_INFO);
  1984. if (errorReason == WAVE5_SYSERR_ACCESS_VIOLATION_HW) {
  1985. return RETCODE_MEMORY_ACCESS_VIOLATION;
  1986. }
  1987. return RETCODE_FAILURE;
  1988. }
  1989. result->encPicCnt = VpuReadReg(coreIdx, W5_RET_ENC_PIC_NUM);
  1990. regVal= VpuReadReg(coreIdx, W5_RET_ENC_PIC_TYPE);
  1991. result->picType = regVal & 0xFFFF;
  1992. result->encVclNal = VpuReadReg(coreIdx, W5_RET_ENC_VCL_NUT);
  1993. result->reconFrameIndex = VpuReadReg(coreIdx, W5_RET_ENC_PIC_IDX);
  1994. if (result->reconFrameIndex >= 0)
  1995. result->reconFrame = pEncInfo->frameBufPool[result->reconFrameIndex];
  1996. result->numOfSlices = VpuReadReg(coreIdx, W5_RET_ENC_PIC_SLICE_NUM);
  1997. result->picSkipped = VpuReadReg(coreIdx, W5_RET_ENC_PIC_SKIP);
  1998. result->numOfIntra = VpuReadReg(coreIdx, W5_RET_ENC_PIC_NUM_INTRA);
  1999. result->numOfMerge = VpuReadReg(coreIdx, W5_RET_ENC_PIC_NUM_MERGE);
  2000. result->numOfSkipBlock = VpuReadReg(coreIdx, W5_RET_ENC_PIC_NUM_SKIP);
  2001. result->bitstreamWrapAround = 0; // wave520 only support line-buffer mode.
  2002. result->avgCtuQp = VpuReadReg(coreIdx, W5_RET_ENC_PIC_AVG_CTU_QP);
  2003. result->encPicByte = VpuReadReg(coreIdx, W5_RET_ENC_PIC_BYTE);
  2004. result->encGopPicIdx = VpuReadReg(coreIdx, W5_RET_ENC_GOP_PIC_IDX);
  2005. result->encPicPoc = VpuReadReg(coreIdx, W5_RET_ENC_PIC_POC);
  2006. result->encSrcIdx = VpuReadReg(coreIdx, W5_RET_ENC_USED_SRC_IDX);
  2007. pEncInfo->streamWrPtr = VpuReadReg(coreIdx, pEncInfo->streamWrPtrRegAddr);
  2008. pEncInfo->streamRdPtr = VpuReadReg(coreIdx, pEncInfo->streamRdPtrRegAddr);
  2009. if (pEncInfo->ringBufferEnable == 0) {
  2010. result->bitstreamBuffer = VpuReadReg(coreIdx, pEncInfo->streamRdPtrRegAddr);
  2011. }
  2012. result->rdPtr = pEncInfo->streamRdPtr;
  2013. result->wrPtr = pEncInfo->streamWrPtr;
  2014. if (result->reconFrameIndex < 0)
  2015. result->bitstreamSize = 0;
  2016. else
  2017. result->bitstreamSize = result->encPicByte;
  2018. result->frameCycle = VpuReadReg(coreIdx, W5_FRAME_CYCLE);
  2019. result->encPrepareCycle = VpuReadReg(coreIdx, W5_RET_ENC_PREPARE_CYCLE);
  2020. result->encProcessingCycle = VpuReadReg(coreIdx, W5_RET_ENC_PROCESSING_CYCLE);
  2021. result->encEncodingCycle = VpuReadReg(coreIdx, W5_RET_ENC_ENCODING_CYCLE);
  2022. return RETCODE_SUCCESS;
  2023. }
  2024. RetCode Wave5VpuEncGetHeader(EncHandle instance, EncHeaderParam * encHeaderParam)
  2025. {
  2026. Int32 coreIdx;
  2027. Uint32 regVal = 0, bsEndian;
  2028. EncInfo* pEncInfo;
  2029. EncOpenParam* pOpenParam;
  2030. coreIdx = instance->coreIdx;
  2031. pEncInfo = VPU_HANDLE_TO_ENCINFO(instance);
  2032. pOpenParam = &pEncInfo->openParam;
  2033. EnterLock(coreIdx);
  2034. regVal = vdi_convert_endian(coreIdx, pOpenParam->streamEndian);
  2035. /* NOTE: When endian mode is 0, SDMA reads MSB first */
  2036. bsEndian = (~regVal&VDI_128BIT_ENDIAN_MASK);
  2037. VpuWriteReg(coreIdx, W5_CMD_ENC_BS_START_ADDR, encHeaderParam->buf);
  2038. VpuWriteReg(coreIdx, W5_CMD_ENC_BS_SIZE, encHeaderParam->size);
  2039. pEncInfo->streamRdPtr = encHeaderParam->buf;
  2040. pEncInfo->streamWrPtr = encHeaderParam->buf;
  2041. pEncInfo->streamBufStartAddr = encHeaderParam->buf;
  2042. pEncInfo->streamBufSize = encHeaderParam->size;
  2043. pEncInfo->streamBufEndAddr = encHeaderParam->buf + encHeaderParam->size;
  2044. VpuWriteReg(coreIdx, W5_BS_OPTION, (pEncInfo->lineBufIntEn<<6) | bsEndian);
  2045. /* Secondary AXI */
  2046. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_USE_SEC_AXI, (pEncInfo->secAxiInfo.u.wave4.useEncImdEnable<<9) |
  2047. (pEncInfo->secAxiInfo.u.wave4.useEncRdoEnable<<11) |
  2048. (pEncInfo->secAxiInfo.u.wave4.useEncLfEnable<<15));
  2049. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_CODE_OPTION, encHeaderParam->headerType);
  2050. VpuWriteReg(coreIdx, W5_CMD_ENC_PIC_SRC_PIC_IDX, 0);
  2051. Wave5BitIssueCommand(instance, W5_ENC_PIC);
  2052. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1) { // Check QUEUE_DONE
  2053. if (instance->loggingEnable)
  2054. vdi_log(instance->coreIdx, W5_ENC_PIC, 2);
  2055. LeaveLock(coreIdx);
  2056. return RETCODE_VPU_RESPONSE_TIMEOUT;
  2057. }
  2058. regVal = VpuReadReg(instance->coreIdx, W5_RET_QUEUE_STATUS);
  2059. pEncInfo->instanceQueueCount = (regVal>>16)&0xff;
  2060. pEncInfo->totalQueueCount = (regVal & 0xffff);
  2061. if (VpuReadReg(instance->coreIdx, W5_RET_SUCCESS) == FALSE) { // FAILED for adding a command into VCPU QUEUE
  2062. if (VpuReadReg(instance->coreIdx, W5_RET_FAIL_REASON) == 1) {
  2063. LeaveLock(coreIdx);
  2064. return RETCODE_QUEUEING_FAILURE;
  2065. } else {
  2066. LeaveLock(coreIdx);
  2067. return RETCODE_FAILURE;
  2068. }
  2069. }
  2070. LeaveLock(coreIdx);
  2071. return RETCODE_SUCCESS;
  2072. }
  2073. RetCode Wave5VpuEncFiniSeq(CodecInst* instance )
  2074. {
  2075. Wave5BitIssueCommand(instance, W5_DESTROY_INSTANCE);
  2076. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W5_VPU_BUSY_STATUS) == -1)
  2077. return RETCODE_VPU_RESPONSE_TIMEOUT;
  2078. if (VpuReadReg(instance->coreIdx, W5_RET_SUCCESS) == FALSE)
  2079. return RETCODE_FAILURE;
  2080. return RETCODE_SUCCESS;
  2081. }
  2082. RetCode Wave5VpuEncParaChange(EncHandle instance, EncChangeParam* param)
  2083. {
  2084. Int32 coreIdx;
  2085. Uint32 regVal = 0;
  2086. EncInfo* pEncInfo;
  2087. coreIdx = instance->coreIdx;
  2088. pEncInfo = &instance->CodecInfo->encInfo;
  2089. EnterLock(coreIdx);
  2090. /* SET_PARAM + COMMON */
  2091. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_SET_PARAM_OPTION, OPT_CHANGE_PARAM);
  2092. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_SET_PARAM_ENABLE, param->enable_option);
  2093. if (param->enable_option & ENC_SET_PPS_PARAM_CHANGE) {
  2094. regVal = (param->losslessEnable) |
  2095. (param->constIntraPredFlag<<1) |
  2096. (param->lfCrossSliceBoundaryEnable<<2) |
  2097. (param->weightPredEnable<<3) |
  2098. (param->wppEnable<<4) |
  2099. (param->disableDeblk<<5) |
  2100. ((param->betaOffsetDiv2&0xF)<<6) |
  2101. ((param->tcOffsetDiv2&0xF)<<10);
  2102. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_SYNTAX_PPS_PARAM, regVal);
  2103. }
  2104. if (param->enable_option & ENC_SET_RC_FRAMERATE_CHANGE) {
  2105. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RC_FRAME_RATE, param->frameRate);
  2106. }
  2107. if (param->enable_option & ENC_SET_INDEPEND_SLICE_CHANGE) {
  2108. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_INDEPENDENT_SLICE, param->independSliceModeArg<<16 | param->independSliceMode);
  2109. }
  2110. if (param->enable_option & ENC_SET_DEPEND_SLICE_CHANGE) {
  2111. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_DEPENDENT_SLICE, param->dependSliceModeArg<<16 | param->dependSliceMode);
  2112. }
  2113. if (param->enable_option & ENC_SET_RDO_PARAM_CHANGE) {
  2114. regVal = (param->useRecommendEncParam) |
  2115. (param->coefClearDisable<<4) |
  2116. (param->cuSizeMode<<5) |
  2117. (param->intraNxNEnable<<8) |
  2118. (param->maxNumMerge<<18) |
  2119. (param->customMDEnable<<20) |
  2120. (param->customLambdaEnable<<11) |
  2121. (param->monochromeEnable<<22);
  2122. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RDO_PARAM, regVal);
  2123. }
  2124. if (param->enable_option & ENC_SET_RC_TARGET_RATE_CHANGE) {
  2125. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RC_TARGET_RATE, param->bitRate);
  2126. }
  2127. if (param->enable_option & ENC_SET_RC_PARAM_CHANGE) {
  2128. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RC_PARAM, (param->rcEnable<<0) |
  2129. (param->cuLevelRCEnable<<1) |
  2130. (param->hvsQPEnable<<2) |
  2131. (param->hvsQpScaleEnable<<3) |
  2132. (param->hvsQpScale<<4) |
  2133. (param->bitAllocMode<<8) |
  2134. (param->seqRoiEnable<<13) |
  2135. ((param->initialRcQp &0x3F)<<14) |
  2136. (param->initialDelay<<16));
  2137. }
  2138. if (param->enable_option & ENC_SET_RC_MIN_MAX_QP_CHANGE) {
  2139. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RC_MIN_MAX_QP, (param->minQp<<0) |
  2140. (param->maxQp<<6) |
  2141. (param->maxDeltaQp<<12) |
  2142. ((param->chromaCbQpOffset&0x1F)<<18) |
  2143. ((param->chromaCrQpOffset&0x1F)<<23));
  2144. }
  2145. if (param->enable_option & ENC_SET_RC_BIT_RATIO_LAYER_CHANGE) {
  2146. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_0_3, (param->fixedBitRatio[0]<<0) |
  2147. (param->fixedBitRatio[1]<<8) |
  2148. (param->fixedBitRatio[2]<<16) |
  2149. (param->fixedBitRatio[3]<<24));
  2150. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_4_7, (param->fixedBitRatio[4]<<0) |
  2151. (param->fixedBitRatio[5]<<8) |
  2152. (param->fixedBitRatio[6]<<16) |
  2153. (param->fixedBitRatio[7]<<24));
  2154. }
  2155. if (param->enable_option & ENC_SET_BG_PARAM_CHANGE) {
  2156. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_BG_PARAM, (param->bgDetectEnable) |
  2157. (param->bgThrDiff<<1) |
  2158. (param->bgThrMeanDiff<<10) |
  2159. (param->bgLambdaQp<<18) |
  2160. ((param->bgDeltaQp&0x1F)<<24));
  2161. }
  2162. if (param->enable_option & ENC_SET_CUSTOM_MD_CHANGE) {
  2163. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_MD_PU04, (param->pu04DeltaRate&0xFF) |
  2164. ((param->pu04IntraPlanarDeltaRate&0xFF)<<8) |
  2165. ((param->pu04IntraDcDeltaRate&0xFF)<<16) |
  2166. ((param->pu04IntraAngleDeltaRate&0xFF)<<24));
  2167. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_MD_PU08, (param->pu08DeltaRate&0xFF) |
  2168. ((param->pu08IntraPlanarDeltaRate&0xFF)<<8) |
  2169. ((param->pu08IntraDcDeltaRate&0xFF)<<16) |
  2170. ((param->pu08IntraAngleDeltaRate&0xFF)<<24));
  2171. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_MD_PU16, (param->pu16DeltaRate&0xFF) |
  2172. ((param->pu16IntraPlanarDeltaRate&0xFF)<<8) |
  2173. ((param->pu16IntraDcDeltaRate&0xFF)<<16) |
  2174. ((param->pu16IntraAngleDeltaRate&0xFF)<<24));
  2175. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_MD_PU32, (param->pu32DeltaRate&0xFF) |
  2176. ((param->pu32IntraPlanarDeltaRate&0xFF)<<8) |
  2177. ((param->pu32IntraDcDeltaRate&0xFF)<<16) |
  2178. ((param->pu32IntraAngleDeltaRate&0xFF)<<24));
  2179. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_MD_CU08, (param->cu08IntraDeltaRate&0xFF) |
  2180. ((param->cu08InterDeltaRate&0xFF)<<8) |
  2181. ((param->cu08MergeDeltaRate&0xFF)<<16));
  2182. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_MD_CU16, (param->cu16IntraDeltaRate&0xFF) |
  2183. ((param->cu16InterDeltaRate&0xFF)<<8) |
  2184. ((param->cu16MergeDeltaRate&0xFF)<<16));
  2185. VpuWriteReg(coreIdx, W5_CMD_ENC_SEQ_CUSTOM_MD_CU32, (param->cu32IntraDeltaRate&0xFF) |
  2186. ((param->cu32InterDeltaRate&0xFF)<<8) |
  2187. ((param->cu32MergeDeltaRate&0xFF)<<16));
  2188. }
  2189. Wave5BitIssueCommand(instance, W5_ENC_SET_PARAM);
  2190. if (vdi_wait_interrupt(coreIdx, VPU_ENC_TIMEOUT, W5_VPU_VINT_REASON) == -1) {
  2191. if (instance->loggingEnable)
  2192. vdi_log(coreIdx, W5_ENC_SET_PARAM, 2);
  2193. LeaveLock(coreIdx);
  2194. return RETCODE_VPU_RESPONSE_TIMEOUT;
  2195. }
  2196. regVal = VpuReadReg(coreIdx, W5_RET_QUEUE_STATUS);
  2197. pEncInfo->instanceQueueCount = (regVal>>16) & 0xFF;
  2198. pEncInfo->totalQueueCount = (regVal & 0xFFFF);
  2199. if (VpuReadReg(coreIdx, W5_RET_SUCCESS) == 0) {
  2200. if (VpuReadReg(coreIdx, W5_RET_FAIL_REASON) == 1) {
  2201. LeaveLock(coreIdx);
  2202. return RETCODE_QUEUEING_FAILURE;
  2203. }
  2204. LeaveLock(coreIdx);
  2205. return RETCODE_FAILURE;
  2206. }
  2207. LeaveLock(coreIdx);
  2208. return RETCODE_SUCCESS;
  2209. }
  2210. #ifdef SUPPORT_W5ENC_BW_REPORT
  2211. RetCode Wave5VpuEncGetBwReport(EncHandle instance, EncBwMonitor* bwMon)
  2212. {
  2213. RetCode ret = RETCODE_SUCCESS;
  2214. Int32 coreIdx;
  2215. coreIdx = instance->coreIdx;
  2216. ret = SendQuery(instance, GET_BW_REPORT);
  2217. if (ret != RETCODE_SUCCESS) {
  2218. if (VpuReadReg(coreIdx, W5_RET_FAIL_REASON) == WAVE5_RESULT_NOT_READY)
  2219. return RETCODE_REPORT_NOT_READY;
  2220. else
  2221. return RETCODE_QUERY_FAILURE;
  2222. }
  2223. bwMon->prpBwRead = VpuReadReg(coreIdx, RET_QUERY_BW_PRP_AXI_READ);
  2224. bwMon->prpBwWrite = VpuReadReg(coreIdx, RET_QUERY_BW_PRP_AXI_WRITE);
  2225. bwMon->fbdYRead = VpuReadReg(coreIdx, RET_QUERY_BW_FBD_Y_AXI_READ);
  2226. bwMon->fbcYWrite = VpuReadReg(coreIdx, RET_QUERY_BW_FBC_Y_AXI_WRITE);
  2227. bwMon->fbdCRead = VpuReadReg(coreIdx, RET_QUERY_BW_FBD_C_AXI_READ);
  2228. bwMon->fbcCWrite = VpuReadReg(coreIdx, RET_QUERY_BW_FBC_C_AXI_WRITE);
  2229. bwMon->priBwRead = VpuReadReg(coreIdx, RET_QUERY_BW_PRI_AXI_READ);
  2230. bwMon->priBwWrite = VpuReadReg(coreIdx, RET_QUERY_BW_PRI_AXI_WRITE);
  2231. bwMon->secBwRead = VpuReadReg(coreIdx, RET_QUERY_BW_SEC_AXI_READ);
  2232. bwMon->secBwWrite = VpuReadReg(coreIdx, RET_QUERY_BW_SEC_AXI_WRITE);
  2233. bwMon->procBwRead = VpuReadReg(coreIdx, RET_QUERY_BW_PROC_AXI_READ);
  2234. bwMon->procBwWrite = VpuReadReg(coreIdx, RET_QUERY_BW_PROC_AXI_WRITE);
  2235. return RETCODE_SUCCESS;
  2236. }
  2237. #endif