wave4_regdefine.h 17 KB

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  1. /* SPDX-License-Identifier: LGPL-2.1 OR BSD-3-Clause */
  2. //--=========================================================================--
  3. // This file is a part of VPU Reference API project
  4. //-----------------------------------------------------------------------------
  5. //
  6. // This confidential and proprietary software may be used only
  7. // as authorized by a licensing agreement from Chips&Media Inc.
  8. // In the event of publication, the following notice is applicable:
  9. //
  10. // (C) COPYRIGHT 2006 - 2013 CHIPS&MEDIA INC.
  11. // ALL RIGHTS RESERVED
  12. //
  13. // The entire notice above must be reproduced on all authorized
  14. // copies.
  15. //
  16. //--=========================================================================--
  17. #ifndef __WAVE410_REGISTER_DEFINE_H__
  18. #define __WAVE410_REGISTER_DEFINE_H__
  19. #define W4_REG_BASE 0x00000000
  20. #define W4_CMD_REG_BASE 0x00000100
  21. #define W4_CMD_REG_END 0x00000200
  22. /************************************************************************/
  23. /* DECODER - DEC_PIC_HDR/DEC_PIC */
  24. /************************************************************************/
  25. #define W4_CMD_DEC_USER_MASK (W4_REG_BASE + 0x0174)
  26. #define W4_CMD_DEC_SEVERITY_LEVEL (W4_REG_BASE + 0x0178)
  27. #define W4_CMD_DEC_VCORE_LIMIT (W4_REG_BASE + 0x017C)
  28. #define W4_CMD_DEC_SKIP_OPTION (W4_REG_BASE + 0x0184)
  29. #define W4_CMD_DEC_FORCE_FB_LATENCY_PLUS1 (W4_REG_BASE + 0x0188)
  30. #define W4_CMD_DEC_TEMPORAL_ID_PLUS1 (W4_REG_BASE + 0x018C)
  31. /* Sequence change enable mask register
  32. * CMD_SEQ_CHANGE_ENABLE_FLAG [5] profile_idc
  33. * [16] pic_width/height_in_luma_sample
  34. * [19] sps_max_dec_pic_buffering, max_num_reorder, max_latency_increase
  35. */
  36. #define W4_CMD_SEQ_CHANGE_ENABLE_FLAG (W4_REG_BASE + 0x0194)
  37. #define W4_RET_DEC_USER_MASK (W4_REG_BASE + 0x0174)
  38. /* Profile/Level/Tier/Max sublayers...
  39. * LEVEL_IDC [7:0] general_level_idc
  40. * FRAME_ONLY_CONSTRAINT_FLAG [8] general_frame_only_constraint_flag
  41. * NON_PACKED_CONSTRAINT_FLAG [9] general_non_packed_constraint_flag
  42. * INTERLACE_SOUCE_FLAG [10] general_interlaced_source_flag
  43. * PROGRESSIVE_SOURCE_FLAG [11] general_progressive_source_flag
  44. * PROFILE_COMPATIBLE_FLAG[8] [19:12]
  45. * SPS_MAX_SUB_LAYER [23:21]
  46. * PROFILE_IDC [28:24]
  47. * TIER_FLAG [29]
  48. * PROFILE_SPACE [31:30]
  49. */
  50. #define W4_RET_DEC_SEQ_PARAM (W4_REG_BASE + 0x0198)
  51. #define W4_RET_DEC_DECODED_ID (W4_REG_BASE + 0x019C)
  52. #define W4_RET_DEC_COLOR_SAMPLE_INFO (W4_REG_BASE + 0x01A0)
  53. #define W4_RET_DEC_ASPECT_RATIO (W4_REG_BASE + 0x01A4)
  54. #define W4_RET_DEC_BIT_RATE (W4_REG_BASE + 0x01A8)
  55. #define W4_RET_DEC_FRAME_RATE_NR (W4_REG_BASE + 0x01AC)
  56. #define W4_RET_DEC_FRAME_RATE_DR (W4_REG_BASE + 0x01B0)
  57. /* conformance_window: top, bottom
  58. * bottom [15:0] conformance_window_bottom_offset
  59. * top [31:16] conformance_window_top_offset
  60. */
  61. #define W4_RET_DEC_CROP_TOP_BOTTOM (W4_REG_BASE + 0x01B4)
  62. /* conformance_window: left, right
  63. * right [15:0] conformance_window_left_offset
  64. * left [31:16] conformance_window_right_offset
  65. */
  66. #define W4_RET_DEC_CROP_LEFT_RIGHT (W4_REG_BASE + 0x01B8)
  67. #define W4_RET_DEC_PIC_SIZE (W4_REG_BASE + 0x01BC)
  68. #define W4_RET_DEC_FRAMEBUF_NEEDED (W4_REG_BASE + 0x01C0)
  69. #define W4_RET_DEC_NUM_REORDER_DELAY (W4_REG_BASE + 0x0188)
  70. #define W4_RET_DEC_INTER_RES_CHANGE_REALLOCATED_DPB_IDX (W4_REG_BASE + 0x0188)
  71. /* Sequence change result register
  72. * RET_SEQ_CHANGE_FLAG [5] profile_idc changed
  73. * [16] pic_width/height_in_luma_sample changed
  74. * [19] sps_max_dec_pic_buffering, max_num_reorder or max_latency_increase changed
  75. */
  76. #define W4_RET_DEC_SEQ_CHANGE_FLAG (W4_REG_BASE + 0x01C4)
  77. #define W4_RET_DEC_RECOVERY_POINT (W4_REG_BASE + 0x01C8)
  78. #define W4_RET_DEC_VCORE_USED (W4_REG_BASE + 0x01CC)
  79. #define W4_RET_TEMP_SUB_LAYER_INFO (W4_REG_BASE + 0x01D0)
  80. #define W4_RET_FRAME_CYCLE (W4_REG_BASE + 0x01D4)
  81. #define W4_RET_DEC_WARN_INFO (W4_REG_BASE + 0x01D8)
  82. #define W4_RET_DEC_PRESCAN_INDEX (W4_REG_BASE + 0x01DC)
  83. #define W4_RET_DEC_DECODED_INDEX (W4_REG_BASE + 0x01E0)
  84. #define W4_RET_DEC_DISPLAY_INDEX (W4_REG_BASE + 0x01E4)
  85. /* I_SLICE_DECODED [0]
  86. * P_SLICE_DECODED [1]
  87. * B_SLICE_DECODED [2]
  88. * VCL_NAL_UNIT_TYPE [9:4] See Table 7-1 in H.265 specification.
  89. */
  90. #define W4_RET_DEC_PIC_TYPE (W4_REG_BASE + 0x01E8)
  91. #define W4_RET_DEC_PIC_POC (W4_REG_BASE + 0x01EC)
  92. #define W4_RET_DEC_ERR_CTB_NUM (W4_REG_BASE + 0x01F0)
  93. #define W4_RET_DEC_ERR_INFO (W4_REG_BASE + 0x01F4)
  94. #define W4_RET_DEC_AU_START_POS (W4_REG_BASE + 0x01F8)
  95. #define W4_RET_DEC_AU_END_POS (W4_REG_BASE + 0x01FC)
  96. #define W4_ENC_SUB_FRAME_SYNC_IF (W4_REG_BASE + 0x00F0)
  97. #define W4_CMD_ENC_SUB_FRAME_SYNC_CONFIG (W4_REG_BASE + 0x019C)
  98. /************************************************************************/
  99. /* ENCODER - SET_PARAM (in common) */
  100. /************************************************************************/
  101. #define W4_CMD_ENC_SET_PARAM_OPTION (W4_REG_BASE + 0x010C)
  102. #define W4_ROLLBACK_OPTION (W4_REG_BASE + 0x011C)
  103. /* same as the WAVE410 host registers
  104. *#define W4_BS_START_ADDR (W4_REG_BASE + 0x0120)
  105. *#define W4_BS_SIZE (W4_REG_BASE + 0x0124)
  106. *#define W4_BS_PARAM (W4_REG_BASE + 0x0128)
  107. *#define W4_BS_OPTION (W4_REG_BASE + 0x012C)
  108. *#define W4_BS_RD_PTR (W4_REG_BASE + 0x0130)
  109. *#define W4_BS_WR_PTR (W4_REG_BASE + 0x0134)
  110. *#define W4_ADDR_WORK_BASE (W4_REG_BASE + 0x0138)
  111. *#define W4_WORK_SIZE (W4_REG_BASE + 0x013C)
  112. *#define W4_WORK_PARAM (W4_REG_BASE + 0x0140)
  113. *#define W4_ADDR_TEMP_BASE (W4_REG_BASE + 0x0144)
  114. *#define W4_TEMP_SIZE (W4_REG_BASE + 0x0148)
  115. *#define W4_TEMP_PARAM (W4_REG_BASE + 0x014C)
  116. *#define W4_ADDR_SEC_AXI (W4_REG_BASE + 0x0150)
  117. *#define W4_SEC_AXI_SIZE (W4_REG_BASE + 0x0154)
  118. *#define W4_USE_SEC_AXI (W4_REG_BASE + 0x0158)
  119. */
  120. /************************************************************************/
  121. /* ENCODER - SET_PARAM + COMMON */
  122. /************************************************************************/
  123. #define W4_CMD_ENC_SET_PARAM_ENABLE (W4_REG_BASE + 0x015C)
  124. #define W4_CMD_ENC_SEQ_SRC_SIZE (W4_REG_BASE + 0x0160)
  125. #define W4_CMD_ENC_SEQ_PIC_PARAM (W4_REG_BASE + 0x016C)
  126. #define W4_CMD_ENC_SEQ_GOP_PARAM (W4_REG_BASE + 0x0170)
  127. #define W4_CMD_ENC_SEQ_INTRA_PARAM (W4_REG_BASE + 0x0174)
  128. #define W4_CMD_ENC_SEQ_CONF_WIN_TOP_BOT (W4_REG_BASE + 0x0178)
  129. #define W4_CMD_ENC_SEQ_CONF_WIN_LEFT_RIGHT (W4_REG_BASE + 0x017C)
  130. #define W4_CMD_ENC_SEQ_FRAME_RATE (W4_REG_BASE + 0x0180)
  131. #define W4_CMD_ENC_SEQ_INDEPENDENT_SLICE (W4_REG_BASE + 0x0184)
  132. #define W4_CMD_ENC_SEQ_DEPENDENT_SLICE (W4_REG_BASE + 0x0188)
  133. #define W4_CMD_ENC_SEQ_INTRA_REFRESH (W4_REG_BASE + 0x018C)
  134. #define W4_CMD_ENC_PARAM (W4_REG_BASE + 0x0190)
  135. #define W4_CMD_ENC_SEQ_LAYER_PERIOD (W4_REG_BASE + 0x0194)
  136. #define W4_CMD_ENC_RC_INTRA_MIN_MAX_QP (W4_REG_BASE + 0x0194)
  137. #define W4_CMD_ENC_RC_PARAM (W4_REG_BASE + 0x0198)
  138. #define W4_CMD_ENC_RC_MIN_MAX_QP (W4_REG_BASE + 0x019C)
  139. #define W4_CMD_ENC_RC_BIT_RATIO_LAYER_0_3 (W4_REG_BASE + 0x01A0)
  140. #define W4_CMD_ENC_RC_BIT_RATIO_LAYER_4_7 (W4_REG_BASE + 0x01A4)
  141. #define W4_CMD_ENC_NR_PARAM (W4_REG_BASE + 0x01A8)
  142. #define W4_CMD_ENC_NR_WEIGHT (W4_REG_BASE + 0x01AC)
  143. #define W4_CMD_ENC_NUM_UNITS_IN_TICK (W4_REG_BASE + 0x01B0)
  144. #define W4_CMD_ENC_TIME_SCALE (W4_REG_BASE + 0x01B4)
  145. #define W4_CMD_ENC_NUM_TICKS_POC_DIFF_ONE (W4_REG_BASE + 0x01B8)
  146. #define W4_CMD_ENC_RC_TRANS_RATE (W4_REG_BASE + 0x01BC)
  147. #define W4_CMD_ENC_RC_TARGET_RATE (W4_REG_BASE + 0x01C0)
  148. #define W4_CMD_ENC_ROT_PARAM (W4_REG_BASE + 0x01C4)
  149. #define W4_CMD_ENC_ROT_RESERVED (W4_REG_BASE + 0x01C8)
  150. #define W4_RET_ENC_MIN_FB_NUM (W4_REG_BASE + 0x01CC)
  151. #define W4_RET_ENC_NAL_INFO_TO_BE_ENCODED (W4_REG_BASE + 0x01D0)
  152. #define W4_RET_ENC_MIN_SRC_BUF_NUM (W4_REG_BASE + 0x01D8)
  153. /************************************************************************/
  154. /* ENCODER - SET_PARAM + CUSTOM_GOP */
  155. /************************************************************************/
  156. #define W4_CMD_ENC_SET_CUSTOM_GOP_ENABLE (W4_REG_BASE + 0x015C)
  157. #define W4_CMD_ENC_CUSTOM_GOP_PARAM (W4_REG_BASE + 0x0160)
  158. #define W4_CMD_ENC_CUSTOM_GOP_PIC_PARAM_0 (W4_REG_BASE + 0x0164)
  159. #define W4_CMD_ENC_CUSTOM_GOP_PIC_PARAM_1 (W4_REG_BASE + 0x0168)
  160. #define W4_CMD_ENC_CUSTOM_GOP_PIC_PARAM_2 (W4_REG_BASE + 0x016C)
  161. #define W4_CMD_ENC_CUSTOM_GOP_PIC_PARAM_3 (W4_REG_BASE + 0x0170)
  162. #define W4_CMD_ENC_CUSTOM_GOP_PIC_PARAM_4 (W4_REG_BASE + 0x0174)
  163. #define W4_CMD_ENC_CUSTOM_GOP_PIC_PARAM_5 (W4_REG_BASE + 0x0178)
  164. #define W4_CMD_ENC_CUSTOM_GOP_PIC_PARAM_6 (W4_REG_BASE + 0x017C)
  165. #define W4_CMD_ENC_CUSTOM_GOP_PIC_PARAM_7 (W4_REG_BASE + 0x0180)
  166. #define W4_CMD_ENC_CUSTOM_GOP_RESERVED (W4_REG_BASE + 0x0184)
  167. #define W4_CMD_ENC_CUSTOM_GOP_PIC_LAMBDA_0 (W4_REG_BASE + 0x0188)
  168. #define W4_CMD_ENC_CUSTOM_GOP_PIC_LAMBDA_1 (W4_REG_BASE + 0x018C)
  169. #define W4_CMD_ENC_CUSTOM_GOP_PIC_LAMBDA_2 (W4_REG_BASE + 0x0190)
  170. #define W4_CMD_ENC_CUSTOM_GOP_PIC_LAMBDA_3 (W4_REG_BASE + 0x0194)
  171. #define W4_CMD_ENC_CUSTOM_GOP_PIC_LAMBDA_4 (W4_REG_BASE + 0x0198)
  172. #define W4_CMD_ENC_CUSTOM_GOP_PIC_LAMBDA_5 (W4_REG_BASE + 0x019C)
  173. #define W4_CMD_ENC_CUSTOM_GOP_PIC_LAMBDA_6 (W4_REG_BASE + 0x01A0)
  174. #define W4_CMD_ENC_CUSTOM_GOP_PIC_LAMBDA_7 (W4_REG_BASE + 0x01A4)
  175. /************************************************************************/
  176. /* ENCODER - SET_PARAM + CUSTOM_HEADER */
  177. /************************************************************************/
  178. #define W4_CMD_ENC_CUSTOM_VPS_COMMON (W4_REG_BASE + 0x015C)
  179. #define W4_CMD_ENC_CUSTOM_VPS_DEC_PIC_BUFFERING_MINUS1 (W4_REG_BASE + 0x0160)
  180. #define W4_CMD_ENC_CUSTOM_VPS_NUM_REORDERING (W4_REG_BASE + 0x0164)
  181. #define W4_CMD_ENC_CUSTOM_VPS_MAX_LATENCY_PLUS1_0 (W4_REG_BASE + 0x0168)
  182. #define W4_CMD_ENC_CUSTOM_VPS_MAX_LATENCY_PLUS1_1 (W4_REG_BASE + 0x016C)
  183. #define W4_CMD_ENC_CUSTOM_VPS_MAX_LATENCY_PLUS1_2 (W4_REG_BASE + 0x0170)
  184. #define W4_CMD_ENC_CUSTOM_VPS_MAX_LATENCY_PLUS1_3 (W4_REG_BASE + 0x0174)
  185. #define W4_CMD_ENC_CUSTOM_VPS_MAX_LATENCY_PLUS1_4 (W4_REG_BASE + 0x0178)
  186. #define W4_CMD_ENC_CUSTOM_VPS_MAX_LATENCY_PLUS1_5 (W4_REG_BASE + 0x017C)
  187. #define W4_CMD_ENC_CUSTOM_VPS_MAX_LATENCY_PLUS1_6 (W4_REG_BASE + 0x0180)
  188. #define W4_CMD_ENC_CUSTOM_VPS_LAYER_ID_0 (W4_REG_BASE + 0x0184)
  189. #define W4_CMD_ENC_CUSTOM_VPS_LAYER_ID_1 (W4_REG_BASE + 0x0188)
  190. #define W4_CMD_ENC_CUSTOM_SPS_COMMON (W4_REG_BASE + 0x018C)
  191. #define W4_CMD_ENC_CUSTOM_SPS_DEC_PIC_BUFFERING_MINUS1 (W4_REG_BASE + 0x0190)
  192. #define W4_CMD_ENC_CUSTOM_SPS_NUM_REORDERING (W4_REG_BASE + 0x0194)
  193. #define W4_CMD_ENC_CUSTOM_SPS_MAX_LATENCY_PLUS1_0 (W4_REG_BASE + 0x0198)
  194. #define W4_CMD_ENC_CUSTOM_SPS_MAX_LATENCY_PLUS1_1 (W4_REG_BASE + 0x019C)
  195. #define W4_CMD_ENC_CUSTOM_SPS_MAX_LATENCY_PLUS1_2 (W4_REG_BASE + 0x01A0)
  196. #define W4_CMD_ENC_CUSTOM_SPS_MAX_LATENCY_PLUS1_3 (W4_REG_BASE + 0x01A4)
  197. #define W4_CMD_ENC_CUSTOM_SPS_MAX_LATENCY_PLUS1_4 (W4_REG_BASE + 0x01A8)
  198. #define W4_CMD_ENC_CUSTOM_SPS_MAX_LATENCY_PLUS1_5 (W4_REG_BASE + 0x01AC)
  199. #define W4_CMD_ENC_CUSTOM_SPS_MAX_LATENCY_PLUS1_6 (W4_REG_BASE + 0x01B0)
  200. #define W4_CMD_ENC_CUSTOM_PPS_COMMON (W4_REG_BASE + 0x01B4)
  201. /************************************************************************/
  202. /* ENCODER - SET_PARAM + VUI */
  203. /************************************************************************/
  204. #define W4_CMD_ENC_VUI_PARAM_FLAGS (W4_REG_BASE + 0x015C)
  205. #define W4_CMD_ENC_VUI_ASPECT_RATIO_IDC (W4_REG_BASE + 0x0160)
  206. #define W4_CMD_ENC_VUI_SAR_SIZE (W4_REG_BASE + 0x0164)
  207. #define W4_CMD_ENC_VUI_OVERSCAN_APPROPRIATE (W4_REG_BASE + 0x0168)
  208. #define W4_CMD_ENC_VUI_VIDEO_SIGNAL (W4_REG_BASE + 0x016C)
  209. #define W4_CMD_ENC_VUI_CHROMA_SAMPLE_LOC (W4_REG_BASE + 0x0170)
  210. #define W4_CMD_ENC_VUI_DISP_WIN_LEFT_RIGHT (W4_REG_BASE + 0x0174)
  211. #define W4_CMD_ENC_VUI_DISP_WIN_TOP_BOT (W4_REG_BASE + 0x0178)
  212. #define W4_CMD_ENC_VUI_HRD_RBSP_PARAM_FLAG (W4_REG_BASE + 0x017C)
  213. #define W4_CMD_ENC_VUI_RBSP_ADDR (W4_REG_BASE + 0x0180)
  214. #define W4_CMD_ENC_VUI_RBSP_SIZE (W4_REG_BASE + 0x0184)
  215. #define W4_CMD_ENC_HRD_RBSP_ADDR (W4_REG_BASE + 0x0188)
  216. #define W4_CMD_ENC_HRD_RBSP_SIZE (W4_REG_BASE + 0x018C)
  217. /************************************************************************/
  218. /* ENCODER - ENC_PIC */
  219. /************************************************************************/
  220. #define W4_CMD_ENC_ADDR_REPORT_BASE (W4_REG_BASE + 0x015C)
  221. #define W4_CMD_ENC_REPORT_SIZE (W4_REG_BASE + 0x0160)
  222. #define W4_CMD_ENC_REPORT_PARAM (W4_REG_BASE + 0x0164)
  223. #define W4_CMD_ENC_CODE_OPTION (W4_REG_BASE + 0x0168)
  224. #define W4_CMD_ENC_PIC_PARAM (W4_REG_BASE + 0x016C)
  225. #define W4_CMD_ENC_SRC_PIC_IDX (W4_REG_BASE + 0x0170)
  226. #define W4_CMD_ENC_SRC_ADDR_Y (W4_REG_BASE + 0x0174)
  227. #define W4_CMD_ENC_SRC_ADDR_U (W4_REG_BASE + 0x0178)
  228. #define W4_CMD_ENC_SRC_ADDR_V (W4_REG_BASE + 0x017C)
  229. #define W4_CMD_ENC_SRC_STRIDE (W4_REG_BASE + 0x0180)
  230. #define W4_CMD_ENC_SRC_FORMAT (W4_REG_BASE + 0x0184)
  231. #define W4_CMD_ENC_PREFIX_SEI_NAL_ADDR (W4_REG_BASE + 0x0188)
  232. #define W4_CMD_ENC_PREFIX_SEI_INFO (W4_REG_BASE + 0x018C)
  233. #define W4_CMD_ENC_SUFFIX_SEI_NAL_ADDR (W4_REG_BASE + 0x0190)
  234. #define W4_CMD_ENC_SUFFIX_SEI_INFO (W4_REG_BASE + 0x0194)
  235. #define W4_CMD_ENC_LONGTERM_PIC (W4_REG_BASE + 0x0198)
  236. /*(W4_REG_BASE + 0x019C) = used for SUB_FRAME_SYNC */
  237. #define W4_CMD_ENC_CTU_OPT_PARAM (W4_REG_BASE + 0x01A0)
  238. #define W4_CMD_ENC_ROI_ADDR_CTU_MAP (W4_REG_BASE + 0x01A4)
  239. #define W4_CMD_ENC_CTU_QP_MAP_ADDR (W4_REG_BASE + 0x01AC)
  240. #define W4_CMD_ENC_SRC_TIMESTAMP_LOW (W4_REG_BASE + 0x01B0)
  241. #define W4_CMD_ENC_SRC_TIMESTAMP_HIGH (W4_REG_BASE + 0x01B4)
  242. #define W4_CMD_ENC_FC_PARAM (W4_REG_BASE + 0x01E8)
  243. #define W4_CMD_ENC_FC_TABLE_ADDR_Y (W4_REG_BASE + 0x01EC)
  244. #define W4_CMD_ENC_FC_TABLE_ADDR_C (W4_REG_BASE + 0x01F0)
  245. #define W4_RET_ENC_PIC_IDX (W4_REG_BASE + 0x01A8)
  246. #define W4_RET_ENC_PIC_SLICE_NUM (W4_REG_BASE + 0x01AC)
  247. #define W4_RET_ENC_PIC_SKIP (W4_REG_BASE + 0x01B0)
  248. #define W4_RET_ENC_PIC_NUM_INTRA (W4_REG_BASE + 0x01B4)
  249. #define W4_RET_ENC_PIC_NUM_MERGE (W4_REG_BASE + 0x01B8)
  250. #define W4_RET_ENC_PIC_FLAG (W4_REG_BASE + 0x01BC)
  251. #define W4_RET_ENC_PIC_NUM_SKIP (W4_REG_BASE + 0x01C0)
  252. #define W4_RET_ENC_PIC_AVG_CU_QP (W4_REG_BASE + 0x01C4)
  253. #define W4_RET_ENC_PIC_BYTE (W4_REG_BASE + 0x01C8)
  254. #define W4_RET_ENC_GOP_PIC_IDX (W4_REG_BASE + 0x01CC)
  255. #define W4_RET_ENC_PIC_POC (W4_REG_BASE + 0x01D0)
  256. #define W4_RET_ENC_USED_SRC_IDX (W4_REG_BASE + 0x01D8)
  257. #define W4_RET_ENC_PIC_NUM (W4_REG_BASE + 0x01DC)
  258. #define W4_RET_ENC_PIC_TYPE (W4_REG_BASE + 0x01E0)
  259. #define W4_RET_ENC_VCL_NUT (W4_REG_BASE + 0x01E4)
  260. /************************************************************************/
  261. /* ENCODER - SET_FRAMEBUF */
  262. /************************************************************************/
  263. #define W4_CMD_FBC_STRIDE_Y (W4_REG_BASE + 0x150)
  264. #define W4_CMD_FBC_STRIDE_C (W4_REG_BASE + 0x154)
  265. /* 1/4 sub-sampled buffer (for S2 ME)
  266. * SUB_SAMPLED_ONE_FB_SIZE = ALIGN16(width/4) * ALIGN8(height/4)
  267. * total size for sub-sampled buffer = SUB_SAMPLED_ONE_FB_SIZE * SET_FB_NUM
  268. */
  269. #define W4_ADDR_SUB_SAMPLED_FB_BASE (W4_REG_BASE + 0x0158)
  270. #define W4_SUB_SAMPLED_ONE_FB_SIZE (W4_REG_BASE + 0x015C)
  271. /* 0x160 ~ 0x17F : same as the WAVE410 registers for SET_FRAMEBUF */
  272. #endif /* __WAVE410_REGISTER_DEFINE_H__ */