common_regdefine.h 26 KB

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  1. /* SPDX-License-Identifier: LGPL-2.1 OR BSD-3-Clause */
  2. //--=========================================================================--
  3. // This file is a part of VPU Reference API project
  4. //-----------------------------------------------------------------------------
  5. //
  6. // This confidential and proprietary software may be used only
  7. // as authorized by a licensing agreement from Chips&Media Inc.
  8. // In the event of publication, the following notice is applicable:
  9. //
  10. // (C) COPYRIGHT 2006 - 2013 CHIPS&MEDIA INC.
  11. // ALL RIGHTS RESERVED
  12. //
  13. // The entire notice above must be reproduced on all authorized
  14. // copies.
  15. //
  16. //--=========================================================================--
  17. #ifndef __COMMON_REGISTER_DEFINE_H__
  18. #define __COMMON_REGISTER_DEFINE_H__
  19. #define W4_REG_BASE 0x00000000
  20. #define W4_CMD_REG_BASE 0x00000100
  21. #define W4_CMD_REG_END 0x00000200
  22. /*
  23. * Common
  24. */
  25. /* Power On Configuration
  26. * PO_DEBUG_MODE [0] 1 - Power On with debug mode
  27. * USE_PO_CONF [3] 1 - Use Power-On-Configuration
  28. */
  29. #define W4_PO_CONF (W4_REG_BASE + 0x0000)
  30. #define W4_VCPU_CUR_PC (W4_REG_BASE + 0x0004)
  31. #define W4_VPU_PDBG_CTRL (W4_REG_BASE + 0x0010) // vCPU debugger ctrl register
  32. #define W4_VPU_PDBG_IDX_REG (W4_REG_BASE + 0x0014) // vCPU debugger index register
  33. #define W4_VPU_PDBG_WDATA_REG (W4_REG_BASE + 0x0018) // vCPU debugger write data register
  34. #define W4_VPU_PDBG_RDATA_REG (W4_REG_BASE + 0x001C) // vCPU debugger read data register
  35. #define W4_VPU_FIO_CTRL_ADDR (W4_REG_BASE + 0x0020)
  36. #define W4_VPU_FIO_DATA (W4_REG_BASE + 0x0024)
  37. #define W4_VPU_VINT_REASON_USR (W4_REG_BASE + 0x0030)
  38. #define W4_VPU_VINT_REASON_CLR (W4_REG_BASE + 0x0034)
  39. #define W4_VPU_HOST_INT_REQ (W4_REG_BASE + 0x0038)
  40. #define W4_VPU_VINT_CLEAR (W4_REG_BASE + 0x003C)
  41. #define W4_VPU_HINT_CLEAR (W4_REG_BASE + 0x0040)
  42. #define W4_VPU_VPU_INT_STS (W4_REG_BASE + 0x0044)
  43. #define W4_VPU_VINT_ENABLE (W4_REG_BASE + 0x0048)
  44. /* INTERRUPT
  45. */
  46. enum {
  47. W4_INT_INIT_VPU = 0,
  48. W4_INT_DEC_PIC_HDR = 1,
  49. W4_INT_SET_PARAM = 1,
  50. W4_INT_ENC_INIT_SEQ = 1,
  51. W4_INT_FINI_SEQ = 2,
  52. W4_INT_DEC_PIC = 3,
  53. W4_INT_ENC_PIC = 3,
  54. W4_INT_SET_FRAMEBUF = 4,
  55. W4_INT_FLUSH_DEC = 5,
  56. W4_INT_ENC_SLICE_INT = 7,
  57. W4_INT_GET_FW_VERSION = 8,
  58. W4_INT_QUERY_DEC = 9,
  59. W4_INT_SLEEP_VPU = 10,
  60. W4_INT_WAKEUP_VPU = 11,
  61. W4_INT_CHANGE_INT = 12,
  62. W4_INT_CREATE_INSTANCE = 14,
  63. W4_INT_BSBUF_EMPTY = 15, /*!<< Bitstream buffer empty[dec]/full[enc] */
  64. };
  65. typedef enum {
  66. INIT_VPU = 0x0001,
  67. DEC_PIC_HDR = 0x0002, /* INIT_SEQ or SLICE HEADER */
  68. SET_PARAM = 0x0002,
  69. FINI_SEQ = 0x0004,
  70. DEC_PIC = 0x0008,
  71. ENC_PIC = 0x0008,
  72. SET_FRAMEBUF = 0x0010,
  73. FLUSH_DECODER = 0x0020,
  74. GET_FW_VERSION = 0x0100,
  75. QUERY_DECODER = 0x0200,
  76. SLEEP_VPU = 0x0400,
  77. WAKEUP_VPU = 0x0800,
  78. CREATE_INSTANCE = 0x4000,
  79. RESET_VPU = 0x10000,
  80. MAX_VPU_COMD = 0x10000,
  81. } VPU_COMMAND;
  82. #define W4_VPU_VINT_REASON (W4_REG_BASE + 0x004C)
  83. /* RESET_REQ
  84. * CCLK [7:0] - for each vCORE
  85. * BCLK [15:8] - for each vCORE
  86. * ACLK [23:16] - for each vCORE
  87. * ACLK [24] - for vCPU
  88. * VCLK [25] -
  89. * MCLK [26] - Multi-media AXI
  90. */
  91. #define W4_VPU_RESET_REQ (W4_REG_BASE + 0x0050)
  92. #define W4_RST_BLOCK_CCLK(_core) (1<<_core)
  93. #define W4_RST_BLOCK_CCLK_ALL (0xff)
  94. #define W4_RST_BLOCK_BCLK(_core) (0x100<<_core)
  95. #define W4_RST_BLOCK_BCLK_ALL (0xff00)
  96. #define W4_RST_BLOCK_ACLK(_core) (0x10000<<_core)
  97. #define W4_RST_BLOCK_ACLK_ALL (0xff0000)
  98. #define W4_RST_BLOCK_VCPU (0x1000000)
  99. #define W4_RST_BLOCK_VCLK (0x2000000)
  100. #define W4_RST_BLOCK_MCLK (0x4000000)
  101. #define W4_RST_BLOCK_ALL (0xfffffff)
  102. #define W4_VPU_RESET_STATUS (W4_REG_BASE + 0x0054)
  103. enum {
  104. RESET_VCE = 0x01,
  105. RESET_BPU = 0x02,
  106. RESET_MAXI = 0x04,
  107. RESET_VCPU = 0x08,
  108. RESET_PAXI = 0x10,
  109. RESET_ALL = 0x1f,
  110. };
  111. #define W4_VCPU_RESTART (W4_REG_BASE + 0x0058)
  112. #define W4_VPU_CLK_MASK (W4_REG_BASE + 0x005C)
  113. /* REMAP_CTRL
  114. * PAGE SIZE: [8:0] 0x001 - 4K
  115. * 0x002 - 8K
  116. * 0x004 - 16K
  117. * ...
  118. * 0x100 - 1M
  119. * REGION ATTR1 [10] 0 - Normal
  120. * 1 - Make Bus error for the region
  121. * REGION ATTR2 [11] 0 - Normal
  122. * 1 - Bypass region
  123. * REMAP INDEX [15:12] - 0 ~ 3 , 0 - Code, 1-Stack
  124. * ENDIAN [19:16] - See EndianMode in vdi.h
  125. * AXI-ID [23:20] - Upper AXI-ID
  126. * BUS_ERROR [29] 0 - bypass
  127. * 1 - Make BUS_ERROR for unmapped region
  128. * BYPASS_ALL [30] 1 - Bypass all
  129. * ENABLE [31] 1 - Update control register[30:16]
  130. */
  131. enum {
  132. W4_REMAP_CODE_INDEX=0,
  133. };
  134. #define W4_VPU_REMAP_CTRL (W4_REG_BASE + 0x0060)
  135. #define W4_VPU_REMAP_VADDR (W4_REG_BASE + 0x0064)
  136. #define W4_VPU_REMAP_PADDR (W4_REG_BASE + 0x0068)
  137. #define W4_VPU_REMAP_CORE_START (W4_REG_BASE + 0x006C)
  138. #define W4_VPU_BUSY_STATUS (W4_REG_BASE + 0x0070)
  139. #define W4_VPU_HALT_STATUS (W4_REG_BASE + 0x0074)
  140. #define W4_CMD_VCPU_DDR_CH_SELECT (W4_REG_BASE + 0x00F8)
  141. /************************************************************************/
  142. /* Decoder Common */
  143. /************************************************************************/
  144. #define W4_COMMAND (W4_REG_BASE + 0x0100)
  145. #define W4_CORE_INDEX (W4_REG_BASE + 0x0104)
  146. /* INST_INDEX [15:0] : 0 - HEVC
  147. * [31:16] : Instance index
  148. */
  149. #define W4_INST_INDEX (W4_REG_BASE + 0x0108)
  150. /* COMMAND Description
  151. * ------------------------------------------------------------------
  152. * DEC_PIC 0x100 Reset
  153. */
  154. #define DEC_PIC_SEQ_INIT (0x1)
  155. #define DEC_PIC_OPT_DISCARD_PICTURE (0x100)
  156. #define DEC_PIC_OPT_EMPTY_INTR_INTERVAL (0x10000)
  157. #define W4_COMMAND_OPTION (W4_REG_BASE + 0x010C)
  158. #define W4_RET_SUCCESS (W4_REG_BASE + 0x0110)
  159. /*
  160. * See WAVE4_ERRORS
  161. */
  162. #define W4_RET_FAIL_REASON (W4_REG_BASE + 0x0114)
  163. #define W4_FRAME_CYCLE (W4_REG_BASE + 0x01d4)
  164. /************************************************************************/
  165. /* DECODER - INIT_VPU */
  166. /************************************************************************/
  167. /* Note: W4_INIT_CODE_BASE_ADDR should be aligned to 4KB */
  168. #define W4_ADDR_CODE_BASE (W4_REG_BASE + 0x0118)
  169. #define W4_CODE_SIZE (W4_REG_BASE + 0x011C)
  170. #define W4_CODE_PARAM (W4_REG_BASE + 0x0120)
  171. #define W4_HW_OPTION (W4_REG_BASE + 0x0124)
  172. /* Note: W4_INIT_STACK_BASE_ADDR should be aligned to 4KB */
  173. #define W4_ADDR_STACK_BASE (W4_REG_BASE + 0x012C)
  174. #define W4_STACK_SIZE (W4_REG_BASE + 0x0130)
  175. #define W4_TIMEOUT_CNT (W4_REG_BASE + 0x0134)
  176. /************************************************************************/
  177. /* DECODER - SET_FRAMEBUF */
  178. /************************************************************************/
  179. /* SFB_OPTION [25:20] fbc mode
  180. * [19:16] endian
  181. * [4] Done
  182. * [3:0] 0: SET_FRAMEBUFFER(upto 8 framebuffers at once)
  183. */
  184. #define W4_SFB_OPTION (W4_REG_BASE + 0x010C)
  185. /* COMMON_PIC_INFO [29] NV21_ENABLE for linear framebuffer
  186. * [28] BWB_ENABLE_FLAG
  187. * [27:24] AXI_ID
  188. * [23] Reserved
  189. * [22] 0: Right justified, 1: Left justified
  190. * [21:20] MapType 0: 8bit, 1: 16bit, 2: 3 pixels in 32bit
  191. * [19:17] Color format
  192. * [16] Cb/Cr interleaved
  193. * [15:0] stride
  194. */
  195. #define W4_COMMON_PIC_INFO (W4_REG_BASE + 0x0120)
  196. /* PIC_SIZE [31:16] picture width
  197. * [15:0] picture height
  198. */
  199. #define W4_PIC_SIZE (W4_REG_BASE + 0x0124)
  200. /* SET_FB_NUM [12:8] FB_NUM_START
  201. * [4:0] FB_NUM_END
  202. * [31:0] TARGET_FB_FLAG
  203. */
  204. #define W4_SET_FB_NUM (W4_REG_BASE + 0x0128) // ADD/REMOVE NUM
  205. #define C7_SET_FRAME_SLICE_BB_START (W4_REG_BASE + 0x0150)
  206. #define C7_SET_FRAME_SLICE_BB_SIZE (W4_REG_BASE + 0x0154)
  207. #define W4_ADDR_LUMA_BASE0 (W4_REG_BASE + 0x0160)
  208. #define W4_ADDR_CB_BASE0 (W4_REG_BASE + 0x0164)
  209. #define W4_ADDR_CR_BASE0 (W4_REG_BASE + 0x0168)
  210. #define W4_ADDR_FBC_Y_OFFSET0 (W4_REG_BASE + 0x0168) // Compression offset table for Luma
  211. #define W4_ADDR_FBC_C_OFFSET0 (W4_REG_BASE + 0x016C) // Compression offset table for Chroma
  212. #define W4_ADDR_LUMA_BASE1 (W4_REG_BASE + 0x0170)
  213. #define W4_ADDR_CB_ADDR1 (W4_REG_BASE + 0x0174)
  214. #define W4_ADDR_CR_ADDR1 (W4_REG_BASE + 0x0178)
  215. #define W4_ADDR_FBC_Y_OFFSET1 (W4_REG_BASE + 0x0178) // Compression offset table for Luma
  216. #define W4_ADDR_FBC_C_OFFSET1 (W4_REG_BASE + 0x017C) // Compression offset table for Chroma
  217. #define W4_ADDR_LUMA_BASE2 (W4_REG_BASE + 0x0180)
  218. #define W4_ADDR_CB_ADDR2 (W4_REG_BASE + 0x0184)
  219. #define W4_ADDR_CR_ADDR2 (W4_REG_BASE + 0x0188)
  220. #define W4_ADDR_FBC_Y_OFFSET2 (W4_REG_BASE + 0x0188) // Compression offset table for Luma
  221. #define W4_ADDR_FBC_C_OFFSET2 (W4_REG_BASE + 0x018C) // Compression offset table for Chroma
  222. #define W4_ADDR_LUMA_BASE3 (W4_REG_BASE + 0x0190)
  223. #define W4_ADDR_CB_ADDR3 (W4_REG_BASE + 0x0194)
  224. #define W4_ADDR_CR_ADDR3 (W4_REG_BASE + 0x0198)
  225. #define W4_ADDR_FBC_Y_OFFSET3 (W4_REG_BASE + 0x0198) // Compression offset table for Luma
  226. #define W4_ADDR_FBC_C_OFFSET3 (W4_REG_BASE + 0x019C) // Compression offset table for Chroma
  227. #define W4_ADDR_LUMA_BASE4 (W4_REG_BASE + 0x01A0)
  228. #define W4_ADDR_CB_ADDR4 (W4_REG_BASE + 0x01A4)
  229. #define W4_ADDR_CR_ADDR4 (W4_REG_BASE + 0x01A8)
  230. #define W4_ADDR_FBC_Y_OFFSET4 (W4_REG_BASE + 0x01A8) // Compression offset table for Luma
  231. #define W4_ADDR_FBC_C_OFFSET4 (W4_REG_BASE + 0x01AC) // Compression offset table for Chroma
  232. #define W4_ADDR_LUMA_BASE5 (W4_REG_BASE + 0x01B0)
  233. #define W4_ADDR_CB_ADDR5 (W4_REG_BASE + 0x01B4)
  234. #define W4_ADDR_CR_ADDR5 (W4_REG_BASE + 0x01B8)
  235. #define W4_ADDR_FBC_Y_OFFSET5 (W4_REG_BASE + 0x01B8) // Compression offset table for Luma
  236. #define W4_ADDR_FBC_C_OFFSET5 (W4_REG_BASE + 0x01BC) // Compression offset table for Chroma
  237. #define W4_ADDR_LUMA_BASE6 (W4_REG_BASE + 0x01C0)
  238. #define W4_ADDR_CB_ADDR6 (W4_REG_BASE + 0x01C4)
  239. #define W4_ADDR_CR_ADDR6 (W4_REG_BASE + 0x01C8)
  240. #define W4_ADDR_FBC_Y_OFFSET6 (W4_REG_BASE + 0x01C8) // Compression offset table for Luma
  241. #define W4_ADDR_FBC_C_OFFSET6 (W4_REG_BASE + 0x01CC) // Compression offset table for Chroma
  242. #define W4_ADDR_LUMA_BASE7 (W4_REG_BASE + 0x01D0)
  243. #define W4_ADDR_CB_ADDR7 (W4_REG_BASE + 0x01D4)
  244. #define W4_ADDR_CR_ADDR7 (W4_REG_BASE + 0x01D8)
  245. #define W4_ADDR_FBC_Y_OFFSET7 (W4_REG_BASE + 0x01D8) // Compression offset table for Luma
  246. #define W4_ADDR_FBC_C_OFFSET7 (W4_REG_BASE + 0x01DC) // Compression offset table for Chroma
  247. #define W4_ADDR_MV_COL0 (W4_REG_BASE + 0x01E0)
  248. #define W4_ADDR_MV_COL1 (W4_REG_BASE + 0x01E4)
  249. #define W4_ADDR_MV_COL2 (W4_REG_BASE + 0x01E8)
  250. #define W4_ADDR_MV_COL3 (W4_REG_BASE + 0x01EC)
  251. #define W4_ADDR_MV_COL4 (W4_REG_BASE + 0x01F0)
  252. #define W4_ADDR_MV_COL5 (W4_REG_BASE + 0x01F4)
  253. #define W4_ADDR_MV_COL6 (W4_REG_BASE + 0x01F8)
  254. #define W4_ADDR_MV_COL7 (W4_REG_BASE + 0x01FC)
  255. /************************************************************************/
  256. /* DECODER - FLUSH_DECODER */
  257. /************************************************************************/
  258. /* W4_FLUSH_DECODER_OPTION[0] 0 - flush DPB
  259. */
  260. #define FLUSH_DPB 0
  261. #define FLUSH_CPB 1
  262. #define W4_FLUSH_DECODER_OPTION (W4_REG_BASE + 0x010C)
  263. #define W4_RET_DEC_DISPLAY_INDEX_0 (W4_REG_BASE + 0x0198)
  264. #define W4_RET_DEC_DISPLAY_INDEX_1 (W4_REG_BASE + 0x019C)
  265. #define W4_RET_DEC_DISPLAY_INDEX_2 (W4_REG_BASE + 0x01A0)
  266. #define W4_RET_DEC_DISPLAY_INDEX_3 (W4_REG_BASE + 0x01A4)
  267. #define W4_RET_DEC_DISPLAY_INDEX_4 (W4_REG_BASE + 0x01A8)
  268. #define W4_RET_DEC_DISPLAY_INDEX_5 (W4_REG_BASE + 0x01AC)
  269. #define W4_RET_DEC_DISPLAY_INDEX_6 (W4_REG_BASE + 0x01B0)
  270. #define W4_RET_DEC_DISPLAY_INDEX_7 (W4_REG_BASE + 0x01B4)
  271. #define W4_RET_DEC_DISPLAY_INDEX_8 (W4_REG_BASE + 0x01B8)
  272. #define W4_RET_DEC_DISPLAY_INDEX_9 (W4_REG_BASE + 0x01BC)
  273. #define W4_RET_DEC_DISPLAY_INDEX_10 (W4_REG_BASE + 0x01C0)
  274. #define W4_RET_DEC_DISPLAY_INDEX_11 (W4_REG_BASE + 0x01C4)
  275. #define W4_RET_DEC_DISPLAY_INDEX_12 (W4_REG_BASE + 0x01C8)
  276. #define W4_RET_DEC_DISPLAY_INDEX_13 (W4_REG_BASE + 0x01CC)
  277. #define W4_RET_DEC_DISPLAY_INDEX_14 (W4_REG_BASE + 0x01D0)
  278. #define W4_RET_DEC_DISPLAY_INDEX_15 (W4_REG_BASE + 0x01D4)
  279. #define W4_RET_DEC_DISPLAY_SIZE (W4_REG_BASE + 0x01D8)
  280. /************************************************************************/
  281. /* DECODER - DEC_PIC_HDR/DEC_PIC */
  282. /************************************************************************/
  283. #define W4_BS_START_ADDR (W4_REG_BASE + 0x0120)
  284. #define W4_BS_SIZE (W4_REG_BASE + 0x0124)
  285. /* BS_PARAM [9] Ring-buffer enable
  286. * [3:0] endianess
  287. */
  288. #define BSPARAM_ENABLE_RINGBUFFER (1<<9)
  289. #define BSPARAM_ENABLE_NALPUMPING (1<<8)
  290. #define BSPARAM_EMODE_SEND_IMM (0<<4)
  291. #define BSPARAM_EMODE_CONCEAL (2<<4)
  292. #define W4_BS_PARAM (W4_REG_BASE + 0x0128)
  293. /* BS_OPTION [0] : 1 - explict_end
  294. * [1] : 1 - stream end flag
  295. */
  296. #define W4_BS_OPTION (W4_REG_BASE + 0x012C)
  297. /* Bit Index */
  298. #define W4_BS_RD_PTR (W4_REG_BASE + 0x0130)
  299. #define W4_BS_WR_PTR (W4_REG_BASE + 0x0134)
  300. #define W4_ADDR_WORK_BASE (W4_REG_BASE + 0x0138)
  301. #define W4_WORK_SIZE (W4_REG_BASE + 0x013C)
  302. /* WORK_PARAM [3:0] Endianess
  303. */
  304. #define W4_WORK_PARAM (W4_REG_BASE + 0x0140)
  305. #define W4_ADDR_TEMP_BASE (W4_REG_BASE + 0x0144)
  306. #define W4_TEMP_SIZE (W4_REG_BASE + 0x0148)
  307. /* TEMP_PARAM [3:0] Endianess
  308. */
  309. #define W4_TEMP_PARAM (W4_REG_BASE + 0x014C)
  310. #define W4_ADDR_SEC_AXI (W4_REG_BASE + 0x0150)
  311. #define W4_SEC_AXI_SIZE (W4_REG_BASE + 0x0154)
  312. #define W4_USE_SEC_AXI (W4_REG_BASE + 0x0158)
  313. /************************************************************************/
  314. /* DECODER - DEC_PIC_HDR/DEC_PIC */
  315. /************************************************************************/
  316. #define W4_CMD_DEC_ADDR_REPORT_BASE (W4_REG_BASE + 0x015C)
  317. #define W4_CMD_DEC_REPORT_SIZE (W4_REG_BASE + 0x0160)
  318. /* USER_PARAM [3:0] Endianess
  319. */
  320. #define W4_CMD_DEC_REPORT_PARAM (W4_REG_BASE + 0x0164)
  321. #define W4_CMD_DEC_ADDR_USER_BASE (W4_REG_BASE + 0x0168)
  322. #define W4_CMD_DEC_USER_SIZE (W4_REG_BASE + 0x016C)
  323. #define W4_CMD_DEC_USER_PARAM (W4_REG_BASE + 0x0170)
  324. #define W4_RET_DEC_DISP_FLAG (W4_REG_BASE + 0x0190)
  325. #define W4_CMD_DEC_DISP_FLAG (W4_REG_BASE + 0x0190)
  326. /************************************************************************/
  327. /* DECODER - GET_FW_VERSION */
  328. /************************************************************************/
  329. #define W4_RET_FW_VERSION (W4_REG_BASE + 0x0118)
  330. #define W4_RET_PRODUCT_NAME (W4_REG_BASE + 0x011C)
  331. #define W4_RET_PRODUCT_VERSION (W4_REG_BASE + 0x0120)
  332. #define W4_RET_STD_DEF0 (W4_REG_BASE + 0x0124)
  333. #define W4_RET_STD_DEF1 (W4_REG_BASE + 0x0128)
  334. #define W4_RET_CONF_FEATURE (W4_REG_BASE + 0x012C)
  335. #define W4_RET_CONFIG_DATE (W4_REG_BASE + 0x0130)
  336. #define W4_RET_CONFIG_REVISION (W4_REG_BASE + 0x0134)
  337. #define W4_RET_CONFIG_TYPE (W4_REG_BASE + 0x0138)
  338. #define W4_RET_CONF_VCORE0 (W4_REG_BASE + 0x0150)
  339. /************************************************************************/
  340. /* SLEEP_VPU */
  341. /************************************************************************/
  342. #define W4_RET_CUR_SP (W4_REG_BASE + 0x0124)
  343. /************************************************************************/
  344. /* WAKEUP_VPU */
  345. /************************************************************************/
  346. #define W4_SET_CUR_SP (W4_REG_BASE + 0x0120)
  347. /************************************************************************/
  348. /* PRODUCT INFORMATION */
  349. /************************************************************************/
  350. #define W4_PRODUCT_NAME (W4_REG_BASE + 0x1040)
  351. #define W4_PRODUCT_NUMBER (W4_REG_BASE + 0x1044)
  352. /************************************************************************/
  353. /* GDI register for Debugging */
  354. /************************************************************************/
  355. #define W4_GDI_BASE 0x8800
  356. #define W4_GDI_CORE1_BASE 0x9800
  357. #define W4_GDI_PRI_RD_PRIO_L (W4_GDI_BASE + 0x000)
  358. #define W4_GDI_PRI_RD_PRIO_H (W4_GDI_BASE + 0x004)
  359. #define W4_GDI_PRI_WR_PRIO_L (W4_GDI_BASE + 0x008)
  360. #define W4_GDI_PRI_WR_PRIO_H (W4_GDI_BASE + 0x00c)
  361. #define W4_GDI_PRI_RD_LOCK_CNT (W4_GDI_BASE + 0x010)
  362. #define W4_GDI_PRI_WR_LOCK_CNT (W4_GDI_BASE + 0x014)
  363. #define W4_GDI_SEC_RD_PRIO_L (W4_GDI_BASE + 0x018)
  364. #define W4_GDI_SEC_RD_PRIO_H (W4_GDI_BASE + 0x01c)
  365. #define W4_GDI_SEC_WR_PRIO_L (W4_GDI_BASE + 0x020)
  366. #define W4_GDI_SEC_WR_PRIO_H (W4_GDI_BASE + 0x024)
  367. #define W4_GDI_SEC_RD_LOCK_CNT (W4_GDI_BASE + 0x028)
  368. #define W4_GDI_SEC_WR_LOCK_CNT (W4_GDI_BASE + 0x02c)
  369. #define W4_GDI_SEC_CLIENT_EN (W4_GDI_BASE + 0x030)
  370. #define W4_GDI_CONTROL (W4_GDI_BASE + 0x034)
  371. #define W4_GDI_PIC_INIT_HOST (W4_GDI_BASE + 0x038)
  372. #define W4_GDI_HW_VERINFO (W4_GDI_BASE + 0x050)
  373. #define W4_GDI_PINFO_REQ (W4_GDI_BASE + 0x060)
  374. #define W4_GDI_PINFO_ACK (W4_GDI_BASE + 0x064)
  375. #define W4_GDI_PINFO_ADDR (W4_GDI_BASE + 0x068)
  376. #define W4_GDI_PINFO_DATA (W4_GDI_BASE + 0x06c)
  377. #define W4_GDI_BWB_ENABLE (W4_GDI_BASE + 0x070)
  378. #define W4_GDI_BWB_SIZE (W4_GDI_BASE + 0x074)
  379. #define W4_GDI_BWB_STD_STRUCT (W4_GDI_BASE + 0x078)
  380. #define W4_GDI_BWB_STATUS (W4_GDI_BASE + 0x07c)
  381. #define W4_GDI_STATUS (W4_GDI_BASE + 0x080)
  382. #define W4_GDI_DEBUG_0 (W4_GDI_BASE + 0x084)
  383. #define W4_GDI_DEBUG_1 (W4_GDI_BASE + 0x088)
  384. #define W4_GDI_DEBUG_2 (W4_GDI_BASE + 0x08c)
  385. #define W4_GDI_DEBUG_3 (W4_GDI_BASE + 0x090)
  386. #define W4_GDI_DEBUG_PROBE_ADDR (W4_GDI_BASE + 0x094)
  387. #define W4_GDI_DEBUG_PROBE_DATA (W4_GDI_BASE + 0x098)
  388. // write protect
  389. #define W4_GDI_WPROT_ERR_CLR (W4_GDI_BASE + 0x0A0)
  390. #define W4_GDI_WPROT_ERR_RSN (W4_GDI_BASE + 0x0A4)
  391. #define W4_GDI_WPROT_ERR_ADR (W4_GDI_BASE + 0x0A8)
  392. #define W4_GDI_WPROT_RGN_EN (W4_GDI_BASE + 0x0AC)
  393. #define W4_GDI_WPROT_RGN0_STA (W4_GDI_BASE + 0x0B0)
  394. #define W4_GDI_WPROT_RGN0_END (W4_GDI_BASE + 0x0B4)
  395. #define W4_GDI_WPROT_RGN1_STA (W4_GDI_BASE + 0x0B8)
  396. #define W4_GDI_WPROT_RGN1_END (W4_GDI_BASE + 0x0BC)
  397. #define W4_GDI_WPROT_RGN2_STA (W4_GDI_BASE + 0x0C0)
  398. #define W4_GDI_WPROT_RGN2_END (W4_GDI_BASE + 0x0C4)
  399. #define W4_GDI_WPROT_RGN3_STA (W4_GDI_BASE + 0x0C8)
  400. #define W4_GDI_WPROT_RGN3_END (W4_GDI_BASE + 0x0CC)
  401. #define W4_GDI_WPROT_RGN4_STA (W4_GDI_BASE + 0x0D0)
  402. #define W4_GDI_WPROT_RGN4_END (W4_GDI_BASE + 0x0D4)
  403. #define W4_GDI_WPROT_RGN5_STA (W4_GDI_BASE + 0x0D8)
  404. #define W4_GDI_WPROT_RGN5_END (W4_GDI_BASE + 0x0DC)
  405. #define W4_GDI_VCORE0_BUS_CTRL (W4_GDI_BASE + 0x0F0)
  406. #define W4_GDI_VCORE0_BUS_STATUS (W4_GDI_BASE + 0x0F4)
  407. #define W4_GDI_VCORE1_BUS_CTRL (W4_GDI_CORE1_BASE + 0x0F0)
  408. #define W4_GDI_VCORE1_BUS_STATUS (W4_GDI_CORE1_BASE + 0x0F4)
  409. #define W4_RET_GDI_WPROT_ERR_RSN (W4_REG_BASE + 0x0118)
  410. #define W4_RET_GDI_WPROT_ERR_ADR (W4_REG_BASE + 0x011C)
  411. #define W4_RET_GDI_SIZE_ERR_FLAG (W4_REG_BASE + 0x0120)
  412. #define W4_GDI_SIZE_ERR_FLAG (W4_GDI_BASE + 0x0e0)
  413. #define W4_GDI_ADR_RQ_SIZE_ERR_PRI0 (W4_GDI_BASE + 0x100)
  414. #define W4_GDI_ADR_RQ_SIZE_ERR_PRI1 (W4_GDI_BASE + 0x104)
  415. #define W4_GDI_ADR_RQ_SIZE_ERR_PRI2 (W4_GDI_BASE + 0x108)
  416. #define W4_GDI_ADR_WQ_SIZE_ERR_PRI0 (W4_GDI_BASE + 0x10c)
  417. #define W4_GDI_ADR_WQ_SIZE_ERR_PRI1 (W4_GDI_BASE + 0x110)
  418. #define W4_GDI_ADR_WQ_SIZE_ERR_PRI2 (W4_GDI_BASE + 0x114)
  419. #define W4_GDI_ADR_RQ_SIZE_ERR_SEC0 (W4_GDI_BASE + 0x118)
  420. #define W4_GDI_ADR_RQ_SIZE_ERR_SEC1 (W4_GDI_BASE + 0x11c)
  421. #define W4_GDI_ADR_RQ_SIZE_ERR_SEC2 (W4_GDI_BASE + 0x120)
  422. #define W4_GDI_ADR_WQ_SIZE_ERR_SEC0 (W4_GDI_BASE + 0x124)
  423. #define W4_GDI_ADR_WQ_SIZE_ERR_SEC1 (W4_GDI_BASE + 0x128)
  424. #define W4_GDI_ADR_WQ_SIZE_ERR_SEC2 (W4_GDI_BASE + 0x12c)
  425. #define W4_GDI_ADR_RQ_SIZE_ERR_PRI0_2D (W4_GDI_BASE + 0x130)
  426. #define W4_GDI_ADR_RQ_SIZE_ERR_PRI1_2D (W4_GDI_BASE + 0x134)
  427. #define W4_GDI_ADR_RQ_SIZE_ERR_PRI2_2D (W4_GDI_BASE + 0x138)
  428. #define W4_GDI_ADR_WQ_SIZE_ERR_PRI0_2D (W4_GDI_BASE + 0x13c)
  429. #define W4_GDI_ADR_WQ_SIZE_ERR_PRI1_2D (W4_GDI_BASE + 0x140)
  430. #define W4_GDI_ADR_WQ_SIZE_ERR_PRI2_2D (W4_GDI_BASE + 0x144)
  431. #define W4_GDI_INFO_CONTROL (W4_GDI_BASE + 0x400)
  432. #define W4_GDI_INFO_PIC_SIZE (W4_GDI_BASE + 0x404)
  433. // W4_GDI 2.0 register
  434. #define W4_GDI_INFO_BASE_Y_TOP (W4_GDI_BASE + 0x408)
  435. #define W4_GDI_INFO_BASE_CB_TOP (W4_GDI_BASE + 0x40C)
  436. #define W4_GDI_INFO_BASE_CR_TOP (W4_GDI_BASE + 0x410)
  437. #define W4_GDI_INFO_BASE_Y_BOT (W4_GDI_BASE + 0x414)
  438. #define W4_GDI_INFO_BASE_CB_BOT (W4_GDI_BASE + 0x418)
  439. #define W4_GDI_INFO_BASE_CR_BOT (W4_GDI_BASE + 0x41C)
  440. #define W4_GDI_XY2AXI_LUM_BIT00 (W4_GDI_BASE + 0x800)
  441. #define W4_GDI_XY2AXI_LUM_BIT1F (W4_GDI_BASE + 0x87C)
  442. #define W4_GDI_XY2AXI_CHR_BIT00 (W4_GDI_BASE + 0x880)
  443. #define W4_GDI_XY2AXI_CHR_BIT1F (W4_GDI_BASE + 0x8FC)
  444. #define W4_GDI_XY2AXI_CONFIG (W4_GDI_BASE + 0x900)
  445. //W4_GDI 1.0 register
  446. #define W4_GDI_INFO_BASE_Y (W4_GDI_BASE + 0x408)
  447. #define W4_GDI_INFO_BASE_CB (W4_GDI_BASE + 0x40C)
  448. #define W4_GDI_INFO_BASE_CR (W4_GDI_BASE + 0x410)
  449. #define W4_GDI_XY2_CAS_0 (W4_GDI_BASE + 0x800)
  450. #define W4_GDI_XY2_CAS_F (W4_GDI_BASE + 0x83C)
  451. #define W4_GDI_XY2_BA_0 (W4_GDI_BASE + 0x840)
  452. #define W4_GDI_XY2_BA_1 (W4_GDI_BASE + 0x844)
  453. #define W4_GDI_XY2_BA_2 (W4_GDI_BASE + 0x848)
  454. #define W4_GDI_XY2_BA_3 (W4_GDI_BASE + 0x84C)
  455. #define W4_GDI_XY2_RAS_0 (W4_GDI_BASE + 0x850)
  456. #define W4_GDI_XY2_RAS_F (W4_GDI_BASE + 0x88C)
  457. #define W4_GDI_XY2_RBC_CONFIG (W4_GDI_BASE + 0x890)
  458. #define W4_GDI_RBC2_AXI_0 (W4_GDI_BASE + 0x8A0)
  459. #define W4_GDI_RBC2_AXI_1F (W4_GDI_BASE + 0x91C)
  460. #define W4_GDI_TILEDBUF_BASE (W4_GDI_BASE + 0x920)
  461. #define W4_FBC_STRIDE (W4_REG_BASE + 0x0154)
  462. #endif /* __COMMON_REGISTER_DEFINE_H__ */