common.c 46 KB

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  1. // SPDX-License-Identifier: LGPL-2.1 OR BSD-3-Clause
  2. #include "product.h"
  3. #include "wave/common/common.h"
  4. #include "wave/common/common_vpuconfig.h"
  5. #include "vpuerror.h"
  6. #include "wave/common/common_regdefine.h"
  7. #define COMMAND_TIMEOUT 0xffff
  8. void Wave4BitIssueCommand(CodecInst* instance, Uint32 cmd)
  9. {
  10. Uint32 instanceIndex = 0;
  11. Uint32 codecMode = 0;
  12. Uint32 coreIdx;
  13. if (instance != NULL) {
  14. instanceIndex = instance->instIndex;
  15. codecMode = instance->codecMode;
  16. }
  17. coreIdx = instance->coreIdx;
  18. VpuWriteReg(coreIdx, W4_VPU_BUSY_STATUS, 1);
  19. VpuWriteReg(coreIdx, W4_RET_SUCCESS, 0); //for debug
  20. VpuWriteReg(coreIdx, W4_CORE_INDEX, 0);
  21. if (instance->productId == PRODUCT_ID_7Q) // only coda7q use codecModeAux for DIV
  22. VpuWriteReg(coreIdx, W4_INST_INDEX, (instanceIndex&0xffff)|(codecMode<<16) | (instance->codecModeAux<<24));
  23. else
  24. VpuWriteReg(coreIdx, W4_INST_INDEX, (instanceIndex&0xffff)|(codecMode<<16));
  25. VpuWriteReg(coreIdx, W4_COMMAND, cmd);
  26. if ((instance != NULL && instance->loggingEnable))
  27. vdi_log(coreIdx, cmd, 1);
  28. if (cmd != INIT_VPU) {
  29. VpuWriteReg(coreIdx, W4_VPU_HOST_INT_REQ, 1);
  30. }
  31. return;
  32. }
  33. static RetCode SetupWave4Properties(
  34. Uint32 coreIdx
  35. )
  36. {
  37. VpuAttr* pAttr = &g_VpuCoreAttributes[coreIdx];
  38. Uint32 regVal;
  39. Uint8* str;
  40. CodecInst hdr;
  41. /* GET FIRMWARE&HARDWARE INFORMATION */
  42. hdr.coreIdx = 0;
  43. hdr.instIndex = 0;
  44. hdr.loggingEnable = 0;
  45. Wave4BitIssueCommand((CodecInst*)&hdr, GET_FW_VERSION);
  46. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_BUSY_STATUS) == -1) {
  47. return RETCODE_VPU_RESPONSE_TIMEOUT;
  48. }
  49. regVal = VpuReadReg(coreIdx, W4_RET_SUCCESS);
  50. if (regVal == 0) {
  51. return RETCODE_FAILURE;
  52. }
  53. regVal = VpuReadReg(coreIdx, W4_RET_PRODUCT_NAME);
  54. str = (Uint8*)&regVal;
  55. pAttr->productName[0] = str[3];
  56. pAttr->productName[1] = str[2];
  57. pAttr->productName[2] = str[1];
  58. pAttr->productName[3] = str[0];
  59. pAttr->productName[4] = 0;
  60. pAttr->productNumber = VpuReadReg(coreIdx, W4_RET_PRODUCT_VERSION);
  61. switch (pAttr->productNumber) {
  62. case WAVE410_CODE: pAttr->productId = PRODUCT_ID_410; break;
  63. case WAVE4102_CODE: pAttr->productId = PRODUCT_ID_4102; break;
  64. case WAVE420_CODE: pAttr->productId = PRODUCT_ID_420; break;
  65. case WAVE412_CODE: pAttr->productId = PRODUCT_ID_412; break;
  66. case CODA7Q_CODE: pAttr->productId = PRODUCT_ID_7Q; break;
  67. case WAVE420L_CODE: pAttr->productId = PRODUCT_ID_420L; break;
  68. case WAVE510_CODE: pAttr->productId = PRODUCT_ID_510; break;
  69. case WAVE512_CODE: pAttr->productId = PRODUCT_ID_412; break;
  70. case WAVE515_CODE: pAttr->productId = PRODUCT_ID_515; break;
  71. default: pAttr->productId = PRODUCT_ID_NONE; break;
  72. }
  73. pAttr->hwConfigDef0 = VpuReadReg(coreIdx, W4_RET_STD_DEF0);
  74. pAttr->hwConfigDef1 = VpuReadReg(coreIdx, W4_RET_STD_DEF1);
  75. pAttr->hwConfigFeature = VpuReadReg(coreIdx, W4_RET_CONF_FEATURE);
  76. pAttr->hwConfigDate = VpuReadReg(coreIdx, W4_RET_CONFIG_DATE);
  77. pAttr->hwConfigRev = VpuReadReg(coreIdx, W4_RET_CONFIG_REVISION);
  78. pAttr->hwConfigType = VpuReadReg(coreIdx, W4_RET_CONFIG_TYPE);
  79. pAttr->supportGDIHW = TRUE;
  80. if (pAttr->productId == PRODUCT_ID_420L) {
  81. pAttr->supportDecoders = (1<<STD_HEVC);
  82. pAttr->supportEncoders = (1<<STD_HEVC);
  83. pAttr->supportGDIHW = FALSE;
  84. }
  85. else if (pAttr->productId == PRODUCT_ID_420) {
  86. pAttr->supportDecoders = (1<<STD_HEVC);
  87. pAttr->supportEncoders = (1<<STD_HEVC);
  88. }
  89. else if (pAttr->productId == PRODUCT_ID_412) {
  90. pAttr->supportDecoders = (1<<STD_HEVC);
  91. pAttr->supportDecoders |= (1<<STD_VP9);;
  92. pAttr->supportEncoders = (1<<STD_VP9);
  93. }
  94. else if (pAttr->productId == PRODUCT_ID_515) {
  95. pAttr->supportDecoders = (1<<STD_HEVC);
  96. pAttr->supportDecoders |= (1<<STD_VP9);
  97. pAttr->supportDecoders |= (1<<STD_AVS2);
  98. pAttr->supportEncoders = (1<<STD_VP9);
  99. }
  100. else if (pAttr->productId == PRODUCT_ID_7Q) {
  101. pAttr->supportDecoders = (1<<STD_AVC) |
  102. (1<<STD_VC1) |
  103. (1<<STD_MPEG2) |
  104. (1<<STD_MPEG4) |
  105. (1<<STD_H263) |
  106. (1<<STD_AVS) |
  107. (1<<STD_DIV3) |
  108. (1<<STD_RV) |
  109. (1<<STD_THO) |
  110. (1<<STD_VP8) |
  111. (1<<STD_HEVC);
  112. pAttr->supportEncoders = (1<<STD_AVC) | (1<<STD_MPEG4) | (1<<STD_H263);
  113. }
  114. else {
  115. // Wave410
  116. pAttr->supportDecoders = (1<<STD_HEVC);
  117. pAttr->supportEncoders = 0;
  118. }
  119. pAttr->supportFBCBWOptimization = (BOOL)((pAttr->hwConfigDef1>>15)&0x01);
  120. pAttr->supportWTL = TRUE;
  121. pAttr->supportTiled2Linear = FALSE;
  122. pAttr->supportMapTypes = FALSE;
  123. pAttr->support128bitBus = TRUE;
  124. pAttr->supportThumbnailMode = TRUE;
  125. pAttr->supportEndianMask = (Uint32)((1<<VDI_LITTLE_ENDIAN) | (1<<VDI_BIG_ENDIAN) | (1<<VDI_32BIT_LITTLE_ENDIAN) | (1<<VDI_32BIT_BIG_ENDIAN) | (0xffff<<16));
  126. pAttr->supportBitstreamMode = (1<<BS_MODE_INTERRUPT) | (1<<BS_MODE_PIC_END);
  127. pAttr->framebufferCacheType = FramebufCacheNone;
  128. pAttr->bitstreamBufferMargin = (pAttr->productId == PRODUCT_ID_7Q) ? 1024 : 0;
  129. pAttr->numberOfVCores = MAX_NUM_VCORE;
  130. pAttr->numberOfMemProtectRgns = 10;
  131. return RETCODE_SUCCESS;
  132. }
  133. Int32 WaveVpuGetProductId(Uint32 coreIdx)
  134. {
  135. Uint32 productId = PRODUCT_ID_NONE;
  136. Uint32 val;
  137. if (coreIdx >= MAX_NUM_VPU_CORE)
  138. return PRODUCT_ID_NONE;
  139. val = VpuReadReg(coreIdx, W4_PRODUCT_NUMBER);
  140. switch (val) {
  141. case WAVE410_CODE: productId = PRODUCT_ID_410; break;
  142. case WAVE4102_CODE: productId = PRODUCT_ID_4102; break;
  143. case WAVE420_CODE: productId = PRODUCT_ID_420; break;
  144. case WAVE412_CODE: productId = PRODUCT_ID_412; break;
  145. case CODA7Q_CODE: productId = PRODUCT_ID_7Q; break;
  146. case WAVE420L_CODE: productId = PRODUCT_ID_420L; break;
  147. case WAVE510_CODE: productId = PRODUCT_ID_510; break;
  148. case WAVE512_CODE: productId = PRODUCT_ID_512; break;
  149. case WAVE515_CODE: productId = PRODUCT_ID_515; break;
  150. case WAVE520_CODE: productId = PRODUCT_ID_520; break;
  151. default:
  152. VLOG(ERR, "Check productId(%d)\n", val);
  153. break;
  154. }
  155. return productId;
  156. }
  157. RetCode Wave4VpuGetVersion(Uint32 coreIdx, Uint32* versionInfo, Uint32* revision)
  158. {
  159. Uint32 regVal;
  160. CodecInstHeader hdr = {0};
  161. /* GET FIRMWARE&HARDWARE INFORMATION */
  162. hdr.coreIdx = 0;
  163. hdr.instIndex = 0;
  164. hdr.loggingEnable = 0;
  165. Wave4BitIssueCommand((CodecInst*)&hdr, GET_FW_VERSION);
  166. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_BUSY_STATUS) == -1) {
  167. return RETCODE_VPU_RESPONSE_TIMEOUT;
  168. }
  169. regVal = VpuReadReg(coreIdx, W4_RET_SUCCESS);
  170. if (regVal == 0)
  171. return RETCODE_FAILURE;
  172. regVal = VpuReadReg(coreIdx, W4_RET_FW_VERSION);
  173. if (versionInfo != NULL) {
  174. *versionInfo = 0;
  175. }
  176. if (revision != NULL) {
  177. *revision = regVal;
  178. }
  179. regVal = VpuReadReg(coreIdx,W4_RET_CONFIG_REVISION );
  180. VLOG(INFO, "\nget hw version %d !!!\n", regVal);
  181. return RETCODE_SUCCESS;
  182. }
  183. RetCode Wave4VpuInit(Uint32 coreIdx, void* firmware, Uint32 size)
  184. {
  185. vpu_buffer_t vb;
  186. PhysicalAddress codeBase;
  187. Uint32 codeSize;
  188. Uint32 i, regVal, remapSize;
  189. Uint32 hwOption = 0;
  190. CodecInstHeader hdr;
  191. osal_memset((void *)&hdr, 0x00, sizeof(CodecInstHeader));
  192. vdi_get_common_memory(coreIdx, &vb);
  193. codeBase = vb.phys_addr;
  194. /* ALIGN TO 4KB */
  195. codeSize = (WAVE4_MAX_CODE_BUF_SIZE&~0xfff);
  196. if (codeSize < size*2) {
  197. return RETCODE_INSUFFICIENT_RESOURCE;
  198. }
  199. VLOG(INFO, "\nVPU INIT Start!!!\n");
  200. VpuWriteMem(coreIdx, codeBase, (unsigned char*)firmware, size*2, VDI_128BIT_LITTLE_ENDIAN);
  201. vdi_set_bit_firmware_to_pm(coreIdx, (Uint16*)firmware);
  202. regVal = 0;
  203. VpuWriteReg(coreIdx, W4_PO_CONF, regVal);
  204. /* Reset All blocks */
  205. regVal = 0x7ffffff;
  206. VpuWriteReg(coreIdx, W4_VPU_RESET_REQ, regVal); // Reset All blocks
  207. /* Waiting reset done */
  208. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_RESET_STATUS) == -1) {
  209. VLOG(ERR, "VPU init(W4_VPU_RESET_REQ) timeout\n");
  210. VpuWriteReg(coreIdx, W4_VPU_RESET_REQ, 0);
  211. return RETCODE_VPU_RESPONSE_TIMEOUT;
  212. }
  213. VpuWriteReg(coreIdx, W4_VPU_RESET_REQ, 0);
  214. /* clear registers */
  215. for (i=W4_CMD_REG_BASE; i<W4_CMD_REG_END; i+=4)
  216. VpuWriteReg(coreIdx, i, 0x00);
  217. /* remap page size */
  218. remapSize = (codeSize >> 12) &0x1ff;
  219. regVal = 0x80000000 | (0 << 16) | (W4_REMAP_CODE_INDEX<<12) | (1<<11) | remapSize;
  220. VpuWriteReg(coreIdx, W4_VPU_REMAP_CTRL, regVal);
  221. VpuWriteReg(coreIdx, W4_VPU_REMAP_VADDR, 0x00000000); /* DO NOT CHANGE! */
  222. VpuWriteReg(coreIdx, W4_VPU_REMAP_PADDR, codeBase);
  223. VpuWriteReg(coreIdx, W4_ADDR_CODE_BASE, codeBase);
  224. VpuWriteReg(coreIdx, W4_CODE_SIZE, codeSize);
  225. VpuWriteReg(coreIdx, W4_CODE_PARAM, 0);
  226. //timeoutTicks = COMMAND_TIMEOUT*VCPU_CLOCK_IN_MHZ*(1000000>>15);
  227. VpuWriteReg(coreIdx, W4_TIMEOUT_CNT, 0xffffffff);
  228. VpuWriteReg(coreIdx, W4_HW_OPTION, hwOption);
  229. /* Interrupt */
  230. // for encoder interrupt
  231. regVal = (1<<W4_INT_ENC_PIC);
  232. regVal |= (1<<W4_INT_SLEEP_VPU);
  233. regVal |= (1<<W4_INT_SET_PARAM);
  234. // for decoder interrupt
  235. regVal |= (1<<W4_INT_DEC_PIC_HDR);
  236. regVal |= (1<<W4_INT_DEC_PIC);
  237. regVal |= (1<<W4_INT_QUERY_DEC);
  238. regVal |= (1<<W4_INT_SLEEP_VPU);
  239. regVal |= (1<<W4_INT_BSBUF_EMPTY);
  240. VpuWriteReg(coreIdx, W4_VPU_VINT_ENABLE, regVal);
  241. hdr.coreIdx = coreIdx;
  242. Wave4BitIssueCommand((CodecInst*)&hdr, INIT_VPU);
  243. VpuWriteReg(coreIdx, W4_VPU_REMAP_CORE_START, 1);
  244. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_BUSY_STATUS) == -1) {
  245. VLOG(ERR, "VPU init(W4_VPU_REMAP_CORE_START) timeout\n");
  246. return RETCODE_VPU_RESPONSE_TIMEOUT;
  247. }
  248. regVal = VpuReadReg(coreIdx, W4_RET_SUCCESS);
  249. if (regVal == 0) {
  250. Uint32 reasonCode = VpuReadReg(coreIdx, W4_RET_FAIL_REASON);
  251. VLOG(ERR, "VPU init(W4_RET_SUCCESS) failed(%d) REASON CODE(%08x)\n", regVal, reasonCode);
  252. return RETCODE_FAILURE;
  253. }
  254. SetupWave4Properties(coreIdx);
  255. return RETCODE_SUCCESS;
  256. }
  257. RetCode Wave4VpuReInit(Uint32 coreIdx, void* firmware, Uint32 size)
  258. {
  259. vpu_buffer_t vb;
  260. PhysicalAddress codeBase;
  261. PhysicalAddress oldCodeBase;
  262. Uint32 codeSize;
  263. Uint32 regVal, remapSize;
  264. CodecInstHeader hdr;
  265. osal_memset((void *)&hdr, 0x00, sizeof(CodecInstHeader));
  266. vdi_get_common_memory(coreIdx, &vb);
  267. codeBase = vb.phys_addr;
  268. /* ALIGN TO 4KB */
  269. codeSize = (WAVE4_MAX_CODE_BUF_SIZE&~0xfff);
  270. if (codeSize < size*2) {
  271. return RETCODE_INSUFFICIENT_RESOURCE;
  272. }
  273. oldCodeBase = VpuReadReg(coreIdx, W4_VPU_REMAP_PADDR);
  274. if (oldCodeBase != codeBase) {
  275. VpuWriteMem(coreIdx, codeBase, (unsigned char*)firmware, size*2, VDI_128BIT_LITTLE_ENDIAN);
  276. vdi_set_bit_firmware_to_pm(coreIdx, (Uint16*)firmware);
  277. regVal = 0;
  278. VpuWriteReg(coreIdx, W4_PO_CONF, regVal);
  279. // Waiting for completion of bus transaction
  280. // Step1 : disable request
  281. vdi_fio_write_register(coreIdx, W4_GDI_VCORE0_BUS_CTRL, 0x100); // WAVE410 GDI added new feature: disable_request
  282. // Step2 : Waiting for completion of bus transaction
  283. if (vdi_wait_bus_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_GDI_VCORE0_BUS_STATUS) == -1) {
  284. vdi_fio_write_register(coreIdx, W4_GDI_VCORE0_BUS_CTRL, 0x00);
  285. vdi_log(coreIdx, RESET_VPU, 2);
  286. return RETCODE_VPU_RESPONSE_TIMEOUT;
  287. }
  288. /* Reset All blocks */
  289. regVal = 0x7ffffff;
  290. VpuWriteReg(coreIdx, W4_VPU_RESET_REQ, regVal); // Reset All blocks
  291. /* Waiting reset done */
  292. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_RESET_STATUS) == -1) {
  293. VpuWriteReg(coreIdx, W4_VPU_RESET_REQ, 0);
  294. return RETCODE_VPU_RESPONSE_TIMEOUT;
  295. }
  296. VpuWriteReg(coreIdx, W4_VPU_RESET_REQ, 0);
  297. // Step3 : must clear GDI_BUS_CTRL after done SW_RESET
  298. vdi_fio_write_register(coreIdx, W4_GDI_VCORE0_BUS_CTRL, 0x00);
  299. /* not needed to clear registers
  300. for (i=W4_CMD_REG_BASE; i<W4_CMD_REG_END; i+=4)
  301. VpuWriteReg(coreIdx, i, 0x00)
  302. */
  303. /* remap page size */
  304. remapSize = (codeSize >> 12) &0x1ff;
  305. regVal = 0x80000000 | (W4_REMAP_CODE_INDEX<<12) | (0 << 16) | (1<<11) | remapSize;
  306. VpuWriteReg(coreIdx, W4_VPU_REMAP_CTRL, regVal);
  307. VpuWriteReg(coreIdx, W4_VPU_REMAP_VADDR, 0x00000000); /* DO NOT CHANGE! */
  308. VpuWriteReg(coreIdx, W4_VPU_REMAP_PADDR, codeBase);
  309. VpuWriteReg(coreIdx, W4_ADDR_CODE_BASE, codeBase);
  310. VpuWriteReg(coreIdx, W4_CODE_SIZE, codeSize);
  311. VpuWriteReg(coreIdx, W4_CODE_PARAM, 0);
  312. VpuWriteReg(coreIdx, W4_TIMEOUT_CNT, COMMAND_TIMEOUT);
  313. VpuWriteReg(coreIdx, W4_HW_OPTION, 0);
  314. /* Interrupt */
  315. // for encoder interrupt
  316. regVal = (1<<W4_INT_ENC_PIC);
  317. regVal |= (1<<W4_INT_SLEEP_VPU);
  318. regVal |= (1<<W4_INT_SET_PARAM);
  319. // for decoder interrupt
  320. regVal |= (1<<W4_INT_DEC_PIC_HDR);
  321. regVal |= (1<<W4_INT_DEC_PIC);
  322. regVal |= (1<<W4_INT_QUERY_DEC);
  323. regVal |= (1<<W4_INT_SLEEP_VPU);
  324. regVal |= (1<<W4_INT_BSBUF_EMPTY);
  325. VpuWriteReg(coreIdx, W4_VPU_VINT_ENABLE, regVal);
  326. hdr.coreIdx = coreIdx;
  327. Wave4BitIssueCommand((CodecInst*)&hdr, INIT_VPU);
  328. VpuWriteReg(coreIdx, W4_VPU_REMAP_CORE_START, 1);
  329. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_BUSY_STATUS) == -1) {
  330. return RETCODE_VPU_RESPONSE_TIMEOUT;
  331. }
  332. regVal = VpuReadReg(coreIdx, W4_RET_SUCCESS);
  333. if (regVal == 0)
  334. return RETCODE_FAILURE;
  335. }
  336. SetupWave4Properties(coreIdx);
  337. return RETCODE_SUCCESS;
  338. }
  339. Uint32 Wave4VpuIsInit(Uint32 coreIdx)
  340. {
  341. Uint32 pc;
  342. pc = (Uint32)VpuReadReg(coreIdx, W4_VCPU_CUR_PC);
  343. return pc;
  344. }
  345. Int32 Wave4VpuIsBusy(Uint32 coreIdx)
  346. {
  347. return VpuReadReg(coreIdx, W4_VPU_BUSY_STATUS);
  348. }
  349. Int32 Wave4VpuWaitInterrupt(CodecInst* handle, Int32 timeout)
  350. {
  351. Int32 reason = -1;
  352. Uint32 coreIdx = handle->coreIdx;
  353. if ((reason=vdi_wait_interrupt(coreIdx, timeout, W4_VPU_VINT_REASON_USR)) > 0) {
  354. /* If you are using device driver that we provide. the below codes are meaningless.
  355. * Because device driver clears interrupt.
  356. */
  357. VpuWriteReg(coreIdx, W4_VPU_VINT_REASON_CLR, reason);
  358. VpuWriteReg(coreIdx, W4_VPU_VINT_CLEAR, 1);
  359. }
  360. return reason;
  361. }
  362. RetCode Wave4VpuClearInterrupt(Uint32 coreIdx, Uint32 flags)
  363. {
  364. Uint32 interruptReason;
  365. interruptReason = VpuReadReg(coreIdx, W4_VPU_VINT_REASON_USR);
  366. interruptReason &= ~flags;
  367. VpuWriteReg(coreIdx, W4_VPU_VINT_REASON_USR, interruptReason);
  368. return RETCODE_SUCCESS;
  369. }
  370. RetCode Wave4VpuSleepWake(Uint32 coreIdx, int iSleepWake, const Uint16* code, Uint32 size)
  371. {
  372. CodecInstHeader hdr;
  373. Uint32 regVal;
  374. vpu_buffer_t vb;
  375. PhysicalAddress codeBase;
  376. Uint32 codeSize;
  377. Uint32 remapSize;
  378. osal_memset((void *)&hdr, 0x00, sizeof(CodecInstHeader));
  379. hdr.coreIdx = coreIdx;
  380. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_BUSY_STATUS) == -1) {
  381. return RETCODE_VPU_RESPONSE_TIMEOUT;
  382. }
  383. if(iSleepWake==1) //saves
  384. {
  385. Wave4BitIssueCommand((CodecInst*)&hdr, SLEEP_VPU);
  386. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_BUSY_STATUS) == -1)
  387. {
  388. return RETCODE_VPU_RESPONSE_TIMEOUT;
  389. }
  390. regVal = VpuReadReg(coreIdx, W4_RET_SUCCESS);
  391. if (regVal == 0)
  392. {
  393. APIDPRINT("SLEEP_VPU failed [0x%x]", VpuReadReg(coreIdx, W4_RET_FAIL_REASON));
  394. return RETCODE_FAILURE;
  395. }
  396. }
  397. else //restore
  398. {
  399. Uint32 hwOption = 0;
  400. vdi_get_common_memory(coreIdx, &vb);
  401. codeBase = vb.phys_addr;
  402. /* ALIGN TO 4KB */
  403. codeSize = (WAVE5_MAX_CODE_BUF_SIZE&~0xfff);
  404. if (codeSize < size*2) {
  405. return RETCODE_INSUFFICIENT_RESOURCE;
  406. }
  407. regVal = 0;
  408. VpuWriteReg(coreIdx, W4_PO_CONF, regVal);
  409. /* SW_RESET_SAFETY */
  410. regVal = W4_RST_BLOCK_ALL;
  411. VpuWriteReg(coreIdx, W4_VPU_RESET_REQ, regVal); // Reset All blocks
  412. /* Waiting reset done */
  413. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_RESET_STATUS) == -1) {
  414. VLOG(ERR, "VPU Wakeup(W4_VPU_RESET_REQ) timeout\n");
  415. VpuWriteReg(coreIdx, W4_VPU_RESET_REQ, 0);
  416. return RETCODE_VPU_RESPONSE_TIMEOUT;
  417. }
  418. VpuWriteReg(coreIdx, W4_VPU_RESET_REQ, 0);
  419. /* remap page size */
  420. remapSize = (codeSize >> 12) &0x1ff;
  421. regVal = 0x80000000 | (0 << 16) |(W4_REMAP_CODE_INDEX<<12) | (1<<11) | remapSize;
  422. VpuWriteReg(coreIdx, W4_VPU_REMAP_CTRL, regVal);
  423. VpuWriteReg(coreIdx, W4_VPU_REMAP_VADDR, 0x00000000); /* DO NOT CHANGE! */
  424. VpuWriteReg(coreIdx, W4_VPU_REMAP_PADDR, codeBase);
  425. VpuWriteReg(coreIdx, W4_ADDR_CODE_BASE, codeBase);
  426. VpuWriteReg(coreIdx, W4_CODE_SIZE, codeSize);
  427. VpuWriteReg(coreIdx, W4_CODE_PARAM, 0);
  428. VpuWriteReg(coreIdx, W4_TIMEOUT_CNT, COMMAND_TIMEOUT);
  429. VpuWriteReg(coreIdx, W4_HW_OPTION, hwOption);
  430. /* Interrupt */
  431. // for encoder interrupt
  432. regVal = (1<<W4_INT_ENC_PIC);
  433. regVal |= (1<<W4_INT_SLEEP_VPU);
  434. regVal |= (1<<W4_INT_SET_PARAM);
  435. // for decoder interrupt
  436. regVal |= (1<<W4_INT_DEC_PIC_HDR);
  437. regVal |= (1<<W4_INT_DEC_PIC);
  438. regVal |= (1<<W4_INT_QUERY_DEC);
  439. regVal |= (1<<W4_INT_SLEEP_VPU);
  440. regVal |= (1<<W4_INT_BSBUF_EMPTY);
  441. VpuWriteReg(coreIdx, W4_VPU_VINT_ENABLE, regVal);
  442. hdr.coreIdx = coreIdx;
  443. VpuWriteReg(coreIdx, W4_VPU_BUSY_STATUS, 1);
  444. VpuWriteReg(coreIdx, W4_RET_SUCCESS, 0); //for debug
  445. VpuWriteReg(coreIdx, W4_CORE_INDEX, 0);
  446. if (hdr.productId == PRODUCT_ID_7Q) // only coda7q use codecModeAux for DIV
  447. VpuWriteReg(coreIdx, W4_INST_INDEX, (hdr.instIndex&0xffff)|(hdr.codecMode<<16) | (hdr.codecModeAux<<24));
  448. else
  449. VpuWriteReg(coreIdx, W4_INST_INDEX, (hdr.instIndex&0xffff)|(hdr.codecMode<<16));
  450. VpuWriteReg(coreIdx, W4_COMMAND, INIT_VPU);
  451. if (hdr.loggingEnable) {
  452. vdi_log(coreIdx, INIT_VPU, 1);
  453. }
  454. VpuWriteReg(coreIdx, W4_VPU_REMAP_CORE_START, 1);
  455. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_BUSY_STATUS) == -1) {
  456. VLOG(ERR, "VPU Wakeup (W4_VPU_REMAP_CORE_START) timeout\n");
  457. return RETCODE_VPU_RESPONSE_TIMEOUT;
  458. }
  459. regVal = VpuReadReg(coreIdx, W4_RET_SUCCESS);
  460. if (regVal == 0) {
  461. Uint32 reasonCode = VpuReadReg(coreIdx, W4_RET_FAIL_REASON);
  462. VLOG(ERR, "VPU Wakeup(W4_RET_SUCCESS) failed(%d) REASON CODE(%08x)\n", regVal, reasonCode);
  463. return RETCODE_FAILURE;
  464. }
  465. }
  466. return RETCODE_SUCCESS;
  467. }
  468. RetCode Wave4VpuReset(Uint32 coreIdx, SWResetMode resetMode)
  469. {
  470. Uint32 val = 0;
  471. RetCode ret = RETCODE_FAILURE;
  472. VpuAttr* pAttr = &g_VpuCoreAttributes[coreIdx];
  473. // VPU doesn't send response. Force to set BUSY flag to 0.
  474. VpuWriteReg(coreIdx, W4_VPU_BUSY_STATUS, 0);
  475. if (pAttr->supportGDIHW == TRUE) {
  476. // Waiting for completion of bus transaction
  477. // Step1 : disable request
  478. vdi_fio_write_register(coreIdx, W4_GDI_VCORE0_BUS_CTRL, 0x100); // WAVE410 GDI added new feature: disable_request
  479. // Step2 : Waiting for completion of bus transaction
  480. if (vdi_wait_bus_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_GDI_VCORE0_BUS_STATUS) == -1) {
  481. vdi_fio_write_register(coreIdx, W4_GDI_VCORE0_BUS_CTRL, 0x00);
  482. vdi_log(coreIdx, RESET_VPU, 2);
  483. return RETCODE_VPU_RESPONSE_TIMEOUT;
  484. }
  485. }
  486. else {
  487. if (pAttr->productId == PRODUCT_ID_420L) {
  488. val = vdi_fio_read_register(coreIdx, W4_GDI_VCORE0_BUS_CTRL);
  489. if ((val>>24) == 0x01) {
  490. /* VPU has a bus transaction controller */
  491. vdi_fio_write_register(coreIdx, W4_GDI_VCORE0_BUS_CTRL, 0x11);
  492. }
  493. if (vdi_wait_bus_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_GDI_VCORE0_BUS_STATUS) == -1) {
  494. vdi_log(coreIdx, RESET_VPU, 2);
  495. return RETCODE_VPU_RESPONSE_TIMEOUT;
  496. }
  497. }
  498. }
  499. if (resetMode == SW_RESET_SAFETY) {
  500. if ((ret=Wave4VpuSleepWake(coreIdx, TRUE, NULL, 0)) != RETCODE_SUCCESS) {
  501. return ret;
  502. }
  503. }
  504. switch (resetMode) {
  505. case SW_RESET_ON_BOOT:
  506. case SW_RESET_FORCE:
  507. val = W4_RST_BLOCK_ALL;
  508. break;
  509. case SW_RESET_SAFETY:
  510. val = W4_RST_BLOCK_ACLK_ALL | W4_RST_BLOCK_BCLK_ALL | W4_RST_BLOCK_CCLK_ALL;
  511. break;
  512. default:
  513. return RETCODE_INVALID_PARAM;
  514. }
  515. if (val) {
  516. VpuWriteReg(coreIdx, W4_VPU_RESET_REQ, val);
  517. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_RESET_STATUS) == -1) {
  518. VpuWriteReg(coreIdx, W4_VPU_RESET_REQ, 0);
  519. vdi_log(coreIdx, RESET_VPU, 2);
  520. return RETCODE_VPU_RESPONSE_TIMEOUT;
  521. }
  522. VpuWriteReg(coreIdx, W4_VPU_RESET_REQ, 0);
  523. }
  524. if (pAttr->supportGDIHW == TRUE) {
  525. // Step3 : must clear GDI_BUS_CTRL after done SW_RESET
  526. vdi_fio_write_register(coreIdx, W4_GDI_VCORE0_BUS_CTRL, 0x00);
  527. }
  528. else {
  529. if (pAttr->productId == PRODUCT_ID_420L) {
  530. val = vdi_fio_read_register(coreIdx, W4_GDI_VCORE0_BUS_CTRL);
  531. if ((val>>24) == 0x01) {
  532. /* VPU has a bus transaction controller */
  533. vdi_fio_write_register(coreIdx, W4_GDI_VCORE0_BUS_CTRL, 0);
  534. }
  535. }
  536. }
  537. if (resetMode == SW_RESET_SAFETY || resetMode == SW_RESET_FORCE) {
  538. ret = Wave4VpuSleepWake(coreIdx, FALSE, NULL, 0);
  539. }
  540. return RETCODE_SUCCESS;
  541. }
  542. RetCode Wave4VpuBuildUpDecParam(CodecInst* instance, DecOpenParam* param)
  543. {
  544. RetCode ret = RETCODE_SUCCESS;
  545. DecInfo* pDecInfo;
  546. VpuAttr* pAttr = &g_VpuCoreAttributes[instance->coreIdx];
  547. pDecInfo = VPU_HANDLE_TO_DECINFO(instance);
  548. pDecInfo->streamRdPtrRegAddr = W4_BS_RD_PTR;
  549. pDecInfo->streamWrPtrRegAddr = W4_BS_WR_PTR;
  550. pDecInfo->frameDisplayFlagRegAddr = W4_RET_DEC_DISP_FLAG;
  551. pDecInfo->currentPC = W4_VCPU_CUR_PC;
  552. pDecInfo->busyFlagAddr = W4_VPU_BUSY_STATUS;
  553. if ((pAttr->supportDecoders&(1<<param->bitstreamFormat)) == 0)
  554. return RETCODE_NOT_SUPPORTED_FEATURE;
  555. pDecInfo->seqChangeMask = (param->bitstreamFormat == STD_HEVC) ?
  556. SEQ_CHANGE_ENABLE_ALL_HEVC : SEQ_CHANGE_ENABLE_ALL_VP9;
  557. pDecInfo->targetSubLayerId = HEVC_MAX_SUB_LAYER_ID;
  558. if (param->vbWork.size > 0) {
  559. pDecInfo->vbWork = param->vbWork;
  560. pDecInfo->workBufferAllocExt = TRUE;
  561. vdi_attach_dma_memory(instance->coreIdx, &param->vbWork);
  562. }
  563. else {
  564. if ((instance->productId == PRODUCT_ID_412) || (instance->productId == PRODUCT_ID_512) || (instance->productId == PRODUCT_ID_515)) {
  565. pDecInfo->vbWork.size = WAVE412DEC_WORKBUF_SIZE;
  566. }
  567. else {
  568. pDecInfo->vbWork.size = WAVE4DEC_WORKBUF_SIZE;
  569. }
  570. pDecInfo->workBufferAllocExt = FALSE;
  571. if (vdi_allocate_dma_memory(instance->coreIdx, &pDecInfo->vbWork) < 0) {
  572. pDecInfo->vbWork.base = 0;
  573. pDecInfo->vbWork.phys_addr = 0;
  574. pDecInfo->vbWork.size = 0;
  575. pDecInfo->vbWork.virt_addr = 0;
  576. return RETCODE_INSUFFICIENT_RESOURCE;
  577. }
  578. }
  579. vdi_clear_memory(instance->coreIdx, pDecInfo->vbWork.phys_addr, pDecInfo->vbWork.size, 0);
  580. VpuWriteReg(instance->coreIdx, W4_ADDR_WORK_BASE, pDecInfo->vbWork.phys_addr);
  581. VpuWriteReg(instance->coreIdx, W4_WORK_SIZE, pDecInfo->vbWork.size);
  582. VpuWriteReg(instance->coreIdx, W4_WORK_PARAM, 0);
  583. Wave4BitIssueCommand(instance, CREATE_INSTANCE);
  584. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_BUSY_STATUS) == -1) {
  585. if (instance->loggingEnable)
  586. vdi_log(instance->coreIdx, CREATE_INSTANCE, 2);
  587. vdi_free_dma_memory(instance->coreIdx, &pDecInfo->vbWork);
  588. return RETCODE_VPU_RESPONSE_TIMEOUT;
  589. }
  590. if (VpuReadReg(instance->coreIdx, W4_RET_SUCCESS) == FALSE) {
  591. vdi_free_dma_memory(instance->coreIdx, &pDecInfo->vbWork);
  592. ret = RETCODE_FAILURE;
  593. }
  594. return ret;
  595. }
  596. RetCode Wave4VpuDecFiniSeq(CodecInst* instance)
  597. {
  598. DecInfo* pDecInfo = VPU_HANDLE_TO_DECINFO(instance);
  599. VpuWriteReg(instance->coreIdx, W4_ADDR_WORK_BASE, pDecInfo->vbWork.phys_addr);
  600. VpuWriteReg(instance->coreIdx, W4_WORK_SIZE, pDecInfo->vbWork.size);
  601. VpuWriteReg(instance->coreIdx, W4_WORK_PARAM, 0);
  602. Wave4BitIssueCommand(instance, FINI_SEQ);
  603. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_BUSY_STATUS) == -1)
  604. return RETCODE_VPU_RESPONSE_TIMEOUT;
  605. if (VpuReadReg(instance->coreIdx, W4_RET_SUCCESS) == FALSE)
  606. return RETCODE_FAILURE;
  607. return RETCODE_SUCCESS;
  608. }
  609. RetCode Wave4VpuDecSetBitstreamFlag(CodecInst* instance, BOOL running, BOOL eos, BOOL explicitEnd)
  610. {
  611. DecInfo* pDecInfo = &instance->CodecInfo->decInfo;
  612. pDecInfo->streamEndflag = (eos == 1) ? TRUE : FALSE;
  613. if (running == TRUE) {
  614. BitStreamMode bsMode = (BitStreamMode)pDecInfo->openParam.bitstreamMode;
  615. BOOL explicitEndFlag=0;
  616. explicitEndFlag = (BOOL)(bsMode == BS_MODE_PIC_END || pDecInfo->streamEndflag == TRUE || explicitEnd == TRUE);
  617. VpuWriteReg(instance->coreIdx, W4_BS_OPTION, (pDecInfo->streamEndflag<<1)|explicitEndFlag );
  618. }
  619. return RETCODE_SUCCESS;
  620. }
  621. RetCode Wave4VpuDecRegisterFramebuffer(CodecInst* inst, FrameBuffer* fbArr, TiledMapType mapType, Uint32 count)
  622. {
  623. RetCode ret = RETCODE_SUCCESS;
  624. DecInfo* pDecInfo = &inst->CodecInfo->decInfo;
  625. DecInitialInfo* sequenceInfo = &inst->CodecInfo->decInfo.initialInfo;
  626. Int32 q, j, i, remain, idx;
  627. Uint32 mvCount;
  628. Uint32 k;
  629. Int32 coreIdx, startNo, endNo;
  630. Uint32 regVal, cbcrInterleave, nv21;
  631. Uint32 endian, yuvFormat = 0;
  632. Uint32 addrY, addrCb, addrCr;
  633. Uint32 mvColSize, fbcYTblSize, fbcCTblSize, lumaStride, chromaStride;
  634. vpu_buffer_t vbBuffer;
  635. Uint32 stride;
  636. Uint32 colorFormat = 0;
  637. Uint32 outputFormat = 0;
  638. Uint32 axiID;
  639. coreIdx = inst->coreIdx;
  640. axiID = pDecInfo->openParam.virtAxiID;
  641. cbcrInterleave = pDecInfo->openParam.cbcrInterleave;
  642. nv21 = pDecInfo->openParam.nv21;
  643. mvColSize = fbcYTblSize = fbcCTblSize = 0;
  644. if (mapType == COMPRESSED_FRAME_MAP) {
  645. cbcrInterleave = 0;
  646. nv21 = 0;
  647. if (inst->codecMode == C7_VP9_DEC) {
  648. mvColSize = WAVE4_DEC_VP9_MVCOL_BUF_SIZE(pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight);
  649. }
  650. else if (inst->codecMode == HEVC_DEC) {
  651. mvColSize = WAVE4_DEC_HEVC_MVCOL_BUF_SIZE(pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight);
  652. }
  653. else if (inst->codecMode == C7_AVS2_DEC) {
  654. mvColSize = CODA7Q_MVCOL_BUF_SIZE(pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight); // [FIX ME!!!]
  655. }
  656. else {
  657. mvColSize = CODA7Q_MVCOL_BUF_SIZE(pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight);
  658. }
  659. mvColSize = VPU_ALIGN16(mvColSize);
  660. vbBuffer.phys_addr = 0;
  661. if (inst->codecMode == HEVC_DEC || inst->codecMode == C7_HEVC_DEC || inst->codecMode == C7_VP9_DEC || inst->codecMode == C7_AVS2_DEC) {
  662. vbBuffer.size = ((mvColSize+4095)&~4095)+4096; /* 4096 is a margin */
  663. mvCount = count;
  664. for (k=0 ; k<mvCount ; k++) {
  665. if ( pDecInfo->vbMV[k].size == 0) {
  666. if (vdi_allocate_dma_memory(inst->coreIdx, &vbBuffer) < 0)
  667. return RETCODE_INSUFFICIENT_RESOURCE;
  668. pDecInfo->vbMV[k] = vbBuffer;
  669. }
  670. }
  671. }
  672. //VP9 Decoded size : 64 aligned.
  673. if (inst->codecMode == C7_VP9_DEC)
  674. fbcYTblSize = WAVE4_FBC_LUMA_TABLE_SIZE(VPU_ALIGN64(pDecInfo->initialInfo.picWidth), VPU_ALIGN64(pDecInfo->initialInfo.picHeight));
  675. else if (inst->codecMode == HEVC_DEC)
  676. fbcYTblSize = WAVE4_FBC_LUMA_TABLE_SIZE(pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight);
  677. else if (inst->codecMode == C7_AVS2_DEC)
  678. fbcYTblSize = CODA7Q_FBC_LUMA_TABLE_SIZE(pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight); // [FIX ME!!!]
  679. else
  680. fbcYTblSize = CODA7Q_FBC_LUMA_TABLE_SIZE(pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight);
  681. fbcYTblSize = VPU_ALIGN16(fbcYTblSize);
  682. vbBuffer.phys_addr = 0;
  683. vbBuffer.size = ((fbcYTblSize+4095)&~4095)+4096;
  684. for (k=0 ; k<count ; k++) {
  685. if ( pDecInfo->vbFbcYTbl[k].size == 0) {
  686. if (vdi_allocate_dma_memory(inst->coreIdx, &vbBuffer) < 0)
  687. return RETCODE_INSUFFICIENT_RESOURCE;
  688. pDecInfo->vbFbcYTbl[k] = vbBuffer;
  689. }
  690. }
  691. if (inst->codecMode == C7_VP9_DEC)
  692. fbcCTblSize = WAVE4_FBC_CHROMA_TABLE_SIZE(VPU_ALIGN64(pDecInfo->initialInfo.picWidth), VPU_ALIGN64(pDecInfo->initialInfo.picHeight));
  693. else if (inst->codecMode == HEVC_DEC)
  694. fbcCTblSize = WAVE4_FBC_CHROMA_TABLE_SIZE(pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight);
  695. else if (inst->codecMode == C7_AVS2_DEC)
  696. fbcCTblSize = CODA7Q_FBC_CHROMA_TABLE_SIZE(pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight); // [FIX ME!!!]
  697. else
  698. fbcCTblSize = CODA7Q_FBC_CHROMA_TABLE_SIZE(pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight);
  699. fbcCTblSize = VPU_ALIGN16(fbcCTblSize);
  700. vbBuffer.phys_addr = 0;
  701. vbBuffer.size = ((fbcCTblSize+4095)&~4095)+4096;
  702. for (k=0 ; k<count ; k++) {
  703. if ( pDecInfo->vbFbcCTbl[k].size == 0) {
  704. if (vdi_allocate_dma_memory(inst->coreIdx, &vbBuffer) < 0)
  705. return RETCODE_INSUFFICIENT_RESOURCE;
  706. pDecInfo->vbFbcCTbl[k] = vbBuffer;
  707. }
  708. }
  709. if (inst->productId == PRODUCT_ID_420 || inst->productId == PRODUCT_ID_420L) {
  710. lumaStride = VPU_ALIGN16(pDecInfo->initialInfo.picWidth)*(pDecInfo->initialInfo.lumaBitdepth>8 ? 5 : 4);
  711. lumaStride = VPU_ALIGN32(lumaStride);
  712. chromaStride = VPU_ALIGN16(pDecInfo->initialInfo.picWidth/2)*(pDecInfo->initialInfo.chromaBitdepth>8 ? 5 : 4);
  713. chromaStride = VPU_ALIGN32(chromaStride);
  714. VpuWriteReg(coreIdx, W4_FBC_STRIDE, lumaStride<<16 | chromaStride);
  715. }
  716. }
  717. endian = vdi_convert_endian(coreIdx, fbArr[0].endian) & VDI_128BIT_ENDIAN_MASK;
  718. regVal = (pDecInfo->initialInfo.picWidth<<16)|(pDecInfo->initialInfo.picHeight);
  719. VpuWriteReg(coreIdx, W4_PIC_SIZE, regVal);
  720. yuvFormat = 0; /* YUV420 8bit */
  721. if (mapType == LINEAR_FRAME_MAP) {
  722. BOOL justified = W4_WTL_RIGHT_JUSTIFIED;
  723. Uint32 formatNo = W4_WTL_PIXEL_8BIT;
  724. switch (pDecInfo->wtlFormat) {
  725. case FORMAT_420_P10_16BIT_MSB:
  726. justified = W4_WTL_RIGHT_JUSTIFIED;
  727. formatNo = W4_WTL_PIXEL_16BIT;
  728. break;
  729. case FORMAT_420_P10_16BIT_LSB:
  730. justified = W4_WTL_LEFT_JUSTIFIED;
  731. formatNo = W4_WTL_PIXEL_16BIT;
  732. break;
  733. case FORMAT_420_P10_32BIT_MSB:
  734. justified = W4_WTL_RIGHT_JUSTIFIED;
  735. formatNo = W4_WTL_PIXEL_32BIT;
  736. break;
  737. case FORMAT_420_P10_32BIT_LSB:
  738. justified = W4_WTL_LEFT_JUSTIFIED;
  739. formatNo = W4_WTL_PIXEL_32BIT;
  740. break;
  741. default:
  742. break;
  743. }
  744. yuvFormat = justified<<2 | formatNo;
  745. }
  746. stride = fbArr[0].stride;
  747. if (mapType == COMPRESSED_FRAME_MAP) {
  748. if ( pDecInfo->chFbcFrameIdx != -1 )
  749. stride = fbArr[pDecInfo->chFbcFrameIdx].stride;
  750. } else {
  751. if ( pDecInfo->chBwbFrameIdx != -1 )
  752. stride = fbArr[pDecInfo->chBwbFrameIdx].stride;
  753. }
  754. if (mapType == LINEAR_FRAME_MAP) {
  755. outputFormat = 0;
  756. outputFormat |= (nv21 << 1);
  757. outputFormat |= (cbcrInterleave << 0);
  758. if (inst->productId == PRODUCT_ID_420 || inst->productId == PRODUCT_ID_420L) {
  759. lumaStride = VPU_ALIGN16(pDecInfo->initialInfo.picWidth)*(pDecInfo->initialInfo.lumaBitdepth>8 ? 5 : 4);
  760. lumaStride = VPU_ALIGN32(lumaStride);
  761. chromaStride = VPU_ALIGN16(pDecInfo->initialInfo.picWidth/2)*(pDecInfo->initialInfo.chromaBitdepth>8 ? 5 : 4);
  762. chromaStride = VPU_ALIGN32(chromaStride);
  763. VpuWriteReg(coreIdx, W4_FBC_STRIDE, lumaStride<<16 | chromaStride);
  764. }
  765. }
  766. regVal =
  767. ((mapType == LINEAR_FRAME_MAP)<< 28) |
  768. (axiID << 24) |
  769. (1<< 23) | /* PIXEL ORDER in 128bit. first pixel in low address */
  770. (yuvFormat << 20) |
  771. (colorFormat << 19) |
  772. (outputFormat << 16) |
  773. (stride);
  774. VpuWriteReg(coreIdx, W4_COMMON_PIC_INFO, regVal);
  775. if ( pDecInfo->interResChange == 1)
  776. {
  777. i=0;
  778. // W4_SFB_OPTION [2:0] : 0x3 = SET_FB_UPDATE_MODE
  779. VpuWriteReg(coreIdx, W4_SFB_OPTION, (pDecInfo->openParam.fbc_mode<<20) | (endian<<16) | (1<<4) | (1<<3) | 3);
  780. if (mapType == COMPRESSED_FRAME_MAP) {
  781. idx=pDecInfo->chFbcFrameIdx;
  782. } else {
  783. idx=pDecInfo->chBwbFrameIdx;
  784. }
  785. VpuWriteReg(coreIdx, W4_SET_FB_NUM, (idx<<8)|idx);
  786. if (mapType == LINEAR_FRAME_MAP && pDecInfo->openParam.cbcrOrder == CBCR_ORDER_REVERSED) {
  787. addrY = fbArr[idx].bufY;
  788. addrCb = fbArr[idx].bufCr;
  789. addrCr = fbArr[idx].bufCb;
  790. }
  791. else {
  792. addrY = fbArr[idx].bufY;
  793. addrCb = fbArr[idx].bufCb;
  794. addrCr = fbArr[idx].bufCr;
  795. }
  796. VpuWriteReg(coreIdx, W4_ADDR_LUMA_BASE0 + (i<<4), addrY);
  797. VpuWriteReg(coreIdx, W4_ADDR_CB_BASE0 + (i<<4), addrCb);
  798. APIDPRINT("REGISTER FB[%02d] Y(0x%08x), Cb(0x%08x) ", i, addrY, addrCb);
  799. if (mapType == COMPRESSED_FRAME_MAP) {
  800. VpuWriteReg(coreIdx, W4_ADDR_FBC_Y_OFFSET0 + (i<<4), pDecInfo->vbFbcYTbl[idx].phys_addr); /* Luma FBC offset table */
  801. VpuWriteReg(coreIdx, W4_ADDR_FBC_C_OFFSET0 + (i<<4), pDecInfo->vbFbcCTbl[idx].phys_addr); /* Chroma FBC offset table */
  802. VpuWriteReg(coreIdx, W4_ADDR_MV_COL0 + (i<<2), pDecInfo->vbMV[idx].phys_addr);
  803. APIDPRINT("Yo(0x%08x) Co(0x%08x), Mv(0x%08x)\n",
  804. pDecInfo->vbFbcYTbl[idx].phys_addr,
  805. pDecInfo->vbFbcCTbl[idx].phys_addr,
  806. pDecInfo->vbMV[idx].phys_addr);
  807. }
  808. else {
  809. VpuWriteReg(coreIdx, W4_ADDR_CR_BASE0 + (i<<4), addrCr);
  810. VpuWriteReg(coreIdx, W4_ADDR_FBC_C_OFFSET0 + (i<<4), 0);
  811. VpuWriteReg(coreIdx, W4_ADDR_MV_COL0 + (i<<2), 0);
  812. APIDPRINT("Cr(0x%08x)\n", addrCr);
  813. }
  814. VpuWriteReg(coreIdx, W4_ADDR_WORK_BASE, pDecInfo->vbWork.phys_addr);
  815. VpuWriteReg(coreIdx, W4_WORK_SIZE, pDecInfo->vbWork.size);
  816. VpuWriteReg(coreIdx, W4_WORK_PARAM, 0);
  817. Wave4BitIssueCommand(inst, SET_FRAMEBUF);
  818. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_BUSY_STATUS) == -1) {
  819. return RETCODE_VPU_RESPONSE_TIMEOUT;
  820. }
  821. }
  822. else
  823. {
  824. remain = count;
  825. q = (remain+7)/8;
  826. idx = 0;
  827. for (j=0; j<q; j++) {
  828. regVal = (pDecInfo->openParam.fbc_mode<<20)|(endian<<16) | (j==q-1)<<4 | ((j==0)<<3) ;
  829. VpuWriteReg(coreIdx, W4_SFB_OPTION, regVal);
  830. startNo = j*8;
  831. endNo = startNo + (remain>=8 ? 8 : remain) - 1;
  832. VpuWriteReg(coreIdx, W4_SET_FB_NUM, (startNo<<8)|endNo);
  833. for (i=0; i<8 && i<remain; i++) {
  834. if (mapType == LINEAR_FRAME_MAP && pDecInfo->openParam.cbcrOrder == CBCR_ORDER_REVERSED) {
  835. addrY = fbArr[i+startNo].bufY;
  836. addrCb = fbArr[i+startNo].bufCr;
  837. addrCr = fbArr[i+startNo].bufCb;
  838. }
  839. else {
  840. addrY = fbArr[i+startNo].bufY;
  841. addrCb = fbArr[i+startNo].bufCb;
  842. addrCr = fbArr[i+startNo].bufCr;
  843. }
  844. VpuWriteReg(coreIdx, W4_ADDR_LUMA_BASE0 + (i<<4), addrY);
  845. VpuWriteReg(coreIdx, W4_ADDR_CB_BASE0 + (i<<4), addrCb);
  846. APIDPRINT("REGISTER FB[%02d] Y(0x%08x), Cb(0x%08x) ", i, addrY, addrCb);
  847. if (mapType == COMPRESSED_FRAME_MAP) {
  848. VpuWriteReg(coreIdx, W4_ADDR_FBC_Y_OFFSET0 + (i<<4), pDecInfo->vbFbcYTbl[idx].phys_addr); /* Luma FBC offset table */
  849. VpuWriteReg(coreIdx, W4_ADDR_FBC_C_OFFSET0 + (i<<4), pDecInfo->vbFbcCTbl[idx].phys_addr); /* Chroma FBC offset table */
  850. VpuWriteReg(coreIdx, W4_ADDR_MV_COL0 + (i<<2), pDecInfo->vbMV[idx].phys_addr);
  851. APIDPRINT("Yo(0x%08x) Co(0x%08x), Mv(0x%08x)\n",
  852. pDecInfo->vbFbcYTbl[idx].phys_addr,
  853. pDecInfo->vbFbcCTbl[idx].phys_addr,
  854. pDecInfo->vbMV[idx].phys_addr);
  855. }
  856. else {
  857. VpuWriteReg(coreIdx, W4_ADDR_CR_BASE0 + (i<<4), addrCr);
  858. VpuWriteReg(coreIdx, W4_ADDR_FBC_C_OFFSET0 + (i<<4), 0);
  859. VpuWriteReg(coreIdx, W4_ADDR_MV_COL0 + (i<<2), 0);
  860. APIDPRINT("Cr(0x%08x)\n", addrCr);
  861. }
  862. idx++;
  863. }
  864. remain -= i;
  865. VpuWriteReg(coreIdx, W4_ADDR_WORK_BASE, pDecInfo->vbWork.phys_addr);
  866. VpuWriteReg(coreIdx, W4_WORK_SIZE, pDecInfo->vbWork.size);
  867. VpuWriteReg(coreIdx, W4_WORK_PARAM, 0);
  868. // CODA7Q needs temporal buffer address.
  869. VpuWriteReg(coreIdx, W4_ADDR_TEMP_BASE, pDecInfo->vbTemp.phys_addr);
  870. VpuWriteReg(coreIdx, W4_TEMP_SIZE, pDecInfo->vbTemp.size);
  871. VpuWriteReg(coreIdx, W4_TEMP_PARAM, 0);
  872. Wave4BitIssueCommand(inst, SET_FRAMEBUF);
  873. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_BUSY_STATUS) == -1) {
  874. return RETCODE_VPU_RESPONSE_TIMEOUT;
  875. }
  876. }
  877. }
  878. regVal = VpuReadReg(coreIdx, W4_RET_SUCCESS);
  879. if (regVal == 0) {
  880. return RETCODE_FAILURE;
  881. }
  882. if (inst->productId == PRODUCT_ID_7Q) {
  883. if (ConfigSecAXICoda7(coreIdx, pDecInfo->openParam.bitstreamFormat,
  884. &pDecInfo->secAxiInfo,
  885. pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight, sequenceInfo->profile) == 0) {
  886. return RETCODE_INSUFFICIENT_RESOURCE;
  887. }
  888. }
  889. else {
  890. if (ConfigSecAXIWave(coreIdx, inst->codecMode,
  891. &pDecInfo->secAxiInfo, pDecInfo->initialInfo.picWidth, pDecInfo->initialInfo.picHeight,
  892. sequenceInfo->profile, sequenceInfo->level) == 0) {
  893. return RETCODE_INSUFFICIENT_RESOURCE;
  894. }
  895. }
  896. return ret;
  897. }
  898. RetCode Wave4VpuDecFlush(CodecInst* instance, FramebufferIndex* framebufferIndexes, Uint32 size)
  899. {
  900. Int32 regVal;
  901. Uint32 i, j;
  902. DecInfo* pDecInfo = &instance->CodecInfo->decInfo;
  903. VpuWriteReg(instance->coreIdx, W4_FLUSH_DECODER_OPTION, FLUSH_DPB);
  904. /* Set up work-buffer */
  905. VpuWriteReg(instance->coreIdx, W4_ADDR_WORK_BASE, pDecInfo->vbWork.phys_addr);
  906. VpuWriteReg(instance->coreIdx, W4_WORK_SIZE, pDecInfo->vbWork.size);
  907. VpuWriteReg(instance->coreIdx, W4_WORK_PARAM, 0);
  908. Wave4BitIssueCommand(instance, FLUSH_DECODER);
  909. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_BUSY_STATUS) == -1) {
  910. return RETCODE_VPU_RESPONSE_TIMEOUT;
  911. }
  912. // Clear display flags.
  913. pDecInfo->frameDisplayFlag = 0;
  914. regVal = VpuReadReg(instance->coreIdx, W4_RET_SUCCESS);
  915. if (regVal == 0) {
  916. return RETCODE_FAILURE;
  917. }
  918. /* Get remaining framebuffers */
  919. if (framebufferIndexes != NULL) {
  920. for (j=0,i=W4_RET_DEC_DISPLAY_INDEX_0; i<=W4_RET_DEC_DISPLAY_INDEX_15 && j<size; i+=4, j++) {
  921. regVal = VpuReadReg(instance->coreIdx, i);
  922. framebufferIndexes[j].linearIndex = regVal>>16;
  923. framebufferIndexes[j].tiledIndex = regVal&0xffff;
  924. if (pDecInfo->wtlEnable == FALSE)
  925. framebufferIndexes[j].linearIndex = framebufferIndexes[j].tiledIndex;
  926. APIDPRINT("FLUSH LINEAR(%d) TILED(%d)\n", framebufferIndexes[j].linearIndex, framebufferIndexes[j].tiledIndex);
  927. }
  928. }
  929. return RETCODE_SUCCESS;
  930. }
  931. RetCode Wave4VpuEncFiniSeq(CodecInst* instance)
  932. {
  933. EncInfo* pEncInfo = VPU_HANDLE_TO_ENCINFO(instance);
  934. VpuWriteReg(instance->coreIdx, W4_ADDR_WORK_BASE, pEncInfo->vbWork.phys_addr);
  935. VpuWriteReg(instance->coreIdx, W4_WORK_SIZE, pEncInfo->vbWork.size);
  936. VpuWriteReg(instance->coreIdx, W4_WORK_PARAM, 0);
  937. Wave4BitIssueCommand(instance, FINI_SEQ);
  938. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_BUSY_STATUS) == -1)
  939. return RETCODE_VPU_RESPONSE_TIMEOUT;
  940. if (VpuReadReg(instance->coreIdx, W4_RET_SUCCESS) == FALSE)
  941. return RETCODE_FAILURE;
  942. return RETCODE_SUCCESS;
  943. }
  944. RetCode Wave4VpuBuildUpEncParam(CodecInst* instance, EncOpenParam* param)
  945. {
  946. RetCode ret = RETCODE_SUCCESS;
  947. VpuAttr* pAttr = &g_VpuCoreAttributes[instance->coreIdx];
  948. EncInfo* pEncInfo = &instance->CodecInfo->encInfo;
  949. pEncInfo->streamRdPtrRegAddr = W4_BS_RD_PTR;
  950. pEncInfo->streamWrPtrRegAddr = W4_BS_WR_PTR;
  951. pEncInfo->currentPC = W4_VCPU_CUR_PC;
  952. pEncInfo->busyFlagAddr = W4_VPU_BUSY_STATUS;
  953. if (instance->productId == PRODUCT_ID_7Q) {
  954. if (param->bitstreamFormat == STD_HEVC)
  955. instance->codecMode = C7_HEVC_ENC;
  956. else if (param->bitstreamFormat == STD_AVC)
  957. instance->codecMode = C7_AVC_ENC;
  958. else if (param->bitstreamFormat == STD_MPEG4 || param->bitstreamFormat == STD_H263)
  959. instance->codecMode = C7_MP4_ENC;
  960. else
  961. return RETCODE_NOT_SUPPORTED_FEATURE;
  962. }
  963. else {
  964. if (param->bitstreamFormat == STD_HEVC)
  965. instance->codecMode = HEVC_ENC;
  966. else
  967. return RETCODE_NOT_SUPPORTED_FEATURE;
  968. }
  969. if ((pAttr->supportEncoders&(1<<param->bitstreamFormat)) == 0)
  970. return RETCODE_NOT_SUPPORTED_FEATURE;
  971. pEncInfo->vbWork.size = WAVE4ENC_WORKBUF_SIZE;
  972. if (vdi_allocate_dma_memory(instance->coreIdx, &pEncInfo->vbWork) < 0)
  973. {
  974. pEncInfo->vbWork.base = 0;
  975. pEncInfo->vbWork.phys_addr = 0;
  976. pEncInfo->vbWork.size = 0;
  977. pEncInfo->vbWork.virt_addr = 0;
  978. return RETCODE_INSUFFICIENT_RESOURCE;
  979. }
  980. vdi_clear_memory(instance->coreIdx, pEncInfo->vbWork.phys_addr, pEncInfo->vbWork.size, 0);
  981. VpuWriteReg(instance->coreIdx, W4_ADDR_WORK_BASE, pEncInfo->vbWork.phys_addr);
  982. VpuWriteReg(instance->coreIdx, W4_WORK_SIZE, pEncInfo->vbWork.size);
  983. VpuWriteReg(instance->coreIdx, W4_WORK_PARAM, 0);
  984. Wave4BitIssueCommand(instance, CREATE_INSTANCE);
  985. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_BUSY_STATUS) == -1) {
  986. if (instance->loggingEnable)
  987. vdi_log(instance->coreIdx, CREATE_INSTANCE, 2);
  988. vdi_free_dma_memory(instance->coreIdx, &pEncInfo->vbWork);
  989. return RETCODE_VPU_RESPONSE_TIMEOUT;
  990. }
  991. if (VpuReadReg(instance->coreIdx, W4_RET_SUCCESS) == FALSE) {
  992. vdi_free_dma_memory(instance->coreIdx, &pEncInfo->vbWork);
  993. ret = RETCODE_FAILURE;
  994. }
  995. pEncInfo->streamRdPtr = param->bitstreamBuffer;
  996. pEncInfo->streamWrPtr = param->bitstreamBuffer;
  997. pEncInfo->lineBufIntEn = param->lineBufIntEn;
  998. pEncInfo->streamBufStartAddr = param->bitstreamBuffer;
  999. pEncInfo->streamBufSize = param->bitstreamBufferSize;
  1000. pEncInfo->streamBufEndAddr = param->bitstreamBuffer + param->bitstreamBufferSize;
  1001. pEncInfo->stride = 0;
  1002. pEncInfo->vbFrame.size = 0;
  1003. pEncInfo->vbPPU.size = 0;
  1004. pEncInfo->frameAllocExt = 0;
  1005. pEncInfo->ppuAllocExt = 0;
  1006. pEncInfo->secAxiInfo.u.wave4.useBitEnable = 0;
  1007. pEncInfo->secAxiInfo.u.wave4.useIpEnable = 0;
  1008. pEncInfo->secAxiInfo.u.wave4.useLfRowEnable = 0;
  1009. pEncInfo->rotationEnable = 0;
  1010. pEncInfo->mirrorEnable = 0;
  1011. pEncInfo->mirrorDirection = MIRDIR_NONE;
  1012. pEncInfo->rotationAngle = 0;
  1013. pEncInfo->initialInfoObtained = 0;
  1014. pEncInfo->ringBufferEnable = param->ringBufferEnable;
  1015. pEncInfo->sliceIntEnable = 0;
  1016. return ret;
  1017. }