coda7q_regdefine.h 9.0 KB

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  1. /* SPDX-License-Identifier: LGPL-2.1 OR BSD-3-Clause */
  2. //--=========================================================================--
  3. // This file is a part of VPU Reference API project
  4. //-----------------------------------------------------------------------------
  5. //
  6. // This confidential and proprietary software may be used only
  7. // as authorized by a licensing agreement from Chips&Media Inc.
  8. // In the event of publication, the following notice is applicable:
  9. //
  10. // (C) COPYRIGHT 2006 - 2013 CHIPS&MEDIA INC.
  11. // ALL RIGHTS RESERVED
  12. //
  13. // The entire notice above must be reproduced on all authorized
  14. // copies.
  15. //
  16. //--=========================================================================--
  17. #ifndef __CODA7Q_REGISTER_DEFINE_H__
  18. #define __CODA7Q_REGISTER_DEFINE_H__
  19. #define C7_REG_BASE 0x00000000
  20. #define C7_CMD_REG_BASE 0x00000100
  21. #define C7_CMD_REG_END 0x00000200
  22. //------------------------------------------------------------------------------
  23. // [DEC SEQ INIT : DEC_PIC_HDR] COMMAND for CODA7Q
  24. //------------------------------------------------------------------------------
  25. #define C7_CMD_DEC_SEQ_USER_DATA_OPTION (C7_REG_BASE + 0x174)
  26. #define C7_CMD_DEC_USER_DATA_MASK (C7_REG_BASE + 0x174)
  27. #define C7_RET_DEC_USER_FLAG (C7_REG_BASE + 0x174)
  28. #define C7_CMD_DEC_SEVERITY_LEVEL (C7_REG_BASE + 0x178)
  29. #define C7_CMD_DEC_SEQ_OPTION (C7_REG_BASE + 0x178)
  30. #define C7_CMD_DEC_VCORE_LIMIT (C7_REG_BASE + 0x17C)
  31. #define C7_RET_DEC_NUM_REORDER_DELAY (C7_REG_BASE + 0x188)
  32. #define C7_CMD_DEC_FORCE_FB_LATENCY_PLUS1 (C7_REG_BASE + 0x188)
  33. #define C7_CMD_DEC_TEMPORAL_ID (C7_REG_BASE + 0x18C)
  34. #define C7_CMD_SEQ_CHANGE_ENABLE_FLAG (C7_REG_BASE + 0x194)
  35. #define C7_RET_DEC_SEQ_PARAM (C7_REG_BASE + 0x198)
  36. #define C7_RET_DEC_SEQ_HEADER_REPORT (C7_REG_BASE + 0x198)
  37. #define C7_RET_DEC_SEQ_VUI_INFO (C7_REG_BASE + 0x19C)
  38. #define C7_RET_DEC_COLOR_SAMPLE_INFO (C7_REG_BASE + 0x1A0)
  39. #define C7_RET_DEC_ASPECT_RATIO (C7_REG_BASE + 0x1A4)
  40. #define C7_RET_DEC_BIT_RATE (C7_REG_BASE + 0x1A8)
  41. #define C7_RET_DEC_FRAME_RATE_NR (C7_REG_BASE + 0x1AC)
  42. #define C7_RET_DEC_FRAME_RATE_DR (C7_REG_BASE + 0x1B0)
  43. #define C7_RET_DEC_CROP_TOP_BOTTOM (C7_REG_BASE + 0x1B4)
  44. #define C7_RET_DEC_CROP_LEFT_RIGHT (C7_REG_BASE + 0x1B8)
  45. #define C7_CMD_DEC_SEQ_SRC_SIZE (C7_REG_BASE + 0x1BC)
  46. #define C7_RET_DEC_PIC_SIZE (C7_REG_BASE + 0x1BC)
  47. #define C7_RET_DEC_FRAMEBUF_NEEDED (C7_REG_BASE + 0x1C0)
  48. #define C7_FRAME_COUNT (C7_REG_BASE + 0x1D4)
  49. #define C7_RET_DEC_SEQ_INFO (C7_REG_BASE + 0x1DC)
  50. #define C7_RET_DEC_SEQ_VP8_SCALE_INFO (C7_REG_BASE + 0x1DC)
  51. #define C7_CMD_DEC_SEQ_MP4_ASP_CLASS (C7_REG_BASE + 0x1E0)
  52. #define C7_CMD_DEC_SEQ_X264_MV_EN (C7_REG_BASE + 0x1E0)
  53. #define C7_CMD_DEC_SEQ_VC1_STREAM_FMT (C7_REG_BASE + 0x1E0)
  54. //------------------------------------------------------------------------------
  55. // [DEC PIC] COMMAND for CODA7Q
  56. //------------------------------------------------------------------------------
  57. #define C7_RET_DEC_PIC_HRD_INFO (C7_REG_BASE + 0x17C)
  58. #define C7_RET_DEC_PIC_AVC_FPA_SEI0 (C7_REG_BASE + 0x180)
  59. #define C7_RET_DEC_PIC_AVC_FPA_SEI1 (C7_REG_BASE + 0x184)
  60. #define C7_RET_DEC_PIC_AVC_FPA_SEI2 (C7_REG_BASE + 0x18C)
  61. #define C7_BIT_FRM_DIS_FLG (C7_REG_BASE + 0x190)
  62. #define C7_RET_DEC_PIC_VUI_INFO (C7_REG_BASE + 0x19C)
  63. #define C7_RET_DEC_PIC_VUI_PIC_STRUCT (C7_REG_BASE + 0x1A0)
  64. #define C7_RET_DEC_PIC_ASPECT (C7_REG_BASE + 0x1A4)
  65. #define C7_RET_DEC_PIC_FRAME_NR (C7_REG_BASE + 0x1AC)
  66. #define C7_RET_DEC_PIC_FRAME_DR (C7_REG_BASE + 0x1B0)
  67. #define C7_RET_DEC_PIC_RV_TR (C7_REG_BASE + 0x1AC)
  68. #define C7_RET_DEC_PIC_RV_TR_BFRAME (C7_REG_BASE + 0x1B0)
  69. #define C7_RET_DEC_SEQ_CHANGE_FLAG (C7_REG_BASE + 0x1C4)
  70. #define C7_RET_DEC_PIC_VP8_PIC_REPORT (C7_REG_BASE + 0x1C8)
  71. #define C7_RET_DEC_PIC_POST (C7_REG_BASE + 0x1D0)
  72. #define C7_RET_DEC_PIC_MVC_REPORT (C7_REG_BASE + 0x1D0)
  73. #define C7_RET_DEC_WARN_INFO (C7_REG_BASE + 0x1D8)
  74. #define C7_RET_DEC_PIC_VP8_SCALE_INFO (C7_REG_BASE + 0x1DC)
  75. #define C7_RET_DEC_PRESCAN_INDEX (C7_REG_BASE + 0x1DC)
  76. #define C7_RET_DEC_PIC_DECODED_IDX (C7_REG_BASE + 0x1E0)
  77. #define C7_RET_DEC_PIC_DISPLAY_IDX (C7_REG_BASE + 0x1E4)
  78. #define C7_RET_DEC_PIC_TYPE (C7_REG_BASE + 0x1E8)
  79. #define C7_RET_DEC_PIC_POC (C7_REG_BASE + 0x1EC)
  80. #define C7_RET_DEC_PIC_ERR_MB (C7_REG_BASE + 0x1F0)
  81. #define C7_RET_DEC_ERR_INFO (C7_REG_BASE + 0x1F4)
  82. #define C7_RET_DEC_ERR_CTB_NUM (C7_REG_BASE + 0x1F0)
  83. #define C7_RET_DEC_ERR_INFO (C7_REG_BASE + 0x1F4)
  84. #define C7_RET_DEC_AU_START_POS (C7_REG_BASE + 0x1F8)
  85. #define C7_RET_DEC_AU_END_POS (C7_REG_BASE + 0x1FC)
  86. #endif /* __CODA7Q_REGISTER_DEFINE_H__ */
  87. //------------------------------------------------------------------------------
  88. // [ENC SEQ INIT] COMMAND
  89. //------------------------------------------------------------------------------
  90. #define C7_CMD_ENC_SET_PARAM_OPTION (C7_REG_BASE + 0x10C)
  91. #define C7_CMD_ENC_SEQ_SRC_SIZE (C7_REG_BASE + 0x160)
  92. #define C7_CMD_ENC_SEQ_PARAM (C7_REG_BASE + 0x16C)
  93. #define C7_CMD_ENC_SEQ_GOP_NUM (C7_REG_BASE + 0x170)
  94. #define C7_CMD_ENC_SEQ_INTRA_PARAM (C7_REG_BASE + 0x174)
  95. #define C7_CMD_ENC_SEQ_SRC_F_RATE (C7_REG_BASE + 0x180)
  96. #define C7_CMD_ENC_SEQ_SLICE_MODE (C7_REG_BASE + 0x184)
  97. #define C7_CMD_ENC_SEQ_OPTION (C7_REG_BASE + 0x188) // HecEnable,ConstIntraQp, FMO, QPREP, AUD, SLICE, MB BIT
  98. #define C7_CMD_ENC_PARAM (C7_REG_BASE + 0x190)
  99. #define C7_CMD_ENC_SEQ_RC_PARAM (C7_REG_BASE + 0x198)
  100. #define C7_CMD_ENC_SEQ_RC_MAX_QP (C7_REG_BASE + 0x19C)
  101. #define C7_CMD_ENC_RC_TARGET_RATE (C7_REG_BASE + 0x1C0)
  102. #define C7_CMD_ENC_ROT_PARAM (C7_REG_BASE + 0x1C4)
  103. #define C7_CMD_ENC_SEQ_STD_PARA (C7_REG_BASE + 0x1DC)
  104. #define C7_CMD_ENC_SEQ_AUX_PARA (C7_REG_BASE + 0x1E0)
  105. #define C7_CMD_ENC_SEARCH_BASE (C7_REG_BASE + 0x1E8)
  106. #define C7_CMD_ENC_SEARCH_SIZE (C7_REG_BASE + 0x1EC)
  107. #define C7_CMD_ENC_SEQ_RC_GAMMA (C7_REG_BASE + 0x1F0)
  108. #define C7_CMD_ENC_SEQ_RC_INTERVAL_MODE (C7_REG_BASE + 0x1F4) // mbInterval[32:2], rcIntervalMode[1:0]
  109. #define C7_CMD_ENC_SEQ_INTRA_WEIGHT (C7_REG_BASE + 0x1F8)
  110. #define C7_CMD_ENC_SEQ_RC_BUF_SIZE (C7_REG_BASE + 0x1FC)
  111. //------------------------------------------------------------------------------
  112. // [ENC SEQ END] COMMAND
  113. //------------------------------------------------------------------------------
  114. #define C7_RET_ENC_AXI_ALLOC_BUF_FAIL (C7_REG_BASE + 0x1C8)
  115. #define C7_RET_ENC_MIN_FB_NUM (C7_REG_BASE + 0x1CC)
  116. #define C7_RET_ENC_NAL_INFO_TO_BE_ENCODED (C7_REG_BASE + 0x1D0)
  117. #define C7_RET_ENC_MIN_SRC_BUF_NUM (C7_REG_BASE + 0x1D8)
  118. //------------------------------------------------------------------------------
  119. // [ENC PIC] COMMAND for CODA7Q
  120. //------------------------------------------------------------------------------
  121. #define C7_CMD_ENC_PIC_OPTION (C7_REG_BASE + 0x10C)
  122. #define C7_CMD_ENC_ADDR_REPORT_BASE (C7_REG_BASE + 0x15C)
  123. #define C7_CMD_ENC_REPORT_SIZE (C7_REG_BASE + 0x160)
  124. #define C7_CMD_ENC_REPORT_PARAM (C7_REG_BASE + 0x164)
  125. #define C7_CMD_ENC_CODE_OPTION (C7_REG_BASE + 0x168)
  126. #define C7_CMD_ENC_PIC_PARAM (C7_REG_BASE + 0x16C)
  127. #define C7_CMD_ENC_SRC_ADDR_Y (C7_REG_BASE + 0x174)
  128. #define C7_CMD_ENC_SRC_ADDR_U (C7_REG_BASE + 0x178)
  129. #define C7_CMD_ENC_SRC_ADDR_V (C7_REG_BASE + 0x17C)
  130. #define C7_CMD_ENC_SRC_STRIDE (C7_REG_BASE + 0x180)
  131. #define C7_CMD_ENC_SRC_FORMAT (C7_REG_BASE + 0x184)
  132. #define C7_CMD_ENC_CONF_WIN_TOP_BOT (C7_REG_BASE + 0x188)
  133. #define C7_CMD_ENC_CONF_WIN_LEFT_RIGHT (C7_REG_BASE + 0x18C)
  134. #define C7_CMD_ENC_PIC_QS (C7_REG_BASE + 0x198)
  135. #define C7_RET_ENC_PIC_FRAME_IDX (C7_REG_BASE + 0x1A0) // reconstructed frame index
  136. #define C7_RET_ENC_PIC_SLICE_NUM (C7_REG_BASE + 0x1A4)
  137. #define C7_RET_ENC_PIC_NUM (C7_REG_BASE + 0x1D8)
  138. #define C7_RET_ENC_PIC_TYPE (C7_REG_BASE + 0x1DC)
  139. #define C7_RET_ENC_PIC_FLAG (C7_REG_BASE + 0x1E0)