coda7q.c 60 KB

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  1. // SPDX-License-Identifier: LGPL-2.1 OR BSD-3-Clause
  2. #include "product.h"
  3. #include "wave/common/common.h"
  4. #include "wave/common/common_vpuconfig.h"
  5. #include "wave/common/common_regdefine.h"
  6. #include "wave/coda7q/coda7q.h"
  7. #include "vpuerror.h"
  8. #include "wave/coda7q/coda7q_regdefine.h"
  9. #define CODA7Q_DEFAULT_TEMPBUF_SIZE 1024*1024
  10. #define CODA7Q_TEMPBUF_OFFSET 1024*1024
  11. #define OPT_ENC_PIC (1)
  12. #define OPT_HEADER_ENC (1<<16)
  13. static RetCode Coda7qPrepareDecodingPicture(CodecInst* instance, Uint32 cmd)
  14. {
  15. Int32 coreIdx;
  16. Uint32 regVal = 0, bsParam, bsOption;
  17. DecInfo* pDecInfo;
  18. DecOpenParam* pOpenParam;
  19. vpu_buffer_t vb;
  20. coreIdx = instance->coreIdx;
  21. pDecInfo = VPU_HANDLE_TO_DECINFO(instance);
  22. pOpenParam = &pDecInfo->openParam;
  23. /* Set attributes of bitstream buffer controller */
  24. bsParam = bsOption = 0;
  25. regVal = 0;
  26. switch (pOpenParam->bitstreamMode) {
  27. case BS_MODE_INTERRUPT:
  28. bsParam = BSPARAM_ENABLE_RINGBUFFER;
  29. break;
  30. case BS_MODE_PIC_END:
  31. bsOption = BSOPTION_ENABLE_EXPLICIT_END;
  32. break;
  33. default:
  34. return RETCODE_INVALID_PARAM;
  35. }
  36. regVal = vdi_convert_endian(coreIdx, pOpenParam->streamEndian);
  37. bsParam |= (regVal&VDI_128BIT_ENDIAN_MASK);
  38. VpuWriteReg(coreIdx, W4_BS_PARAM, bsParam);
  39. VpuWriteReg(coreIdx, W4_BS_START_ADDR, pDecInfo->streamBufStartAddr);
  40. VpuWriteReg(coreIdx, W4_BS_SIZE, pDecInfo->streamBufSize);
  41. VpuWriteReg(coreIdx, W4_BS_RD_PTR, pDecInfo->streamRdPtr);
  42. VpuWriteReg(coreIdx, W4_BS_WR_PTR, pDecInfo->streamWrPtr);
  43. if (pDecInfo->streamEndflag == 1)
  44. bsOption = 3;
  45. VpuWriteReg(coreIdx, W4_BS_OPTION, bsOption);
  46. /* Secondary AXI */
  47. vdi_get_sram_memory(coreIdx, &vb);
  48. VpuWriteReg(coreIdx, W4_ADDR_SEC_AXI, vb.phys_addr);
  49. VpuWriteReg(coreIdx, W4_SEC_AXI_SIZE, pDecInfo->secAxiInfo.bufSize);
  50. if (instance->codecMode == C7_HEVC_DEC) {
  51. regVal = (pDecInfo->secAxiInfo.u.wave4.useBitEnable<<0) |
  52. (pDecInfo->secAxiInfo.u.wave4.useIpEnable<<9) |
  53. (pDecInfo->secAxiInfo.u.wave4.useLfRowEnable<<15);
  54. }
  55. else {
  56. regVal = ((pDecInfo->secAxiInfo.u.coda9.useBitEnable&0x01) <<0 |
  57. (pDecInfo->secAxiInfo.u.coda9.useIpEnable&0x01) <<1 |
  58. (pDecInfo->secAxiInfo.u.coda9.useDbkYEnable&0x01) <<2 |
  59. (pDecInfo->secAxiInfo.u.coda9.useDbkCEnable&0x01) <<3 |
  60. (pDecInfo->secAxiInfo.u.coda9.useOvlEnable&0x01) <<4 |
  61. (pDecInfo->secAxiInfo.u.coda9.useBitEnable&0x01) <<8 |
  62. (pDecInfo->secAxiInfo.u.coda9.useIpEnable&0x01) <<9 |
  63. (pDecInfo->secAxiInfo.u.coda9.useDbkYEnable&0x01) <<10 |
  64. (pDecInfo->secAxiInfo.u.coda9.useDbkCEnable&0x01) <<11 |
  65. (pDecInfo->secAxiInfo.u.coda9.useOvlEnable&0x01) <<12 );
  66. }
  67. VpuWriteReg(coreIdx, W4_USE_SEC_AXI, regVal);
  68. /* Set up work-buffer */
  69. VpuWriteReg(coreIdx, W4_ADDR_WORK_BASE, pDecInfo->vbWork.phys_addr);
  70. VpuWriteReg(coreIdx, W4_WORK_SIZE, pDecInfo->vbWork.size);
  71. VpuWriteReg(coreIdx, W4_WORK_PARAM, 0);
  72. /* Set up temp-buffer */
  73. VpuWriteReg(coreIdx, W4_ADDR_TEMP_BASE, pDecInfo->vbTemp.phys_addr);
  74. VpuWriteReg(coreIdx, W4_TEMP_SIZE, pDecInfo->vbTemp.size);
  75. VpuWriteReg(coreIdx, W4_TEMP_PARAM, 0);
  76. {
  77. PhysicalAddress addr;
  78. Uint32 size;
  79. addr = pDecInfo->userDataBufAddr;
  80. size = pDecInfo->userDataBufSize;
  81. if (pDecInfo->userDataEnable == FALSE) {
  82. addr = 0L;
  83. size = 0L;
  84. }
  85. /* Set attributes of User buffer */
  86. VpuWriteReg(coreIdx, W4_CMD_DEC_ADDR_USER_BASE, addr);
  87. VpuWriteReg(coreIdx, W4_CMD_DEC_USER_SIZE, size);
  88. VpuWriteReg(coreIdx, W4_CMD_DEC_USER_PARAM, VDI_128BIT_LITTLE_ENDIAN&VDI_128BIT_ENDIAN_MASK);
  89. /** Configure CU data report */
  90. addr = pDecInfo->cuDataBufAddr;
  91. size = pDecInfo->cuDataBufSize;
  92. if (pDecInfo->cuDataEnable == FALSE) {
  93. addr = 0L;
  94. size = 0L;
  95. }
  96. VpuWriteReg(coreIdx, W4_CMD_DEC_ADDR_REPORT_BASE, addr);
  97. VpuWriteReg(coreIdx, W4_CMD_DEC_REPORT_SIZE, size);
  98. VpuWriteReg(coreIdx, W4_CMD_DEC_REPORT_PARAM, (pDecInfo->cuDataEnable<<31 | (VDI_128BIT_LE_WORD_BYTE_SWAP&VDI_128BIT_ENDIAN_MASK)));
  99. }
  100. return RETCODE_SUCCESS;
  101. }
  102. static void Coda7qGetSequenceInformation(CodecInst* instance, DecInitialInfo* info)
  103. {
  104. DecInfo* pDecInfo = &instance->CodecInfo->decInfo;
  105. Uint32 regVal;
  106. Uint32 left, right, top, bottom;
  107. Uint32 profileCompatibilityFlag;
  108. info->rdPtr = VpuReadReg(instance->coreIdx, W4_BS_RD_PTR);
  109. info->wrPtr = VpuReadReg(instance->coreIdx, W4_BS_WR_PTR);
  110. pDecInfo->streamRdPtr = VpuReadReg(instance->coreIdx, pDecInfo->streamRdPtrRegAddr);
  111. pDecInfo->frameDisplayFlag = VpuReadReg(instance->coreIdx, pDecInfo->frameDisplayFlagRegAddr);
  112. regVal = VpuReadReg(instance->coreIdx, W4_BS_OPTION);
  113. pDecInfo->streamEndflag = (regVal&0x02) ? TRUE : FALSE;
  114. regVal = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_SIZE);
  115. info->picWidth = ( (regVal >> 16) & 0xffff );
  116. info->picHeight = ( regVal & 0xffff );
  117. if (instance->codecMode == C7_HEVC_DEC) {
  118. regVal = VpuReadReg(instance->coreIdx, C7_RET_DEC_CROP_LEFT_RIGHT);
  119. left = (regVal >> 16) & 0xffff;
  120. right = regVal & 0xffff;
  121. regVal = VpuReadReg(instance->coreIdx, C7_RET_DEC_CROP_TOP_BOTTOM);
  122. top = (regVal >> 16) & 0xffff;
  123. bottom = regVal & 0xffff;
  124. info->picCropRect.left = left;
  125. info->picCropRect.right = info->picWidth - right;
  126. info->picCropRect.top = top;
  127. info->picCropRect.bottom = info->picHeight - bottom;
  128. info->minFrameBufferCount = VpuReadReg(instance->coreIdx, C7_RET_DEC_FRAMEBUF_NEEDED);
  129. info->frameBufDelay = VpuReadReg(instance->coreIdx, C7_RET_DEC_NUM_REORDER_DELAY);
  130. regVal = VpuReadReg(instance->coreIdx, C7_RET_DEC_SEQ_PARAM);
  131. profileCompatibilityFlag = (regVal>>12)&0xff;
  132. info->profile = (regVal >> 24)&0x1f;
  133. info->level = regVal & 0xff;
  134. info->tier = (regVal >> 29)&0x01;
  135. info->maxSubLayers = (regVal >> 21)&0x07;
  136. info->fRateNumerator = VpuReadReg(instance->coreIdx, C7_RET_DEC_FRAME_RATE_NR);
  137. info->fRateDenominator = VpuReadReg(instance->coreIdx, C7_RET_DEC_FRAME_RATE_DR);
  138. regVal = VpuReadReg(instance->coreIdx, C7_RET_DEC_COLOR_SAMPLE_INFO);
  139. info->chromaFormatIDC = (regVal>>8)&0x0f;
  140. info->lumaBitdepth = (regVal>>0)&0x0f;
  141. info->chromaBitdepth = (regVal>>4)&0x0f;
  142. info->aspectRateInfo = (regVal>>16)&0xff;
  143. info->isExtSAR = (info->aspectRateInfo == 255 ? TRUE : FALSE);
  144. if (info->isExtSAR == TRUE) {
  145. info->aspectRateInfo = VpuReadReg(instance->coreIdx, C7_RET_DEC_ASPECT_RATIO); /* [0:15] - vertical size, [16:31] - horizontal size */
  146. }
  147. info->bitRate = VpuReadReg(instance->coreIdx, C7_RET_DEC_BIT_RATE);
  148. /* Guessing Profile */
  149. if (info->profile == 0) {
  150. if ((profileCompatibilityFlag&0x06) == 0x06) info->profile = 1; /* Main profile */
  151. else if ((profileCompatibilityFlag&0x04) == 0x04) info->profile = 2; /* Main10 profile */
  152. else if ((profileCompatibilityFlag&0x08) == 0x08) info->profile = 3; /* Main Still Picture profile */
  153. else info->profile = 1; /* For old version HM */
  154. }
  155. }
  156. else {
  157. //---------------------------------------------------
  158. // for Legacy codecs
  159. //---------------------------------------------------
  160. info->lumaBitdepth = 8;
  161. info->chromaBitdepth = 8;
  162. if (instance->codecMode == C7_AVC_DEC) {
  163. info->numReorderFrames = VpuReadReg(instance->coreIdx, C7_RET_DEC_SEQ_VUI_INFO);
  164. regVal = VpuReadReg(instance->coreIdx, C7_RET_DEC_CROP_LEFT_RIGHT);
  165. left = (regVal >> 16) & 0xffff;
  166. right = regVal & 0xffff;
  167. regVal = VpuReadReg(instance->coreIdx, C7_RET_DEC_CROP_TOP_BOTTOM);
  168. top = (regVal >> 16) & 0xffff;
  169. bottom = regVal & 0xffff;
  170. info->picCropRect.left = left;
  171. info->picCropRect.right = info->picWidth - right;
  172. info->picCropRect.top = top;
  173. info->picCropRect.bottom = info->picHeight - bottom;
  174. }
  175. info->aspectRateInfo = VpuReadReg(instance->coreIdx, C7_RET_DEC_ASPECT_RATIO);
  176. info->fRateNumerator = VpuReadReg(instance->coreIdx, C7_RET_DEC_FRAME_RATE_NR);
  177. info->fRateDenominator = VpuReadReg(instance->coreIdx, C7_RET_DEC_FRAME_RATE_DR);
  178. if (instance->codecMode == C7_VP8_DEC && instance->codecModeAux == VPX_AUX_VP8) {
  179. regVal = VpuReadReg(instance->coreIdx, C7_RET_DEC_SEQ_VP8_SCALE_INFO);
  180. info->vp8ScaleInfo.hScaleFactor = (regVal >> 30) & 0x03;
  181. info->vp8ScaleInfo.vScaleFactor = (regVal >> 28) & 0x03;
  182. info->vp8ScaleInfo.picWidth = (regVal >> 14) & 0x3FFF;
  183. info->vp8ScaleInfo.picHeight = (regVal >> 0) & 0x3FFF;
  184. }
  185. }
  186. }
  187. RetCode Coda7qVpuDecInitSeq(CodecInst* instance)
  188. {
  189. RetCode ret;
  190. DecInfo* pDecInfo;
  191. Uint32 cmdOption = INIT_SEQ_NORMAL;
  192. Uint32 val;
  193. vpu_buffer_t vb;
  194. if (instance == NULL)
  195. return RETCODE_INVALID_PARAM;
  196. pDecInfo = VPU_HANDLE_TO_DECINFO(instance);
  197. vdi_get_common_memory(instance->coreIdx, &vb);
  198. pDecInfo->vbTemp.phys_addr = vb.phys_addr + CODA7Q_TEMPBUF_OFFSET;
  199. pDecInfo->vbTemp.virt_addr = vb.virt_addr + CODA7Q_TEMPBUF_OFFSET;
  200. pDecInfo->vbTemp.size = CODA7Q_DEFAULT_TEMPBUF_SIZE;
  201. if (pDecInfo->thumbnailMode)
  202. cmdOption = INIT_SEQ_W_THUMBNAIL;
  203. if ((ret=Coda7qPrepareDecodingPicture(instance, DEC_PIC_HDR)) != RETCODE_SUCCESS) {
  204. return ret;
  205. }
  206. if (instance->codecMode == C7_HEVC_DEC) {
  207. VpuWriteReg(instance->coreIdx, C7_CMD_DEC_USER_DATA_MASK, 0xFFFFFFFF); // fix me.
  208. VpuWriteReg(instance->coreIdx, C7_CMD_DEC_SEVERITY_LEVEL, 0);
  209. VpuWriteReg(instance->coreIdx, C7_CMD_DEC_FORCE_FB_LATENCY_PLUS1, 0);
  210. }
  211. else { // for Legacy codecs
  212. if (pDecInfo->userDataEnable) {
  213. VpuWriteReg(instance->coreIdx, C7_CMD_DEC_SEQ_USER_DATA_OPTION, (pDecInfo->userDataReportMode << 10) | (pDecInfo->userDataEnable << 5));
  214. VpuWriteReg(instance->coreIdx, W4_CMD_DEC_ADDR_USER_BASE, pDecInfo->userDataBufAddr);
  215. VpuWriteReg(instance->coreIdx, W4_CMD_DEC_USER_SIZE, pDecInfo->userDataBufSize);
  216. }
  217. else {
  218. VpuWriteReg(instance->coreIdx, C7_CMD_DEC_SEQ_USER_DATA_OPTION, 0);
  219. VpuWriteReg(instance->coreIdx, W4_CMD_DEC_ADDR_USER_BASE, 0);
  220. VpuWriteReg(instance->coreIdx, W4_CMD_DEC_USER_SIZE, 0);
  221. }
  222. // set reorderEnable && DeblkEnable flag
  223. val = 0;
  224. if (pDecInfo->openParam.bitstreamMode == BS_MODE_PIC_END) {
  225. val |= (1 << 3) & 0x8;
  226. val |= (1 << 2) & 0x4;
  227. }
  228. if (!pDecInfo->lowDelayInfo.lowDelayEn) {
  229. val |= (pDecInfo->reorderEnable<<1) & 0x2;
  230. }
  231. val |= (pDecInfo->openParam.mp4DeblkEnable & 0x1);
  232. VpuWriteReg(instance->coreIdx, C7_CMD_DEC_SEQ_OPTION, val);
  233. // removed CMD_DEC_SEQ_START_BYTE setting.
  234. if (instance->codecMode == C7_DV3_DEC)
  235. VpuWriteReg(instance->coreIdx, C7_CMD_DEC_SEQ_SRC_SIZE, (pDecInfo->div3Width<<16) | (pDecInfo->div3Height));
  236. switch (instance->codecMode) {
  237. case C7_MP4_DEC:
  238. VpuWriteReg(instance->coreIdx, C7_CMD_DEC_SEQ_MP4_ASP_CLASS, (CODA7Q_VPU_GMC_PROCESS_METHOD<<3)|pDecInfo->openParam.mp4Class);
  239. break;
  240. case C7_VC1_DEC:
  241. VpuWriteReg(instance->coreIdx, C7_CMD_DEC_SEQ_VC1_STREAM_FMT, (0 << 3) & 0x08);
  242. break;
  243. case C7_AVC_DEC:
  244. VpuWriteReg(instance->coreIdx, C7_CMD_DEC_SEQ_X264_MV_EN, CODA7Q_VPU_AVC_X264_SUPPORT);
  245. break;
  246. }
  247. }
  248. VpuWriteReg(instance->coreIdx, W4_CMD_DEC_DISP_FLAG, 0);
  249. VpuWriteReg(instance->coreIdx, W4_COMMAND_OPTION, cmdOption); /* INIT_SEQ */
  250. Wave4BitIssueCommand(instance, DEC_PIC_HDR);
  251. return RETCODE_SUCCESS;
  252. }
  253. RetCode Coda7qVpuDecode(CodecInst* instance, DecParam* option)
  254. {
  255. RetCode ret;
  256. Uint32 modeOption = DEC_PIC_NORMAL;
  257. Int32 forceLatency = -1;
  258. if (instance->CodecInfo->decInfo.thumbnailMode)
  259. modeOption = DEC_PIC_W_THUMBNAIL;
  260. else if (option->skipframeMode)
  261. {
  262. switch (option->skipframeMode) {
  263. case 1:
  264. modeOption = SKIP_NON_IRAP;
  265. forceLatency = 0;
  266. break;
  267. case 3:
  268. modeOption = SKIP_NON_REF_PIC;
  269. break;
  270. default:
  271. break;
  272. }
  273. }
  274. if ((ret=Coda7qPrepareDecodingPicture(instance, DEC_PIC)) != RETCODE_SUCCESS) {
  275. return ret;
  276. }
  277. if (instance->codecMode == C7_HEVC_DEC) {
  278. VpuWriteReg(instance->coreIdx, C7_CMD_DEC_USER_DATA_MASK, 0xFFFFFFFF); // fix me.
  279. VpuWriteReg(instance->coreIdx, C7_CMD_DEC_TEMPORAL_ID, 7);
  280. VpuWriteReg(instance->coreIdx, C7_CMD_DEC_FORCE_FB_LATENCY_PLUS1, forceLatency+1);
  281. VpuWriteReg(instance->coreIdx, C7_CMD_DEC_SEVERITY_LEVEL, 0);
  282. VpuWriteReg(instance->coreIdx, C7_CMD_SEQ_CHANGE_ENABLE_FLAG, instance->CodecInfo->decInfo.seqChangeMask);
  283. }
  284. VpuWriteReg(instance->coreIdx, W4_COMMAND_OPTION, modeOption);
  285. Wave4BitIssueCommand(instance, DEC_PIC);
  286. return RETCODE_SUCCESS;
  287. }
  288. RetCode Coda7qVpuDecGetResult(CodecInst* instance, DecOutputInfo* result)
  289. {
  290. DecInfo* pDecInfo = VPU_HANDLE_TO_DECINFO(instance);
  291. int regVal, nalUnitType, index;
  292. if (instance->codecMode == C7_HEVC_DEC) {
  293. result->frameCycle = VpuReadReg(instance->coreIdx, W4_FRAME_CYCLE);
  294. result->decodingSuccess = VpuReadReg(instance->coreIdx, W4_RET_SUCCESS);
  295. result->refMissingFrameFlag = FALSE;
  296. if (result->decodingSuccess == FALSE) {
  297. result->errorReason = VpuReadReg(instance->coreIdx, W4_RET_FAIL_REASON);
  298. if (result->errorReason == WAVE4_SYSERR_WRITEPROTECTION) {
  299. return RETCODE_MEMORY_ACCESS_VIOLATION;
  300. }
  301. else if (result->errorReason == WAVE4_CODEC_ERROR) {
  302. result->errorReasonExt = VpuReadReg(instance->coreIdx, C7_RET_DEC_ERR_INFO);
  303. }
  304. if (result->errorReasonExt == WAVE4_ETCERR_MISSING_REFERENCE_PICTURE) {
  305. result->refMissingFrameFlag = TRUE;
  306. }
  307. }
  308. else {
  309. result->warnInfo = VpuReadReg(instance->coreIdx, C7_RET_DEC_WARN_INFO);
  310. }
  311. regVal = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_TYPE);
  312. if (regVal&0x04) result->picType = PIC_TYPE_B;
  313. else if (regVal&0x02) result->picType = PIC_TYPE_P;
  314. else if (regVal&0x01) result->picType = PIC_TYPE_I;
  315. else result->picType = PIC_TYPE_MAX;
  316. nalUnitType = (regVal & 0x3f0) >> 4;
  317. if ((nalUnitType == 19 || nalUnitType == 20) && result->picType == PIC_TYPE_I) {
  318. /* IDR_W_RADL, IDR_N_LP */
  319. result->picType = PIC_TYPE_IDR;
  320. }
  321. result->nalType = nalUnitType;
  322. result->ctuSize = 16<<((regVal>>10)&0x3);
  323. if (pDecInfo->openParam.wtlEnable == TRUE) {
  324. index = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_DISPLAY_IDX);
  325. result->indexFrameDisplay = (short)(index>>16 & 0xffff); // linear
  326. result->indexFrameDisplayForTiled = (short)(index&0xffff); // fbc
  327. index = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_DECODED_IDX);
  328. result->indexFrameDecoded = (short)(index>>16&0xffff);
  329. result->indexFrameDecodedForTiled = (short)(index&0xffff);
  330. } else {
  331. index = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_DISPLAY_IDX);
  332. result->indexFrameDisplay = (short)(index & 0xffff);
  333. result->indexFrameDisplayForTiled = result->indexFrameDisplay;
  334. index = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_DECODED_IDX);
  335. result->indexFrameDecoded = (short)(index&0xffff);
  336. result->indexFrameDecodedForTiled = result->indexFrameDecoded;
  337. }
  338. result->h265Info.decodedPOC = -1;
  339. result->h265Info.displayPOC = -1;
  340. if (result->indexFrameDecoded >= 0)
  341. result->h265Info.decodedPOC = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_POC);
  342. result->sequenceChanged = VpuReadReg(instance->coreIdx, C7_RET_DEC_SEQ_CHANGE_FLAG);
  343. /*
  344. * If current picture is the last of the current sequence and sequence-change flag is not 0, then
  345. * the width and height of the current picture is set to the width and height of the current sequence.
  346. */
  347. if (result->sequenceChanged == 0) {
  348. regVal = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_SIZE);
  349. result->decPicWidth = regVal>>16;
  350. result->decPicHeight = regVal&0xffff;
  351. }
  352. else {
  353. if (result->indexFrameDecoded < 0) {
  354. result->decPicWidth = 0;
  355. result->decPicHeight = 0;
  356. }
  357. else {
  358. result->decPicWidth = pDecInfo->initialInfo.picWidth;
  359. result->decPicHeight = pDecInfo->initialInfo.picHeight;
  360. }
  361. }
  362. result->numOfErrMBs = VpuReadReg(instance->coreIdx, C7_RET_DEC_ERR_CTB_NUM)>>16;
  363. result->numOfTotMBs = VpuReadReg(instance->coreIdx, C7_RET_DEC_ERR_CTB_NUM)&0xffff;
  364. result->bytePosFrameStart = VpuReadReg(instance->coreIdx, C7_RET_DEC_AU_START_POS);
  365. result->bytePosFrameEnd = VpuReadReg(instance->coreIdx, C7_RET_DEC_AU_END_POS);
  366. pDecInfo->prevFrameEndPos = result->bytePosFrameEnd;
  367. if (result->indexFrameDecodedForTiled == -1 && pDecInfo->openParam.bitstreamMode == BS_MODE_PIC_END) {
  368. result->chunkReuseRequired = 1;
  369. }
  370. result->indexFramePrescan = VpuReadReg(instance->coreIdx, C7_RET_DEC_PRESCAN_INDEX);
  371. }
  372. else {
  373. //***********************************************
  374. // for Legacy codecs
  375. //***********************************************
  376. result->frameCycle = VpuReadReg(instance->coreIdx, W4_FRAME_CYCLE);
  377. regVal = VpuReadReg(instance->coreIdx, W4_RET_SUCCESS);
  378. result->decodingSuccess = regVal;
  379. if (result->decodingSuccess == FALSE) {
  380. result->errorReason = VpuReadReg(instance->coreIdx, W4_RET_FAIL_REASON);
  381. if (result->errorReason == WAVE4_SYSERR_WRITEPROTECTION) {
  382. return RETCODE_MEMORY_ACCESS_VIOLATION;
  383. }
  384. return RETCODE_FAILURE;
  385. }
  386. if (instance->codecMode == C7_AVC_DEC) {
  387. result->notSufficientPsBuffer = (regVal >> 3) & 0x1;
  388. result->notSufficientSliceBuffer= (regVal >> 2) & 0x1;
  389. }
  390. result->chunkReuseRequired = 0;
  391. if (pDecInfo->openParam.bitstreamMode == BS_MODE_PIC_END) {
  392. if (instance->codecMode == C7_AVC_DEC) {
  393. result->chunkReuseRequired = (regVal >> 16) & 0x1;
  394. regVal = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_DECODED_IDX);
  395. if (regVal == (Uint32)-1)
  396. result->chunkReuseRequired = 1;
  397. }
  398. else if (instance->codecMode == C7_MP2_DEC) {
  399. result->chunkReuseRequired = (regVal >> 16) & 0x1;
  400. }
  401. else if (instance->codecMode == C7_MP4_DEC) {
  402. result->chunkReuseRequired = (regVal >> 16) & 0x1;
  403. }
  404. }
  405. if (pDecInfo->openParam.wtlEnable == TRUE) { // case of H.264 && MbsOnlyFlag==1
  406. index = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_DISPLAY_IDX);
  407. result->indexFrameDisplay = (short)(index>>16 & 0xffff); // linear
  408. result->indexFrameDisplayForTiled = (short)(index&0xffff); // fbc
  409. index = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_DECODED_IDX);
  410. result->indexFrameDecoded = (short)(index>>16&0xffff);
  411. result->indexFrameDecodedForTiled = (short)(index&0xffff);
  412. }
  413. else {
  414. index = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_DISPLAY_IDX);
  415. result->indexFrameDisplay = (short)(index & 0xffff);
  416. result->indexFrameDisplayForTiled = result->indexFrameDisplay;
  417. index = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_DECODED_IDX);
  418. result->indexFrameDecoded = (short)(index&0xffff);
  419. result->indexFrameDecodedForTiled = result->indexFrameDecoded;
  420. }
  421. regVal = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_SIZE);
  422. result->decPicWidth = (regVal >> 16) & 0xFFFF;
  423. result->decPicHeight= (regVal) & 0xFFFF;
  424. if (result->indexFrameDecoded >= 0 && result->indexFrameDecoded < MAX_GDI_IDX) {
  425. if (instance->codecMode == C7_VP8_DEC) {
  426. regVal = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_VP8_SCALE_INFO); // fix me (not defined yet)
  427. result->vp8ScaleInfo.hScaleFactor = (regVal >> 30) & 0x03;
  428. result->vp8ScaleInfo.vScaleFactor = (regVal >> 28) & 0x03;
  429. result->vp8ScaleInfo.picWidth = (regVal >> 14) & 0x3FFF;
  430. result->vp8ScaleInfo.picHeight = (regVal >> 0) & 0x3FFF;
  431. // ref_idx_gold[31:24], ref_idx_altr[23:16], ref_idx_last[15: 8],
  432. // version_number[3:1], show_frame[0]
  433. regVal = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_VP8_PIC_REPORT);
  434. result->vp8PicInfo.refIdxGold = (regVal >> 24) & 0x0FF;
  435. result->vp8PicInfo.refIdxAltr = (regVal >> 16) & 0x0FF;
  436. result->vp8PicInfo.refIdxLast = (regVal >> 8) & 0x0FF;
  437. result->vp8PicInfo.versionNumber = (regVal >> 1) & 0x07;
  438. result->vp8PicInfo.showFrame = (regVal >> 0) & 0x01;
  439. }
  440. }
  441. regVal = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_TYPE);
  442. result->interlacedFrame = (regVal >> 18) & 0x1;
  443. result->topFieldFirst = (regVal >> 21) & 0x1;
  444. if (result->interlacedFrame) {
  445. if (instance->codecMode == C7_VC1_DEC) {
  446. result->picTypeFirst = (regVal >> 3) & 0x3;
  447. result->picType = regVal & 0x3; // pic_type of 2nd field
  448. }
  449. else {
  450. index = (regVal >> 2) & 0x7; // pic_type of 1st field
  451. if (index & 0x1) {
  452. result->picTypeFirst = PIC_TYPE_I;
  453. }
  454. if (index & 0x2) {
  455. result->picTypeFirst = PIC_TYPE_P;
  456. }
  457. if (index & 0x4) {
  458. result->picTypeFirst = PIC_TYPE_B;
  459. }
  460. index = (regVal >> 5) & 0x7; // pic_type of 2nd field
  461. if (index & 0x1) {
  462. result->picType = PIC_TYPE_I;
  463. }
  464. if (index & 0x2) {
  465. result->picType = PIC_TYPE_P;
  466. }
  467. if (index & 0x4) {
  468. result->picType = PIC_TYPE_B;
  469. }
  470. }
  471. if (result->topFieldFirst) {
  472. result->picType = result->picTypeFirst;
  473. }
  474. }
  475. else {
  476. result->picTypeFirst = PIC_TYPE_MAX;
  477. if (instance->codecMode == C7_VC1_DEC)
  478. result->picType = (regVal >> 3) & 0x3;
  479. else
  480. result->picType = regVal & 0x3;
  481. }
  482. result->pictureStructure = (regVal >> 19) & 0x3;
  483. result->repeatFirstField = (regVal >> 22) & 0x1;
  484. result->progressiveFrame = (regVal >> 23) & 0x3;
  485. if (instance->codecMode == C7_AVC_DEC) {
  486. result->nalRefIdc = (regVal >> 7) & 0x3;
  487. result->picStrPresent = (regVal >> 27) & 0x1;
  488. result->picTimingStruct = (regVal >> 28) & 0xF;
  489. result->decFrameInfo = (regVal >> 15) & 0x1;
  490. result->avcNpfFieldInfo = (regVal >> 16) & 0x3;
  491. regVal = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_HRD_INFO);
  492. result->avcHrdInfo.cpbMinus1 = regVal >> 2;
  493. result->avcHrdInfo.vclHrdParamFlag = (regVal>> 1)&1;
  494. result->avcHrdInfo.nalHrdParamFlag = regVal & 1;
  495. regVal = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_VUI_INFO);
  496. result->avcVuiInfo.fixedFrameRateFlag = regVal &1;
  497. result->avcVuiInfo.timingInfoPresent = (regVal >> 1) & 0x01;
  498. result->avcVuiInfo.chromaLocBotField = (regVal >> 2) & 0x07;
  499. result->avcVuiInfo.chromaLocTopField = (regVal >> 5) & 0x07;
  500. result->avcVuiInfo.chromaLocInfoPresent = (regVal >> 8) & 0x01;
  501. result->avcVuiInfo.colorPrimaries = (regVal >> 16) & 0xFF;
  502. result->avcVuiInfo.colorDescPresent = (regVal >> 24) & 0x01;
  503. result->avcVuiInfo.isExtSAR = (regVal >> 25) & 0x01;
  504. result->avcVuiInfo.vidFullRange = (regVal >> 26) & 0x01;
  505. result->avcVuiInfo.vidFormat = (regVal >> 27) & 0x07;
  506. result->avcVuiInfo.vidSigTypePresent = (regVal >> 30) & 0x01;
  507. result->avcVuiInfo.vuiParamPresent = (regVal >> 31) & 0x01;
  508. regVal = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_VUI_PIC_STRUCT);
  509. result->avcVuiInfo.vuiPicStructPresent = regVal & 0x1;
  510. result->avcVuiInfo.vuiPicStruct = regVal >> 1;
  511. }
  512. if (instance->codecMode == C7_MP2_DEC) {
  513. result->fieldSequence = (regVal >> 25) & 0x7;
  514. result->frameDct = (regVal >> 28) & 0x1;
  515. result->progressiveSequence = (regVal >> 29) & 0x1;
  516. result->decFrameInfo = (regVal >> 16) & 0x3;
  517. if (result->indexFrameDisplay >= 0) {
  518. if (result->indexFrameDisplay == result->indexFrameDecoded) {
  519. result->mp2NpfFieldInfo = result->decFrameInfo;
  520. }
  521. else {
  522. result->mp2NpfFieldInfo = pDecInfo->decOutInfo[result->indexFrameDisplay].decFrameInfo;
  523. }
  524. }
  525. }
  526. if (instance->codecMode == C7_VC1_DEC) {
  527. result->decFrameInfo = (regVal >> 16) & 0x3;
  528. if (result->indexFrameDisplay >= 0) {
  529. if (result->indexFrameDisplay == result->indexFrameDecoded) {
  530. result->vc1NpfFieldInfo = result->decFrameInfo;
  531. }
  532. else {
  533. result->vc1NpfFieldInfo = pDecInfo->decOutInfo[result->indexFrameDisplay].decFrameInfo;
  534. }
  535. }
  536. }
  537. if (instance->codecMode == C7_AVC_DEC) {
  538. result->fRateNumerator = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_FRAME_NR);
  539. result->fRateDenominator = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_FRAME_DR);
  540. if (result->fRateDenominator > 0) {
  541. result->fRateDenominator *= 2;
  542. }
  543. }
  544. else {
  545. //regVal = VpuReadReg(pCodecInst->coreIdx, C7_RET_DEC_PIC_SRC_F_RATE); // fix me (not defined yet)
  546. result->fRateNumerator = (regVal & 0xffff);
  547. result->fRateDenominator = (regVal==0)?0:((regVal >> 16) + 1) & 0xffff;
  548. }
  549. if (instance->codecMode == C7_RVX_DEC) {
  550. result->rvTr = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_RV_TR);
  551. result->rvTrB = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_RV_TR_BFRAME);
  552. }
  553. if (instance->codecMode == C7_VP8_DEC) {
  554. result->aspectRateInfo = 0;
  555. }
  556. else {
  557. result->aspectRateInfo = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_ASPECT);
  558. }
  559. //*******************************************
  560. // user data reporting
  561. //*******************************************
  562. if (pDecInfo->userDataEnable == TRUE) {
  563. Uint32 userDataNum;
  564. Uint32 userDataSize;
  565. BYTE tempBuf[8] = {0,};
  566. VpuReadMem(instance->coreIdx, pDecInfo->userDataBufAddr + 0, tempBuf, 8, VPU_USER_DATA_ENDIAN);
  567. regVal = ((tempBuf[0]<<24) & 0xFF000000) |
  568. ((tempBuf[1]<<16) & 0x00FF0000) |
  569. ((tempBuf[2]<< 8) & 0x0000FF00) |
  570. ((tempBuf[3]<< 0) & 0x000000FF);
  571. userDataNum = (regVal >> 16) & 0xFFFF;
  572. userDataSize = (regVal >> 0) & 0xFFFF;
  573. if (userDataNum == 0) {
  574. userDataSize = 0;
  575. }
  576. result->decOutputExtData.userDataNum = userDataNum;
  577. result->decOutputExtData.userDataSize = userDataSize;
  578. regVal = ((tempBuf[4]<<24) & 0xFF000000) |
  579. ((tempBuf[5]<<16) & 0x00FF0000) |
  580. ((tempBuf[6]<< 8) & 0x0000FF00) |
  581. ((tempBuf[7]<< 0) & 0x000000FF);
  582. if (userDataNum == 0) {
  583. result->decOutputExtData.userDataBufFull = 0;
  584. }
  585. else {
  586. result->decOutputExtData.userDataBufFull = (regVal >> 16) & 0xFFFF;
  587. }
  588. }
  589. result->numOfErrMBs = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_ERR_MB);
  590. if (instance->codecMode == C7_VC1_DEC && result->indexFrameDisplay != -3) {
  591. if (pDecInfo->vc1BframeDisplayValid == 0) {
  592. if (result->picType == 2) {
  593. result->indexFrameDisplay = -3;
  594. }
  595. else {
  596. pDecInfo->vc1BframeDisplayValid = 1;
  597. }
  598. }
  599. }
  600. if (instance->codecMode == C7_AVC_DEC && instance->codecModeAux == AVC_AUX_MVC) {
  601. regVal = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_MVC_REPORT);
  602. result->mvcPicInfo.viewIdxDisplay = (regVal >> 0) & 0x1;
  603. result->mvcPicInfo.viewIdxDecoded = (regVal >> 1) & 0x1;
  604. }
  605. if (instance->codecMode == C7_AVC_DEC) {
  606. regVal = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_AVC_FPA_SEI0);
  607. if (regVal < 0) {
  608. result->avcFpaSei.exist = 0;
  609. }
  610. else {
  611. result->avcFpaSei.exist = 1;
  612. result->avcFpaSei.framePackingArrangementId = regVal;
  613. regVal = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_AVC_FPA_SEI1);
  614. result->avcFpaSei.contentInterpretationType = regVal&0x3F; // [5:0]
  615. result->avcFpaSei.framePackingArrangementType = (regVal >> 6)&0x7F; // [12:6]
  616. result->avcFpaSei.framePackingArrangementExtensionFlag = (regVal >> 13)&0x01; // [13]
  617. result->avcFpaSei.frame1SelfContainedFlag = (regVal >> 14)&0x01; // [14]
  618. result->avcFpaSei.frame0SelfContainedFlag = (regVal >> 15)&0x01; // [15]
  619. result->avcFpaSei.currentFrameIsFrame0Flag = (regVal >> 16)&0x01; // [16]
  620. result->avcFpaSei.fieldViewsFlag = (regVal >> 17)&0x01; // [17]
  621. result->avcFpaSei.frame0FlippedFlag = (regVal >> 18)&0x01; // [18]
  622. result->avcFpaSei.spatialFlippingFlag = (regVal >> 19)&0x01; // [19]
  623. result->avcFpaSei.quincunxSamplingFlag = (regVal >> 20)&0x01; // [20]
  624. result->avcFpaSei.framePackingArrangementCancelFlag = (regVal >> 21)&0x01; // [21]
  625. regVal = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_AVC_FPA_SEI2);
  626. result->avcFpaSei.framePackingArrangementRepetitionPeriod = regVal&0x7FFF; // [14:0]
  627. result->avcFpaSei.frame1GridPositionY = (regVal >> 16)&0x0F; // [19:16]
  628. result->avcFpaSei.frame1GridPositionX = (regVal >> 20)&0x0F; // [23:20]
  629. result->avcFpaSei.frame0GridPositionY = (regVal >> 24)&0x0F; // [27:24]
  630. result->avcFpaSei.frame0GridPositionX = (regVal >> 28)&0x0F; // [31:28]
  631. }
  632. regVal = VpuReadReg(instance->coreIdx, C7_RET_DEC_PIC_POC);
  633. result->avcPocTop = regVal & 0x3FF;
  634. result->avcPocBot = (regVal >> 10) & 0x3FF;
  635. if (result->interlacedFrame) {
  636. if (result->avcPocTop > result->avcPocBot) {
  637. result->avcPocPic = result->avcPocBot;
  638. }
  639. else {
  640. result->avcPocPic = result->avcPocTop;
  641. }
  642. }
  643. else {
  644. result->avcPocPic = result->avcPocTop;
  645. }
  646. }
  647. #ifdef SUPPORT_REF_FLAG_REPORT
  648. // regVal = VpuReadReg(pCodecInst->coreIdx, BIT_FRM_REF_FLG); // fix me (not defined yet)
  649. for (index = 0; index < MAX_GDI_IDX; index++) {
  650. result->frameReferenceFlag[index] = ((regVal>>index)&0x01);
  651. }
  652. #endif
  653. }
  654. Coda7qGetSequenceInformation(instance, &pDecInfo->initialInfo);
  655. return RETCODE_SUCCESS;
  656. }
  657. RetCode Coda7qVpuDecGetSeqInfo(CodecInst* pCodecInst, DecInitialInfo* info)
  658. {
  659. DecInfo* pDecInfo = &pCodecInst->CodecInfo->decInfo;
  660. Uint32 regVal;
  661. if (pDecInfo->openParam.bitstreamMode == BS_MODE_INTERRUPT && pDecInfo->seqInitEscape) {
  662. pDecInfo->seqInitEscape = 0;
  663. /* NOTE: Not implemented yet */
  664. return RETCODE_NOT_SUPPORTED_FEATURE;
  665. }
  666. Coda7qGetSequenceInformation(pCodecInst, info);
  667. if (pCodecInst->codecMode != C7_HEVC_DEC) {
  668. info->minFrameBufferCount = VpuReadReg(pCodecInst->coreIdx, C7_RET_DEC_FRAMEBUF_NEEDED);
  669. info->frameBufDelay = VpuReadReg(pCodecInst->coreIdx, C7_RET_DEC_NUM_REORDER_DELAY);
  670. regVal = VpuReadReg(pCodecInst->coreIdx, C7_RET_DEC_SEQ_HEADER_REPORT);
  671. info->profile = (regVal >> 0) & 0xFF;
  672. info->level = (regVal >> 8) & 0xFF;
  673. info->interlace = !((regVal >> 16) & 0x01);
  674. info->direct8x8Flag = (regVal >> 17) & 0x01;
  675. info->vc1Psf = (regVal >> 18) & 0x01;
  676. info->constraint_set_flag[0] = (regVal >> 19) & 0x01;
  677. info->constraint_set_flag[1] = (regVal >> 20) & 0x01;
  678. info->constraint_set_flag[2] = (regVal >> 21) & 0x01;
  679. info->constraint_set_flag[3] = (regVal >> 22) & 0x01;
  680. info->chromaFormatIDC = (regVal >> 23) & 0x03;
  681. info->isExtSAR = (regVal >> 25) & 0x01;
  682. info->maxNumRefFrm = (regVal >> 27) & 0x0f;
  683. info->maxNumRefFrmFlag = (regVal >> 31) & 0x01;
  684. info->bitRate = VpuReadReg(pCodecInst->coreIdx, C7_RET_DEC_BIT_RATE);
  685. if (pCodecInst->codecMode == C7_MP4_DEC) {
  686. regVal = VpuReadReg(pCodecInst->coreIdx, C7_RET_DEC_SEQ_INFO);
  687. info->mp4ShortVideoHeader = (regVal >> 2) & 1;
  688. info->mp4DataPartitionEnable = (regVal >> 0) & 1;
  689. info->mp4ReversibleVlcEnable = info->mp4DataPartitionEnable ? ((regVal>>1) & 1) : 0;
  690. info->h263AnnexJEnable = (regVal >> 3) & 1;
  691. }
  692. }
  693. info->warnInfo = 0;
  694. regVal = VpuReadReg(pCodecInst->coreIdx, W4_RET_SUCCESS);
  695. if (regVal == FALSE) {
  696. info->seqInitErrReason = VpuReadReg(pCodecInst->coreIdx, W4_RET_FAIL_REASON);
  697. if (info->seqInitErrReason == WAVE4_SYSERR_WRITEPROTECTION)
  698. return RETCODE_MEMORY_ACCESS_VIOLATION;
  699. else if (info->seqInitErrReason == 1) {
  700. info->seqInitErrReason = VpuReadReg(pCodecInst->coreIdx, C7_RET_DEC_ERR_INFO);
  701. }
  702. return RETCODE_FAILURE;
  703. }
  704. else {
  705. info->warnInfo = VpuReadReg(pCodecInst->coreIdx, C7_RET_DEC_WARN_INFO);
  706. }
  707. return RETCODE_SUCCESS;
  708. }
  709. extern RetCode Coda7qVpuEncSetup(CodecInst* instance)
  710. {
  711. Int32 picWidth, picHeight, int_reason;
  712. Int32 data;
  713. Uint32 regVal = 0, rotMirMode;
  714. EncInfo* pEncInfo = &instance->CodecInfo->encInfo;
  715. rotMirMode = 0;
  716. if (pEncInfo->rotationEnable == TRUE) {
  717. switch (pEncInfo->rotationAngle) {
  718. case 0:
  719. rotMirMode |= 0x0;
  720. break;
  721. case 90:
  722. rotMirMode |= 0x1;
  723. break;
  724. case 180:
  725. rotMirMode |= 0x2;
  726. break;
  727. case 270:
  728. rotMirMode |= 0x3;
  729. break;
  730. }
  731. }
  732. if (pEncInfo->mirrorEnable == TRUE) {
  733. switch (pEncInfo->mirrorDirection) {
  734. case MIRDIR_NONE :
  735. rotMirMode |= 0x0;
  736. break;
  737. case MIRDIR_VER :
  738. rotMirMode |= 0x4;
  739. break;
  740. case MIRDIR_HOR :
  741. rotMirMode |= 0x8;
  742. break;
  743. case MIRDIR_HOR_VER :
  744. rotMirMode |= 0xC;
  745. break;
  746. }
  747. }
  748. switch(pEncInfo->openParam.srcFormat) { // FIX ME. (don't know exactly how srcFormat is set including cbcrInterleave, nv21 options)
  749. case FORMAT_420: regVal = 0; break;
  750. case FORMAT_422: regVal = 1; break;
  751. case FORMAT_YUYV: regVal = 2; break;
  752. case FORMAT_UYVY: regVal = 3; break;
  753. }
  754. rotMirMode |= (regVal<<5);
  755. picWidth = pEncInfo->openParam.picWidth;
  756. picHeight = pEncInfo->openParam.picHeight;
  757. VpuWriteReg(instance->coreIdx, C7_CMD_ENC_ROT_PARAM, rotMirMode);
  758. /* Set up work-buffer */
  759. VpuWriteReg(instance->coreIdx, W4_ADDR_WORK_BASE, pEncInfo->vbWork.phys_addr);
  760. VpuWriteReg(instance->coreIdx, W4_WORK_SIZE, pEncInfo->vbWork.size);
  761. VpuWriteReg(instance->coreIdx, W4_WORK_PARAM, 0);
  762. pEncInfo->vbTemp.size = 0;
  763. VpuWriteReg(instance->coreIdx, C7_CMD_ENC_SET_PARAM_OPTION, (1<< C7_OPT_COMMON));
  764. // Rotation Left 90 or 270 case : Swap XY resolution for VPU internal usage
  765. if (pEncInfo->rotationAngle == 90 || pEncInfo->rotationAngle == 270)
  766. data = (picHeight<< 16) | picWidth;
  767. else
  768. data = (picWidth << 16) | picHeight;
  769. VpuWriteReg(instance->coreIdx, C7_CMD_ENC_SEQ_SRC_SIZE, data);
  770. VpuWriteReg(instance->coreIdx, C7_CMD_ENC_SEQ_SRC_F_RATE, pEncInfo->openParam.frameRateInfo);
  771. if (pEncInfo->openParam.bitstreamFormat == STD_MPEG4) {
  772. data = pEncInfo->openParam.EncStdParam.mp4Param.mp4IntraDcVlcThr << 2 |
  773. pEncInfo->openParam.EncStdParam.mp4Param.mp4ReversibleVlcEnable << 1 |
  774. pEncInfo->openParam.EncStdParam.mp4Param.mp4DataPartitionEnable;
  775. data |= ((pEncInfo->openParam.EncStdParam.mp4Param.mp4HecEnable >0)? 1:0)<<5;
  776. data |= ((pEncInfo->openParam.EncStdParam.mp4Param.mp4Verid == 2)? 0:1) << 6;
  777. VpuWriteReg(instance->coreIdx, C7_CMD_ENC_SEQ_STD_PARA, data);
  778. }
  779. else if (pEncInfo->openParam.bitstreamFormat == STD_H263) {
  780. data = (1<<5) | // short_header enable
  781. pEncInfo->openParam.EncStdParam.h263Param.h263AnnexIEnable << 3 |
  782. pEncInfo->openParam.EncStdParam.h263Param.h263AnnexJEnable << 2 |
  783. pEncInfo->openParam.EncStdParam.h263Param.h263AnnexKEnable << 1|
  784. pEncInfo->openParam.EncStdParam.h263Param.h263AnnexTEnable;
  785. VpuWriteReg(instance->coreIdx, C7_CMD_ENC_SEQ_AUX_PARA, data);
  786. }
  787. else if (pEncInfo->openParam.bitstreamFormat == STD_AVC) {
  788. data = (pEncInfo->openParam.EncStdParam.avcParam.deblkFilterOffsetBeta & 15) << 12 |
  789. (pEncInfo->openParam.EncStdParam.avcParam.deblkFilterOffsetAlpha & 15) << 8 |
  790. pEncInfo->openParam.EncStdParam.avcParam.disableDeblk << 6 |
  791. pEncInfo->openParam.EncStdParam.avcParam.constrainedIntraPredFlag << 5 |
  792. (pEncInfo->openParam.EncStdParam.avcParam.chromaQpOffset & 31);
  793. VpuWriteReg(instance->coreIdx, C7_CMD_ENC_SEQ_STD_PARA, data);
  794. }
  795. data = pEncInfo->openParam.sliceMode.sliceSize << 16 |
  796. pEncInfo->openParam.sliceMode.sliceSizeMode << 1 |
  797. pEncInfo->openParam.sliceMode.sliceMode;
  798. VpuWriteReg(instance->coreIdx, C7_CMD_ENC_SEQ_SLICE_MODE, data);
  799. VpuWriteReg(instance->coreIdx, C7_CMD_ENC_SEQ_GOP_NUM, pEncInfo->openParam.gopSize);
  800. if (pEncInfo->openParam.rcEnable) { // rate control enabled
  801. data = (pEncInfo->openParam.frameSkipDisable) << 31 |
  802. pEncInfo->openParam.initialDelay << 16 | 1;
  803. VpuWriteReg(instance->coreIdx, C7_CMD_ENC_SEQ_RC_PARAM, data);
  804. VpuWriteReg(instance->coreIdx, C7_CMD_ENC_RC_TARGET_RATE, pEncInfo->openParam.bitRate);
  805. }
  806. else {
  807. VpuWriteReg(instance->coreIdx, C7_CMD_ENC_SEQ_RC_PARAM, 0);
  808. VpuWriteReg(instance->coreIdx, C7_CMD_ENC_RC_TARGET_RATE, 0);
  809. }
  810. VpuWriteReg(instance->coreIdx, C7_CMD_ENC_SEQ_RC_BUF_SIZE, pEncInfo->openParam.vbvBufferSize);
  811. //data = pEncInfo->openParam.intraRefresh | pEncInfo->openParam.ConscIntraRefreshEnable<<16;
  812. data = 0;
  813. if (instance->codecMode == C7_AVC_ENC)
  814. data |= (pEncInfo->openParam.EncStdParam.avcParam.audEnable); // [0] audenable
  815. if(pEncInfo->openParam.rcIntraQp>=0) {
  816. VpuWriteReg(instance->coreIdx, C7_CMD_ENC_SEQ_INTRA_PARAM, pEncInfo->openParam.intraRefresh<<16 | (pEncInfo->openParam.rcIntraQp)<<3 );
  817. data |= (1<<1); // [1] rc_const_intra_qp enable
  818. }
  819. else {
  820. VpuWriteReg(instance->coreIdx, C7_CMD_ENC_SEQ_INTRA_PARAM, pEncInfo->openParam.intraRefresh<<16);
  821. }
  822. if(pEncInfo->openParam.userQpMax>=0) {
  823. data |= (1<<2); // [2] rc_qp_max_enable
  824. VpuWriteReg(instance->coreIdx, C7_CMD_ENC_SEQ_RC_MAX_QP, pEncInfo->openParam.userQpMax<<6); // fix me (support min ??)
  825. }
  826. else {
  827. VpuWriteReg(instance->coreIdx, C7_CMD_ENC_SEQ_RC_MAX_QP, 0);
  828. }
  829. if(pEncInfo->openParam.userGamma >= 0) {
  830. data |= (1<<3); // [3] rc_gamma_enable
  831. VpuWriteReg(instance->coreIdx, C7_CMD_ENC_SEQ_RC_GAMMA, pEncInfo->openParam.userGamma);
  832. }
  833. else {
  834. VpuWriteReg(instance->coreIdx, C7_CMD_ENC_SEQ_RC_GAMMA, 0);
  835. }
  836. VpuWriteReg(instance->coreIdx, C7_CMD_ENC_SEQ_PARAM, data);
  837. VpuWriteReg(instance->coreIdx, C7_CMD_ENC_SEQ_RC_INTERVAL_MODE, (pEncInfo->openParam.mbInterval<<2) | pEncInfo->openParam.rcIntervalMode);
  838. VpuWriteReg(instance->coreIdx, C7_CMD_ENC_SEQ_INTRA_WEIGHT, pEncInfo->openParam.intraCostWeight);
  839. Wave4BitIssueCommand(instance, SET_PARAM);
  840. if ((int_reason = vdi_wait_interrupt(instance->coreIdx, VPU_ENC_TIMEOUT, W4_VPU_VINT_REASON)) == -1) {
  841. if (instance->loggingEnable)
  842. vdi_log(instance->coreIdx, SET_PARAM, 0);
  843. return RETCODE_VPU_RESPONSE_TIMEOUT;
  844. }
  845. VpuWriteReg(instance->coreIdx, W4_VPU_VINT_REASON_CLR, int_reason);
  846. VpuWriteReg(instance->coreIdx, W4_VPU_VINT_CLEAR, 1);
  847. if (instance->loggingEnable)
  848. vdi_log(instance->coreIdx, SET_PARAM, 0);
  849. if (VpuReadReg(instance->coreIdx, W4_RET_SUCCESS) == 0) {
  850. if (VpuReadReg(instance->coreIdx, W4_RET_FAIL_REASON) == WAVE4_SYSERR_WRITEPROTECTION) {
  851. return RETCODE_MEMORY_ACCESS_VIOLATION;
  852. }
  853. return RETCODE_FAILURE;
  854. }
  855. pEncInfo->streamWrPtr = VpuReadReg(instance->coreIdx, pEncInfo->streamWrPtrRegAddr);
  856. return RETCODE_SUCCESS;
  857. }
  858. RetCode Coda7qVpuEncRegisterFramebuffer(CodecInst* instance, FrameBuffer* fbArr, TiledMapType mapType, Uint32 count)
  859. {
  860. RetCode ret = RETCODE_SUCCESS;
  861. EncInfo* pEncInfo = &instance->CodecInfo->encInfo;
  862. Int32 q, j, i, remain, idx, bufHeight = 0, bufWidth = 0;
  863. Int32 coreIdx, startNo, endNo;
  864. Uint32 regVal, cbcrInterleave=0, nv21=0;
  865. Uint32 endian, yuvFormat = 0;
  866. Uint32 addrY, addrCb, addrCr;
  867. Uint32 mvColSize, fbcYTblSize, fbcCTblSize;
  868. Uint32 bpp=1;/* byte per pixel */
  869. int stride;
  870. vpu_buffer_t vbBuffer;
  871. coreIdx = instance->coreIdx;
  872. mvColSize = fbcYTblSize = fbcCTblSize = 0;
  873. stride = pEncInfo->stride;
  874. bufWidth = VPU_ALIGN8(pEncInfo->openParam.picWidth);
  875. bufHeight = VPU_ALIGN8(pEncInfo->openParam.picHeight);
  876. if ((pEncInfo->rotationAngle != 0 || pEncInfo->mirrorDirection != 0) && !(pEncInfo->rotationAngle == 180 && pEncInfo->mirrorDirection == MIRDIR_HOR_VER)) {
  877. bufWidth = VPU_ALIGN32(pEncInfo->openParam.picWidth);
  878. bufHeight = VPU_ALIGN32(pEncInfo->openParam.picHeight);
  879. }
  880. if (pEncInfo->rotationAngle == 90 || pEncInfo->rotationAngle == 270) {
  881. bufWidth = VPU_ALIGN32(pEncInfo->openParam.picHeight);
  882. bufHeight = VPU_ALIGN32(pEncInfo->openParam.picWidth);
  883. }
  884. if (mapType == COMPRESSED_FRAME_MAP) {
  885. fbcYTblSize = CODA7Q_FBC_LUMA_TABLE_SIZE(bufWidth, bufHeight);
  886. fbcYTblSize = VPU_ALIGN16(fbcYTblSize);
  887. vbBuffer.phys_addr = 0;
  888. vbBuffer.size = ((fbcYTblSize*count+4095)&~4095)+4096;
  889. if (vdi_allocate_dma_memory(instance->coreIdx, &vbBuffer) < 0)
  890. return RETCODE_INSUFFICIENT_RESOURCE;
  891. pEncInfo->vbFbcYTbl = vbBuffer;
  892. fbcCTblSize = CODA7Q_FBC_CHROMA_TABLE_SIZE(bufWidth, bufHeight);
  893. fbcCTblSize = VPU_ALIGN16(fbcCTblSize);
  894. vbBuffer.phys_addr = 0;
  895. vbBuffer.size = ((fbcCTblSize*count+4095)&~4095)+4096;
  896. if (vdi_allocate_dma_memory(instance->coreIdx, &vbBuffer) < 0)
  897. return RETCODE_INSUFFICIENT_RESOURCE;
  898. pEncInfo->vbFbcCTbl = vbBuffer;
  899. }
  900. endian = vdi_convert_endian(coreIdx, fbArr[0].endian) & VDI_128BIT_ENDIAN_MASK;
  901. regVal = (nv21 << 29) |
  902. ((mapType == LINEAR_FRAME_MAP)<<28) |
  903. (0 << 24) |
  904. (yuvFormat << 20) |
  905. (cbcrInterleave << 16) |
  906. // (fbcDisable << 20) |
  907. (stride*bpp);
  908. VpuWriteReg(coreIdx, W4_COMMON_PIC_INFO, regVal);
  909. regVal = (bufWidth<<16) | bufHeight;
  910. VpuWriteReg(coreIdx, W4_PIC_SIZE, regVal);
  911. remain = count;
  912. q = (remain+7)/8;
  913. idx = 0;
  914. for (j=0; j<q; j++) {
  915. regVal = (endian<<16) | (j==q-1)<<4 | ((j==0)<<3) ;
  916. VpuWriteReg(coreIdx, W4_SFB_OPTION, regVal);
  917. startNo = j*8;
  918. endNo = startNo + (remain>=8 ? 8 : remain) - 1;
  919. VpuWriteReg(coreIdx, W4_SET_FB_NUM, (startNo<<8)|endNo);
  920. for (i=0; i<8 && i<remain; i++) {
  921. addrY = fbArr[i+startNo].bufY;
  922. addrCb = fbArr[i+startNo].bufCb;
  923. addrCr = fbArr[i+startNo].bufCr;
  924. VpuWriteReg(coreIdx, W4_ADDR_LUMA_BASE0 + (i<<4), addrY);
  925. VpuWriteReg(coreIdx, W4_ADDR_CB_BASE0 + (i<<4), addrCb);
  926. APIDPRINT("REGISTER FB[%02d] Y(0x%08x), Cb(0x%08x) ", i, addrY, addrCb);
  927. if (mapType == COMPRESSED_FRAME_MAP) {
  928. VpuWriteReg(coreIdx, W4_ADDR_FBC_Y_OFFSET0 + (i<<4), pEncInfo->vbFbcYTbl.phys_addr+idx*fbcYTblSize); /* Luma FBC offset table */
  929. VpuWriteReg(coreIdx, W4_ADDR_FBC_C_OFFSET0 + (i<<4), pEncInfo->vbFbcCTbl.phys_addr+idx*fbcCTblSize); /* Chroma FBC offset table */
  930. VpuWriteReg(coreIdx, W4_ADDR_MV_COL0 + (i<<2), pEncInfo->vbMV.phys_addr+idx*mvColSize);
  931. APIDPRINT("Yo(0x%08x) Co(0x%08x), Mv(0x%08x)\n",
  932. pEncInfo->vbFbcYTbl.phys_addr+idx*fbcYTblSize,
  933. pEncInfo->vbFbcCTbl.phys_addr+idx*fbcCTblSize,
  934. pEncInfo->vbMV.phys_addr+idx*mvColSize);
  935. }
  936. else {
  937. VpuWriteReg(coreIdx, W4_ADDR_CR_BASE0 + (i<<4), addrCr);
  938. VpuWriteReg(coreIdx, W4_ADDR_FBC_C_OFFSET0 + (i<<4), 0);
  939. VpuWriteReg(coreIdx, W4_ADDR_MV_COL0 + (i<<2), 0);
  940. APIDPRINT("Cr(0x%08x)\n", addrCr);
  941. }
  942. idx++;
  943. }
  944. remain -= i;
  945. VpuWriteReg(coreIdx, W4_ADDR_WORK_BASE, pEncInfo->vbWork.phys_addr);
  946. VpuWriteReg(coreIdx, W4_WORK_SIZE, pEncInfo->vbWork.size);
  947. VpuWriteReg(coreIdx, W4_WORK_PARAM, 0);
  948. Wave4BitIssueCommand(instance, SET_FRAMEBUF);
  949. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, W4_VPU_BUSY_STATUS) == -1) {
  950. return RETCODE_VPU_RESPONSE_TIMEOUT;
  951. }
  952. }
  953. regVal = VpuReadReg(coreIdx, W4_RET_SUCCESS);
  954. if (regVal == 0) {
  955. return RETCODE_FAILURE;
  956. }
  957. if (ConfigSecAXICoda7(coreIdx, pEncInfo->openParam.bitstreamFormat,
  958. &pEncInfo->secAxiInfo,
  959. pEncInfo->openParam.picWidth, pEncInfo->openParam.picHeight, pEncInfo->openParam.EncStdParam.hevcParam.profile) == 0) {
  960. return RETCODE_INSUFFICIENT_RESOURCE;
  961. }
  962. return ret;
  963. }
  964. RetCode Coda7qVpuEncGetHeader(EncHandle instance, EncHeaderParam* encHeaderParam)
  965. {
  966. EncInfo * pEncInfo;
  967. EncOpenParam *encOP;
  968. PhysicalAddress rdPtr;
  969. PhysicalAddress wrPtr;
  970. Int32 coreIdx, bsEndian, wrapAroundFlag, regVal, int_reason;
  971. RetCode ret;
  972. pEncInfo = VPU_HANDLE_TO_ENCINFO(instance);
  973. encOP = &(pEncInfo->openParam);
  974. coreIdx = instance->coreIdx;
  975. EnterLock(coreIdx);
  976. regVal = vdi_convert_endian(coreIdx, encOP->streamEndian);
  977. bsEndian = (regVal&VDI_128BIT_ENDIAN_MASK);
  978. if (pEncInfo->ringBufferEnable == 1) {
  979. VpuWriteReg(coreIdx, W4_BS_START_ADDR, pEncInfo->streamBufStartAddr);
  980. VpuWriteReg(coreIdx, W4_BS_SIZE, pEncInfo->streamBufSize);
  981. }
  982. else {
  983. VpuWriteReg(coreIdx, W4_BS_START_ADDR, encHeaderParam->buf);
  984. VpuWriteReg(coreIdx, W4_BS_SIZE, encHeaderParam->size);
  985. pEncInfo->streamRdPtr = encHeaderParam->buf;
  986. pEncInfo->streamWrPtr = encHeaderParam->buf;
  987. pEncInfo->streamBufStartAddr = encHeaderParam->buf;
  988. pEncInfo->streamBufSize = encHeaderParam->size;
  989. pEncInfo->streamBufEndAddr = encHeaderParam->buf + encHeaderParam->size;
  990. }
  991. //[FIX ME!!!!!]
  992. if (pEncInfo->ringBufferEnable == 1)
  993. wrapAroundFlag = 0;
  994. else
  995. wrapAroundFlag = 1;
  996. VpuWriteReg(coreIdx, W4_BS_PARAM, (wrapAroundFlag<<4) | bsEndian);
  997. VpuWriteReg(coreIdx, W4_BS_OPTION, 0);
  998. /* Set up work-buffer */
  999. VpuWriteReg(coreIdx, W4_ADDR_WORK_BASE, pEncInfo->vbWork.phys_addr);
  1000. VpuWriteReg(coreIdx, W4_WORK_SIZE, pEncInfo->vbWork.size);
  1001. VpuWriteReg(coreIdx, W4_WORK_PARAM, 0);
  1002. VpuWriteReg(coreIdx, pEncInfo->streamRdPtrRegAddr, pEncInfo->streamRdPtr);
  1003. VpuWriteReg(coreIdx, pEncInfo->streamWrPtrRegAddr, pEncInfo->streamWrPtr);
  1004. if (encHeaderParam->headerType == SPS_RBSP && pEncInfo->openParam.bitstreamFormat == STD_AVC) {
  1005. if (encOP->EncStdParam.avcParam.frameCroppingFlag == 1) {
  1006. VpuWriteReg(coreIdx, C7_CMD_ENC_CONF_WIN_TOP_BOT, encOP->EncStdParam.avcParam.frameCropTop << 16 | encOP->EncStdParam.avcParam.frameCropBottom);
  1007. VpuWriteReg(coreIdx, C7_CMD_ENC_CONF_WIN_LEFT_RIGHT, encOP->EncStdParam.avcParam.frameCropLeft << 16 | encOP->EncStdParam.avcParam.frameCropRight);
  1008. }
  1009. }
  1010. VpuWriteReg(coreIdx, C7_CMD_ENC_CODE_OPTION, (encOP->EncStdParam.avcParam.frameCroppingFlag<<6) | 1<<(encHeaderParam->headerType));
  1011. VpuWriteReg(coreIdx, C7_CMD_ENC_PIC_OPTION, OPT_HEADER_ENC); // encode header
  1012. Wave4BitIssueCommand(instance, ENC_PIC);
  1013. if ((int_reason = vdi_wait_interrupt(coreIdx, VPU_ENC_TIMEOUT, W4_VPU_VINT_REASON)) == -1) {
  1014. LeaveLock(coreIdx);
  1015. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1016. }
  1017. VpuWriteReg(coreIdx, W4_VPU_VINT_REASON_CLR, int_reason);
  1018. VpuWriteReg(coreIdx, W4_VPU_VINT_CLEAR, 1);
  1019. if (instance->loggingEnable)
  1020. vdi_log(coreIdx, ENC_PIC, 0);
  1021. rdPtr = VpuReadReg(coreIdx, pEncInfo->streamRdPtrRegAddr);
  1022. wrPtr = VpuReadReg(coreIdx, pEncInfo->streamWrPtrRegAddr);
  1023. encHeaderParam->buf = rdPtr;
  1024. encHeaderParam->size = wrPtr - rdPtr;
  1025. pEncInfo->streamWrPtr = wrPtr;
  1026. pEncInfo->streamRdPtr = rdPtr;
  1027. regVal = VpuReadReg(coreIdx, W4_RET_SUCCESS);
  1028. if (regVal == 0) {
  1029. encHeaderParam->failReasonCode = VpuReadReg(coreIdx, W4_RET_FAIL_REASON);
  1030. ret = RETCODE_FAILURE;
  1031. }
  1032. else {
  1033. ret = RETCODE_SUCCESS;
  1034. }
  1035. LeaveLock(coreIdx);
  1036. return ret;
  1037. }
  1038. RetCode Coda7qVpuEncode(CodecInst* instance, EncParam* option)
  1039. {
  1040. Int32 coreIdx, srcFrameFormat;
  1041. Uint32 regVal = 0, bsEndian, wrapAroundFlag;
  1042. EncInfo* pEncInfo;
  1043. FrameBuffer* pSrcFrame;
  1044. EncOpenParam* pOpenParam;
  1045. coreIdx = instance->coreIdx;
  1046. pEncInfo = VPU_HANDLE_TO_ENCINFO(instance);
  1047. pOpenParam = &pEncInfo->openParam;
  1048. pSrcFrame = option->sourceFrame;
  1049. if (pEncInfo->openParam.ringBufferEnable == 1) {
  1050. VpuWriteReg(coreIdx, W4_BS_START_ADDR, pEncInfo->streamBufStartAddr);
  1051. VpuWriteReg(coreIdx, W4_BS_SIZE, pEncInfo->streamBufSize);
  1052. }
  1053. else {
  1054. VpuWriteReg(coreIdx, W4_BS_START_ADDR, option->picStreamBufferAddr);
  1055. VpuWriteReg(coreIdx, W4_BS_SIZE, option->picStreamBufferSize);
  1056. pEncInfo->streamRdPtr = option->picStreamBufferAddr;
  1057. pEncInfo->streamWrPtr = option->picStreamBufferAddr;
  1058. pEncInfo->streamBufStartAddr = option->picStreamBufferAddr;
  1059. pEncInfo->streamBufSize = option->picStreamBufferSize;
  1060. pEncInfo->streamBufEndAddr = option->picStreamBufferAddr + option->picStreamBufferSize;
  1061. }
  1062. VpuWriteReg(coreIdx, pEncInfo->streamRdPtrRegAddr, pEncInfo->streamRdPtr);
  1063. VpuWriteReg(coreIdx, pEncInfo->streamWrPtrRegAddr, pEncInfo->streamWrPtr);
  1064. //[FIX ME!!!!!]
  1065. if (pEncInfo->ringBufferEnable == 1)
  1066. wrapAroundFlag = 0;
  1067. else
  1068. wrapAroundFlag = 1;
  1069. regVal = vdi_convert_endian(coreIdx, pOpenParam->streamEndian);
  1070. bsEndian = (regVal&VDI_128BIT_ENDIAN_MASK);
  1071. VpuWriteReg(coreIdx, W4_BS_PARAM, (wrapAroundFlag<<4) | bsEndian);
  1072. /* Secondary AXI */
  1073. VpuWriteReg(coreIdx, W4_ADDR_SEC_AXI, pEncInfo->secAxiInfo.bufBase);
  1074. VpuWriteReg(coreIdx, W4_SEC_AXI_SIZE, pEncInfo->secAxiInfo.bufSize);
  1075. VpuWriteReg(coreIdx, W4_USE_SEC_AXI, ((pEncInfo->secAxiInfo.u.coda9.useBitEnable&0x01) <<0 | // fix me.
  1076. (pEncInfo->secAxiInfo.u.coda9.useIpEnable&0x01) <<1 |
  1077. (pEncInfo->secAxiInfo.u.coda9.useDbkYEnable&0x01) <<2 |
  1078. (pEncInfo->secAxiInfo.u.coda9.useDbkCEnable&0x01) <<3 |
  1079. (pEncInfo->secAxiInfo.u.coda9.useOvlEnable&0x01) <<4 |
  1080. (pEncInfo->secAxiInfo.u.coda9.useMeEnable&0x01) <<5 |
  1081. (pEncInfo->secAxiInfo.u.coda9.useBitEnable&0x01) <<8 |
  1082. (pEncInfo->secAxiInfo.u.coda9.useIpEnable&0x01) <<9 |
  1083. (pEncInfo->secAxiInfo.u.coda9.useDbkYEnable&0x01) <<10 |
  1084. (pEncInfo->secAxiInfo.u.coda9.useDbkCEnable&0x01) <<11 |
  1085. (pEncInfo->secAxiInfo.u.coda9.useOvlEnable&0x01) <<12 |
  1086. (pEncInfo->secAxiInfo.u.coda9.useMeEnable&0x01) <<13));
  1087. /* Set up work-buffer */
  1088. VpuWriteReg(coreIdx, W4_ADDR_WORK_BASE, pEncInfo->vbWork.phys_addr);
  1089. VpuWriteReg(coreIdx, W4_WORK_SIZE, pEncInfo->vbWork.size);
  1090. VpuWriteReg(coreIdx, W4_WORK_PARAM, 0);
  1091. /* Set up temp-buffer */
  1092. VpuWriteReg(coreIdx, W4_ADDR_TEMP_BASE, pEncInfo->vbTemp.phys_addr);
  1093. VpuWriteReg(coreIdx, W4_TEMP_SIZE, pEncInfo->vbTemp.size);
  1094. VpuWriteReg(coreIdx, W4_TEMP_PARAM, 0);
  1095. /* Set up reporting-buffer */
  1096. VpuWriteReg(coreIdx, C7_CMD_ENC_PIC_OPTION, OPT_ENC_PIC);
  1097. srcFrameFormat = pOpenParam->cbcrInterleave<<1 | pOpenParam->nv21;
  1098. VpuWriteReg(coreIdx, C7_CMD_ENC_SRC_FORMAT, (srcFrameFormat<<0) |
  1099. //(srcPixelFormat<<3) |
  1100. (option->srcEndFlag<<31));
  1101. VpuWriteReg(coreIdx, C7_CMD_ENC_PIC_QS, option->quantParam);
  1102. if (option->skipPicture) {
  1103. VpuWriteReg(coreIdx, C7_CMD_ENC_PIC_PARAM, 1); // pic_skip_flag = 1
  1104. }
  1105. else {
  1106. VpuWriteReg(coreIdx, C7_CMD_ENC_SRC_STRIDE, pSrcFrame->stride);
  1107. VpuWriteReg(coreIdx, C7_CMD_ENC_SRC_ADDR_Y, pSrcFrame->bufY);
  1108. if (pOpenParam->cbcrOrder == CBCR_ORDER_NORMAL) {
  1109. VpuWriteReg(coreIdx, C7_CMD_ENC_SRC_ADDR_U, pSrcFrame->bufCb);
  1110. VpuWriteReg(coreIdx, C7_CMD_ENC_SRC_ADDR_V, pSrcFrame->bufCr);
  1111. }
  1112. else {
  1113. VpuWriteReg(coreIdx, C7_CMD_ENC_SRC_ADDR_U, pSrcFrame->bufCr);
  1114. VpuWriteReg(coreIdx, C7_CMD_ENC_SRC_ADDR_V, pSrcFrame->bufCb);
  1115. }
  1116. VpuWriteReg(coreIdx, C7_CMD_ENC_PIC_PARAM, 0 |
  1117. (option->forcePicQpEnable<<1) |
  1118. (option->forcePicQpI<<2) |
  1119. (option->forcePicQpP<<8) |
  1120. (option->forcePicTypeEnable<<20) |
  1121. (option->forcePicType)<< 21);
  1122. }
  1123. Wave4BitIssueCommand(instance, ENC_PIC);
  1124. return RETCODE_SUCCESS;
  1125. }
  1126. RetCode Coda7qVpuEncGetResult(CodecInst* instance, EncOutputInfo* result)
  1127. {
  1128. Uint32 encodingSuccess, errorReason = 0;
  1129. Int32 coreIdx;
  1130. EncInfo* pEncInfo = VPU_HANDLE_TO_ENCINFO(instance);
  1131. coreIdx = instance->coreIdx;
  1132. if (instance->loggingEnable)
  1133. vdi_log(coreIdx, ENC_PIC, 0);
  1134. encodingSuccess = VpuReadReg(coreIdx, W4_RET_SUCCESS);
  1135. if (encodingSuccess == FALSE) {
  1136. errorReason = VpuReadReg(coreIdx, W4_RET_FAIL_REASON);
  1137. if (errorReason == WAVE4_SYSERR_WRITEPROTECTION) {
  1138. vdi_print_vpu_status(coreIdx);
  1139. return RETCODE_MEMORY_ACCESS_VIOLATION;
  1140. }
  1141. if (errorReason == WAVE4_SYSERR_CP0_EXCEPTION) {
  1142. vdi_print_vpu_status(coreIdx);
  1143. return RETCODE_CP0_EXCEPTION;
  1144. }
  1145. if (errorReason == WAVE4_SYSERR_STREAM_BUF_FULL) {
  1146. vdi_print_vpu_status(coreIdx);
  1147. return RETCODE_STREAM_BUF_FULL;
  1148. }
  1149. if (errorReason == WAVE4_SYSERR_ACCESS_VIOLATION_HW) {
  1150. vdi_print_vpu_status(coreIdx);
  1151. return RETCODE_ACCESS_VIOLATION_HW;
  1152. }
  1153. return RETCODE_FAILURE;
  1154. }
  1155. pEncInfo->frameIdx = VpuReadReg(coreIdx, C7_RET_ENC_PIC_NUM);
  1156. result->picType = VpuReadReg(coreIdx, C7_RET_ENC_PIC_TYPE);
  1157. result->numOfSlices = VpuReadReg(coreIdx, C7_RET_ENC_PIC_SLICE_NUM);
  1158. result->reconFrameIndex = VpuReadReg(coreIdx, C7_RET_ENC_PIC_FRAME_IDX);
  1159. result->bitstreamWrapAround = VpuReadReg(coreIdx, C7_RET_ENC_PIC_FLAG);
  1160. if (result->reconFrameIndex >= 0)
  1161. result->reconFrame = pEncInfo->frameBufPool[result->reconFrameIndex];
  1162. result->frameCycle = VpuReadReg(coreIdx, W4_FRAME_CYCLE);
  1163. pEncInfo->streamWrPtr = VpuReadReg(coreIdx, pEncInfo->streamWrPtrRegAddr);
  1164. if (pEncInfo->ringBufferEnable == 0) {
  1165. result->bitstreamBuffer = VpuReadReg(coreIdx, pEncInfo->streamRdPtrRegAddr);
  1166. result->bitstreamSize = pEncInfo->streamWrPtr - result->bitstreamBuffer;
  1167. }
  1168. result->rdPtr = pEncInfo->streamRdPtr;
  1169. result->wrPtr = pEncInfo->streamWrPtr;
  1170. if (result->reconFrameIndex < 0)
  1171. result->bitstreamSize = 0;
  1172. return RETCODE_SUCCESS;
  1173. }