vpuconfig.h 5.4 KB

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  1. /* SPDX-License-Identifier: LGPL-2.1 OR BSD-3-Clause */
  2. //--=========================================================================--
  3. // This file is a part of VPU Reference API project
  4. //-----------------------------------------------------------------------------
  5. //
  6. // This confidential and proprietary software may be used only
  7. // as authorized by a licensing agreement from Chips&Media Inc.
  8. // In the event of publication, the following notice is applicable:
  9. //
  10. // (C) COPYRIGHT 2006 - 2011 CHIPS&MEDIA INC.
  11. // ALL RIGHTS RESERVED
  12. //
  13. // The entire notice above must be reproduced on all authorized
  14. // copies.
  15. // This file should be modified by some customers according to their SOC configuration.
  16. //--=========================================================================--
  17. #ifndef _VPU_CONFIG_H_
  18. #define _VPU_CONFIG_H_
  19. #include "../config.h"
  20. #define BODA7503_CODE 0x7503
  21. #define CODA7542_CODE 0x7542
  22. #define BODA950_CODE 0x9500
  23. #define CODA960_CODE 0x9600
  24. #define CODA980_CODE 0x9800
  25. #define WAVE320_CODE 0x3200
  26. #define WAVE410_CODE 0x4100 /* Wave410 version 1: Single vcore */
  27. #define WAVE4102_CODE 0x4102 /* Wave410 version 2: Multi vcore */
  28. #define WAVE420_CODE 0x4200 /* Wave420 */
  29. #define WAVE420L_CODE 0x4201 /* Wave420L */
  30. #define WAVE412_CODE 0x4120
  31. #define WAVE510_CODE 0x5100
  32. #define WAVE512_CODE 0x5120
  33. #define WAVE515_CODE 0x5150
  34. #define WAVE520_CODE 0x5200
  35. #define CODA7Q_CODE 0x7101
  36. #define PRODUCT_CODE_W_SERIES(x) (x == WAVE410_CODE || x == WAVE4102_CODE || x == WAVE420_CODE || x == WAVE412_CODE || x == CODA7Q_CODE || x == WAVE420L_CODE || x == WAVE510_CODE || x == WAVE512_CODE || x == WAVE515_CODE || x == WAVE520_CODE)
  37. #define PRODUCT_CODE_NOT_W_SERIES(x) (x == BODA7503_CODE || x == CODA7542_CODE || x == BODA950_CODE || x == CODA960_CODE || x == CODA980_CODE || x == WAVE320_CODE)
  38. #define MAX_INST_HANDLE_SIZE 48 /* DO NOT CHANGE THIS VALUE */
  39. #define MAX_NUM_INSTANCE 4
  40. #define MAX_NUM_VPU_CORE 1
  41. #define MAX_NUM_VCORE 1
  42. #define MAX_ENC_AVC_PIC_WIDTH 4096
  43. #define MAX_ENC_AVC_PIC_HEIGHT 2304
  44. #define MAX_ENC_PIC_WIDTH 4096
  45. #define MAX_ENC_PIC_HEIGHT 2304
  46. #define MIN_ENC_PIC_WIDTH 96
  47. #define MIN_ENC_PIC_HEIGHT 16
  48. // for WAVE420
  49. #define W4_MIN_ENC_PIC_WIDTH 256
  50. #define W4_MIN_ENC_PIC_HEIGHT 128
  51. #define W4_MAX_ENC_PIC_WIDTH 8192
  52. #define W4_MAX_ENC_PIC_HEIGHT 8192
  53. #define MAX_DEC_PIC_WIDTH 4096
  54. #define MAX_DEC_PIC_HEIGHT 2304
  55. // Application specific configuration
  56. #ifdef HAPS_SIM
  57. #define VPU_ENC_TIMEOUT (30000*10000)
  58. #else
  59. #define VPU_ENC_TIMEOUT 30000
  60. #endif
  61. #define VPU_DEC_TIMEOUT 10000
  62. #ifdef HAPS_SIM
  63. #define VPU_BUSY_CHECK_TIMEOUT (5000*10000)
  64. #else
  65. #define VPU_BUSY_CHECK_TIMEOUT 5000
  66. #endif
  67. // codec specific configuration
  68. #define VPU_REORDER_ENABLE 1 // it can be set to 1 to handle reordering DPB in host side.
  69. #define CBCR_INTERLEAVE 1 //[default 1 for BW checking with CnMViedo Conformance] 0 (chroma separate mode), 1 (chroma interleave mode) // if the type of tiledmap uses the kind of MB_RASTER_MAP. must set to enable CBCR_INTERLEAVE
  70. #define VPU_ENABLE_BWB 1
  71. #define HOST_ENDIAN VDI_128BIT_LITTLE_ENDIAN
  72. #define VPU_FRAME_ENDIAN HOST_ENDIAN
  73. #define VPU_STREAM_ENDIAN HOST_ENDIAN
  74. #define VPU_USER_DATA_ENDIAN HOST_ENDIAN
  75. #define VPU_SOURCE_ENDIAN HOST_ENDIAN
  76. #define DRAM_BUS_WIDTH 16
  77. /************************************************************************/
  78. /* VPU COMMON MEMORY */
  79. /************************************************************************/
  80. #define COMMAND_QUEUE_DEPTH 4
  81. #define ONE_TASKBUF_SIZE_FOR_W5DEC_CQ (8*1024*1024) /* upto 8Kx4K, need 8Mbyte per task*/
  82. #define ONE_TASKBUF_SIZE_FOR_W5ENC_CQ (16*1024*1024) /* upto 8Kx8K, need 16Mbyte per task. (worst case VLC data =: 13M for 8kx8k) */
  83. #define ONE_TASKBUF_SIZE_FOR_CQ 0x0
  84. #define SIZE_COMMON (2*1024*1024)
  85. //=====4. VPU REPORT MEMORY ======================//
  86. #define SIZE_REPORT_BUF (0x10000)
  87. #define STREAM_END_SIZE 0
  88. #define STREAM_END_SET_FLAG 0
  89. #define STREAM_END_CLEAR_FLAG -1
  90. #define EXPLICIT_END_SET_FLAG -2
  91. #define USE_BIT_INTERNAL_BUF 0
  92. #define USE_IP_INTERNAL_BUF 0
  93. #define USE_DBKY_INTERNAL_BUF 0
  94. #define USE_DBKC_INTERNAL_BUF 0
  95. #define USE_OVL_INTERNAL_BUF 0
  96. #define USE_BTP_INTERNAL_BUF 0
  97. #define USE_ME_INTERNAL_BUF 0
  98. /* WAVE410 only */
  99. #define USE_BPU_INTERNAL_BUF 0
  100. #define USE_VCE_IP_INTERNAL_BUF 0
  101. #define USE_VCE_LF_ROW_INTERNAL_BUF 0
  102. /* WAVE420 only */
  103. #define USE_IMD_INTERNAL_BUF 0
  104. #define USE_RDO_INTERNAL_BUF 0
  105. #define USE_LF_INTERNAL_BUF 0
  106. #endif /* _VPU_CONFIG_H_ */