coda9_vpuconfig.h 4.7 KB

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  1. /* SPDX-License-Identifier: LGPL-2.1 OR BSD-3-Clause */
  2. //--=========================================================================--
  3. // This file is a part of VPU Reference API project
  4. //-----------------------------------------------------------------------------
  5. //
  6. // This confidential and proprietary software may be used only
  7. // as authorized by a licensing agreement from Chips&Media Inc.
  8. // In the event of publication, the following notice is applicable:
  9. //
  10. // (C) COPYRIGHT 2006 - 2011 CHIPS&MEDIA INC.
  11. // ALL RIGHTS RESERVED
  12. //
  13. // The entire notice above must be reproduced on all authorized
  14. // copies.
  15. // This file should be modified by some customers according to their SOC configuration.
  16. //--=========================================================================--
  17. #ifndef __CODA9_VPU_CONFIG_H__
  18. #define __CODA9_VPU_CONFIG_H__
  19. #include "vpuconfig.h"
  20. #include "vputypes.h"
  21. #if MAX_DEC_PIC_WIDTH > 1920 // 4K
  22. #define USE_WTL 0 // not support 4K WTL
  23. #define MAX_EXTRA_FRAME_BUFFER_NUM 1
  24. #define MAX_PP_SRC_NUM 2 //PPU buffer(decoding case) or Source buffer(encoding case)
  25. #define MAX_DPB_MBS 110400 // 32768 for level 5
  26. #elif MAX_DEC_PIC_WIDTH > 720
  27. #define USE_WTL 0 // for WTL (needs MAX_DPB_NUM*2 frame)
  28. #define MAX_EXTRA_FRAME_BUFFER_NUM 4
  29. #define MAX_PP_SRC_NUM 2 //PPU buffer(decoding case) or Source buffer(encoding case)
  30. #define MAX_DPB_MBS 32768 // 32768 for level 4.1
  31. #else
  32. #define USE_WTL 0 // for WTL (needs MAX_DPB_NUM*2 frame)
  33. #define MAX_EXTRA_FRAME_BUFFER_NUM 4
  34. #define MAX_PP_SRC_NUM 2 //PPU buffer(decoding case) or Source buffer(encoding case)
  35. #define MAX_DPB_MBS 32768 // 32768 for level 4.1
  36. #endif
  37. // codec specific configuration
  38. #define VPU_REORDER_ENABLE 1 // it can be set to 1 to handle reordering DPB in host side.
  39. #define VPU_GMC_PROCESS_METHOD 0
  40. #define VPU_AVC_X264_SUPPORT 1
  41. // DRAM configuration for TileMap access
  42. #define EM_RAS 13
  43. #define EM_BANK 3
  44. #define EM_CAS 10
  45. #define EM_WIDTH 2
  46. // DDR3 3BA, DDR4 1BG+2BA
  47. //#define EM_RAS 16
  48. //#define EM_BANK 3
  49. //#define EM_CAS 10
  50. //#define EM_WIDTH 3
  51. // DDR3 4BA, DDR4 2BG+2BA
  52. //#define EM_RAS 15
  53. //#define EM_BANK 4
  54. //#define EM_CAS 10
  55. //#define EM_WIDTH 3
  56. #define VPU_ME_LINEBUFFER_MODE 0
  57. #define VPU_GBU_SIZE 1024
  58. //********************************************//
  59. // External Memory Map Table
  60. //********************************************//
  61. # define CODE_BUF_SIZE (272*1024)
  62. # define TEMP_BUF_SIZE (470*1024)
  63. # define WORK_BUF_SIZE (80*1024)
  64. #define PARA_BUF_SIZE (10*1024)
  65. //=====2. VPU BITSTREAM MEMORY ===================//
  66. #define MAX_STREAM_BUF_SIZE 0x300000 // max bitstream size
  67. //===== 3. VPU PPS Save Size ===================//
  68. //----- SPS/PPS save buffer --------------------//
  69. #define PS_SAVE_SIZE ((320+8)*1024*4) // sps[64], pps[256], backupPsBuf[8] for rollback, error concealment (each 4Kbyte)
  70. //----- VP8 MB save buffer -------------------//
  71. #define VP8_MB_SAVE_SIZE (17*4*(MAX_DEC_PIC_WIDTH*MAX_DEC_PIC_HEIGHT/256)) // MB information + split MVs)*4*MbNumbyte
  72. //----- slice save buffer --------------------//
  73. #define SLICE_SAVE_SIZE (MAX_DEC_PIC_WIDTH*MAX_DEC_PIC_HEIGHT*3/4) // this buffer for ASO/FMO
  74. //=====5. VPU Encoder Scratch buffer ssize ======================//
  75. #define SIZE_AVCENC_QMAT_TABLE ((16*6)+(64*2)) // 4x4 6, 8x8 2
  76. #define SIZE_MP4ENC_DATA_PARTITION (MAX_ENC_PIC_WIDTH*MAX_ENC_PIC_HEIGHT*3/4)
  77. //=====6. Check VPU required memory size =======================//
  78. #define MAX_FRM_SIZE ((MAX_DEC_PIC_WIDTH*MAX_DEC_PIC_HEIGHT*3)/2)
  79. #define MAX_DEC_FRAME_BUFFERING (MAX_DPB_MBS/((MAX_DEC_PIC_WIDTH*MAX_DEC_PIC_HEIGHT)/256))
  80. #define MAX_DPB_NUM (16 < MAX_DEC_FRAME_BUFFERING ? (16+2+MAX_EXTRA_FRAME_BUFFER_NUM) : (MAX_DEC_FRAME_BUFFERING+2+MAX_EXTRA_FRAME_BUFFER_NUM)) // (+2 for current and display_delay)
  81. #define MAX_DPB_SIZE (((MAX_FRM_SIZE+0x3fff)&(~0x3fff))*MAX_DPB_NUM) // frame buffer for codec (MAX_DPB_NUM)
  82. #define MAX_MV_COL_SIZE (((MAX_FRM_SIZE+4)/5)*MAX_DPB_NUM)
  83. #define MAX_PP_SRC_SIZE (((MAX_FRM_SIZE+0x3fff)&(~0x3fff))*MAX_PP_SRC_NUM)
  84. #define CODEC_FRAME_BASE ((((MAX_STREAM_BUF_SIZE*MAX_NUM_INSTANCE)) + 0xff) & (~0xff))
  85. #define REQUIRED_VPU_MEMORY_SIZE (CODEC_FRAME_BASE+((MAX_DPB_SIZE*(1+USE_WTL))+MAX_MV_COL_SIZE+MAX_PP_SRC_SIZE)*MAX_NUM_INSTANCE)
  86. #endif /* __CODA9_VPU_CONFIG_H__ */