coda9.c 118 KB

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  1. // SPDX-License-Identifier: LGPL-2.1 OR BSD-3-Clause
  2. //--=========================================================================--
  3. // This file is a part of VPU Reference API project
  4. //-----------------------------------------------------------------------------
  5. //
  6. // This confidential and proprietary software may be used only
  7. // as authorized by a licensing agreement from Chips&Media Inc.
  8. // In the event of publication, the following notice is applicable:
  9. //
  10. // (C) COPYRIGHT 2006 - 2013 CHIPS&MEDIA INC.
  11. // ALL RIGHTS RESERVED
  12. //
  13. // The entire notice above must be reproduced on all authorized
  14. // copies.
  15. //
  16. //--=========================================================================--
  17. #include "coda9_vpuconfig.h"
  18. #include "product.h"
  19. #include "coda9_regdefine.h"
  20. static void LoadBitCode(Uint32 coreIdx, PhysicalAddress codeBase, const Uint16 *codeWord, int codeSize)
  21. {
  22. int i;
  23. BYTE code[8];
  24. for (i=0; i<codeSize; i+=4) {
  25. // 2byte little endian variable to 1byte big endian buffer
  26. code[0] = (BYTE)(codeWord[i+0]>>8);
  27. code[1] = (BYTE)codeWord[i+0];
  28. code[2] = (BYTE)(codeWord[i+1]>>8);
  29. code[3] = (BYTE)codeWord[i+1];
  30. code[4] = (BYTE)(codeWord[i+2]>>8);
  31. code[5] = (BYTE)codeWord[i+2];
  32. code[6] = (BYTE)(codeWord[i+3]>>8);
  33. code[7] = (BYTE)codeWord[i+3];
  34. VpuWriteMem(coreIdx, codeBase+i*2, (BYTE *)code, 8, VDI_BIG_ENDIAN);
  35. }
  36. vdi_set_bit_firmware_to_pm(coreIdx, codeWord);
  37. }
  38. static RetCode BitLoadFirmware(Uint32 coreIdx, PhysicalAddress codeBase, const Uint16 *codeWord, int codeSize)
  39. {
  40. int i;
  41. Uint32 data;
  42. LoadBitCode(coreIdx, codeBase, codeWord, codeSize);
  43. VpuWriteReg(coreIdx, BIT_INT_ENABLE, 0);
  44. VpuWriteReg(coreIdx, BIT_CODE_RUN, 0);
  45. #ifdef SMALL_CODE_SIZE
  46. for (i=0; i<10*1024; ++i) {
  47. #else
  48. for (i=0; i<2048; ++i) {
  49. #endif
  50. data = codeWord[i];
  51. VpuWriteReg(coreIdx, BIT_CODE_DOWN, (i << 16) | data);
  52. }
  53. return RETCODE_SUCCESS;
  54. }
  55. static void SetEncFrameMemInfo(CodecInst* pCodecInst)
  56. {
  57. Uint32 val;
  58. EncInfo* pEncInfo = &pCodecInst->CodecInfo->encInfo;
  59. switch (pCodecInst->productId) {
  60. case PRODUCT_ID_960:
  61. val = 0;
  62. if (pEncInfo->mapType) {
  63. if (pEncInfo->mapType == TILED_FRAME_MB_RASTER_MAP || pEncInfo->mapType == TILED_FIELD_MB_RASTER_MAP)
  64. val |= (pEncInfo->linear2TiledEnable<<11)|(0x03<<9)|(FORMAT_420<<6);
  65. else
  66. val |= (pEncInfo->linear2TiledEnable<<11)|(0x02<<9)|(FORMAT_420<<6);
  67. }
  68. val |= ((pEncInfo->openParam.cbcrInterleave)<<2); // Interleave bit position is modified
  69. val |= (pEncInfo->openParam.cbcrInterleave&pEncInfo->openParam.nv21) << 3;
  70. val |= (pEncInfo->openParam.bwbEnable<<12);
  71. val |= pEncInfo->openParam.frameEndian;
  72. VpuWriteReg(pCodecInst->coreIdx, BIT_FRAME_MEM_CTRL, val);
  73. break;
  74. }
  75. return;
  76. }
  77. void Coda9BitIssueCommand(Uint32 coreIdx, CodecInst *inst, int cmd)
  78. {
  79. int instIdx = 0;
  80. int cdcMode = 0;
  81. int auxMode = 0;
  82. if (inst != NULL) // command is specific to instance
  83. {
  84. instIdx = inst->instIndex;
  85. cdcMode = inst->codecMode;
  86. auxMode = inst->codecModeAux;
  87. }
  88. if (inst) {
  89. if (inst->codecMode < AVC_ENC) {
  90. VpuWriteReg(coreIdx, BIT_WORK_BUF_ADDR, inst->CodecInfo->decInfo.vbWork.phys_addr);
  91. }
  92. else {
  93. VpuWriteReg(coreIdx, BIT_WORK_BUF_ADDR, inst->CodecInfo->encInfo.vbWork.phys_addr);
  94. }
  95. }
  96. VpuWriteReg(coreIdx, BIT_BUSY_FLAG, 1);
  97. VpuWriteReg(coreIdx, BIT_RUN_INDEX, instIdx);
  98. VpuWriteReg(coreIdx, BIT_RUN_COD_STD, cdcMode);
  99. VpuWriteReg(coreIdx, BIT_RUN_AUX_STD, auxMode);
  100. if (inst && inst->loggingEnable)
  101. vdi_log(coreIdx, cmd, 1);
  102. VpuWriteReg(coreIdx, BIT_RUN_COMMAND, cmd);
  103. }
  104. static void SetupCoda9Properties(Uint32 coreIdx, Uint32 productId)
  105. {
  106. VpuAttr* pAttr = &g_VpuCoreAttributes[coreIdx];
  107. Int32 val;
  108. char* pstr;
  109. /* Setup Attributes */
  110. pAttr = &g_VpuCoreAttributes[coreIdx];
  111. // Hardware version information
  112. val = VpuReadReg(coreIdx, VPU_PRODUCT_CODE_REGISTER);
  113. if ((val&0xff00) == 0x3200) val = 0x3200;
  114. val = VpuReadReg(coreIdx, DBG_CONFIG_REPORT_0);
  115. pstr = (char*)&val;
  116. pAttr->productName[0] = pstr[3];
  117. pAttr->productName[1] = pstr[2];
  118. pAttr->productName[2] = pstr[1];
  119. pAttr->productName[3] = pstr[0];
  120. pAttr->productName[4] = 0;
  121. pAttr->supportDecoders = (1<<STD_AVC) |
  122. (1<<STD_VC1) |
  123. (1<<STD_MPEG2) |
  124. (1<<STD_MPEG4) |
  125. (1<<STD_H263) |
  126. (1<<STD_AVS) |
  127. (1<<STD_DIV3) |
  128. (1<<STD_RV) |
  129. (1<<STD_THO) |
  130. (1<<STD_VP8);
  131. /* Encoder */
  132. pAttr->supportEncoders = (1<<STD_AVC) | (1<<STD_MPEG4) | (1<<STD_H263);
  133. /* WTL */
  134. if (productId == PRODUCT_ID_960 || productId == PRODUCT_ID_980) {
  135. pAttr->supportWTL = 1;
  136. }
  137. /* Tiled2Linear */
  138. pAttr->supportTiled2Linear = 1;
  139. /* Maptypes */
  140. pAttr->supportMapTypes = (1<<LINEAR_FRAME_MAP) |
  141. (1<<TILED_FRAME_V_MAP) |
  142. (1<<TILED_FRAME_H_MAP) |
  143. (1<<TILED_FIELD_V_MAP) |
  144. (1<<TILED_MIXED_V_MAP) |
  145. (1<<TILED_FRAME_MB_RASTER_MAP) |
  146. (1<<TILED_FIELD_MB_RASTER_MAP);
  147. if (productId == PRODUCT_ID_980) {
  148. pAttr->supportMapTypes |= (1<<TILED_FRAME_NO_BANK_MAP) |
  149. (1<<TILED_FIELD_NO_BANK_MAP);
  150. }
  151. /* Linear2Tiled */
  152. if (productId == PRODUCT_ID_960 || productId == PRODUCT_ID_980) {
  153. pAttr->supportLinear2Tiled = 1;
  154. }
  155. /* Framebuffer Cache */
  156. if (productId == PRODUCT_ID_960)
  157. pAttr->framebufferCacheType = FramebufCacheMaverickI;
  158. else if (productId == PRODUCT_ID_980)
  159. pAttr->framebufferCacheType = FramebufCacheMaverickII;
  160. else
  161. pAttr->framebufferCacheType = FramebufCacheNone;
  162. /* AXI 128bit Bus */
  163. pAttr->support128bitBus = FALSE;
  164. pAttr->supportEndianMask = (1<<VDI_LITTLE_ENDIAN) | (1<<VDI_BIG_ENDIAN) | (1<<VDI_32BIT_LITTLE_ENDIAN) | (1<<VDI_32BIT_BIG_ENDIAN);
  165. pAttr->supportBitstreamMode = (1<<BS_MODE_INTERRUPT) | (1<<BS_MODE_PIC_END);
  166. pAttr->bitstreamBufferMargin = VPU_GBU_SIZE;
  167. pAttr->numberOfMemProtectRgns = 6;
  168. }
  169. Uint32 Coda9VpuGetProductId(Uint32 coreIdx)
  170. {
  171. Uint32 productId;
  172. Uint32 val;
  173. val = VpuReadReg(coreIdx, VPU_PRODUCT_CODE_REGISTER);
  174. if (val == BODA950_CODE)
  175. productId = PRODUCT_ID_950;
  176. else if (val == CODA960_CODE)
  177. productId = PRODUCT_ID_960;
  178. else if (val == CODA980_CODE)
  179. productId = PRODUCT_ID_980;
  180. else
  181. productId = PRODUCT_ID_NONE;
  182. if (productId != PRODUCT_ID_NONE)
  183. SetupCoda9Properties(coreIdx, productId);
  184. return productId;
  185. }
  186. RetCode Coda9VpuGetVersion(Uint32 coreIdx, Uint32* versionInfo, Uint32* revision)
  187. {
  188. /* Get Firmware version */
  189. VpuWriteReg(coreIdx, RET_FW_VER_NUM , 0);
  190. Coda9BitIssueCommand(coreIdx, NULL, FIRMWARE_GET);
  191. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1)
  192. return RETCODE_VPU_RESPONSE_TIMEOUT;
  193. if (versionInfo != NULL) {
  194. *versionInfo = VpuReadReg(coreIdx, RET_FW_VER_NUM);
  195. }
  196. if (revision != NULL) {
  197. *revision = VpuReadReg(coreIdx, RET_FW_CODE_REV);
  198. }
  199. return RETCODE_SUCCESS;
  200. }
  201. RetCode Coda9VpuInit(Uint32 coreIdx, void* firmware, Uint32 size)
  202. {
  203. Uint32 data;
  204. vpu_buffer_t vb;
  205. PhysicalAddress tempBuffer;
  206. PhysicalAddress paraBuffer;
  207. PhysicalAddress codeBuffer;
  208. vdi_get_common_memory((unsigned long)coreIdx, &vb);
  209. codeBuffer = vb.phys_addr;
  210. tempBuffer = codeBuffer + CODE_BUF_SIZE;
  211. paraBuffer = tempBuffer + TEMP_BUF_SIZE;
  212. BitLoadFirmware(coreIdx, codeBuffer, (const Uint16 *)firmware, size);
  213. /* Clear registers */
  214. if (vdi_read_register(coreIdx, BIT_CUR_PC) == 0) {
  215. Uint32 i;
  216. for (i=0; i<64; i++) {
  217. vdi_write_register(coreIdx, (i*4) + 0x100, 0x0);
  218. }
  219. }
  220. VpuWriteReg(coreIdx, BIT_PARA_BUF_ADDR, paraBuffer);
  221. VpuWriteReg(coreIdx, BIT_CODE_BUF_ADDR, codeBuffer);
  222. VpuWriteReg(coreIdx, BIT_TEMP_BUF_ADDR, tempBuffer);
  223. VpuWriteReg(coreIdx, BIT_BIT_STREAM_CTRL, VPU_STREAM_ENDIAN);
  224. VpuWriteReg(coreIdx, BIT_FRAME_MEM_CTRL, CBCR_INTERLEAVE<<2|VPU_FRAME_ENDIAN); // Interleave bit position is modified
  225. VpuWriteReg(coreIdx, BIT_BIT_STREAM_PARAM, 0);
  226. VpuWriteReg(coreIdx, BIT_AXI_SRAM_USE, 0);
  227. VpuWriteReg(coreIdx, BIT_INT_ENABLE, 0);
  228. VpuWriteReg(coreIdx, BIT_ROLLBACK_STATUS, 0);
  229. data = (1<<INT_BIT_BIT_BUF_FULL);
  230. data |= (1<<INT_BIT_BIT_BUF_EMPTY);
  231. data |= (1<<INT_BIT_DEC_MB_ROWS);
  232. data |= (1<<INT_BIT_SEQ_INIT);
  233. data |= (1<<INT_BIT_DEC_FIELD);
  234. data |= (1<<INT_BIT_PIC_RUN);
  235. VpuWriteReg(coreIdx, BIT_INT_ENABLE, data);
  236. VpuWriteReg(coreIdx, BIT_INT_CLEAR, 0x1);
  237. VpuWriteReg(coreIdx, BIT_BUSY_FLAG, 0x1);
  238. VpuWriteReg(coreIdx, BIT_CODE_RESET, 1);
  239. VpuWriteReg(coreIdx, BIT_CODE_RUN, 1);
  240. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1)
  241. return RETCODE_VPU_RESPONSE_TIMEOUT;
  242. return RETCODE_SUCCESS;
  243. }
  244. RetCode Coda9VpuReInit(Uint32 coreIdx, void* firmware, Uint32 size)
  245. {
  246. vpu_buffer_t vb;
  247. PhysicalAddress tempBuffer;
  248. PhysicalAddress paraBuffer;
  249. PhysicalAddress codeBuffer;
  250. PhysicalAddress oldCodeBuffer;
  251. vdi_get_common_memory((unsigned long)coreIdx, &vb);
  252. codeBuffer = vb.phys_addr;
  253. tempBuffer = codeBuffer + CODE_BUF_SIZE;
  254. paraBuffer = tempBuffer + TEMP_BUF_SIZE;
  255. oldCodeBuffer = VpuReadReg(coreIdx, BIT_CODE_BUF_ADDR);
  256. VpuWriteReg(coreIdx, BIT_PARA_BUF_ADDR, paraBuffer);
  257. VpuWriteReg(coreIdx, BIT_CODE_BUF_ADDR, codeBuffer);
  258. VpuWriteReg(coreIdx, BIT_TEMP_BUF_ADDR, tempBuffer);
  259. if (oldCodeBuffer != codeBuffer) {
  260. LoadBitCode(coreIdx, codeBuffer, (const Uint16 *)firmware, size);
  261. }
  262. return RETCODE_SUCCESS;
  263. }
  264. Uint32 Coda9VpuIsInit(Uint32 coreIdx)
  265. {
  266. Uint32 pc;
  267. pc = VpuReadReg(coreIdx, BIT_CUR_PC);
  268. return pc;
  269. }
  270. Int32 Coda9VpuIsBusy(Uint32 coreIdx)
  271. {
  272. return VpuReadReg(coreIdx, BIT_BUSY_FLAG);
  273. }
  274. Int32 Coda9VpuWaitInterrupt(CodecInst* handle, Int32 timeout)
  275. {
  276. Int32 reason = 0;
  277. reason = vdi_wait_interrupt(handle->coreIdx, timeout, BIT_INT_REASON);
  278. if (reason != INTERRUPT_TIMEOUT_VALUE) {
  279. VpuWriteReg(handle->coreIdx, BIT_INT_CLEAR, 1); // clear HW signal
  280. }
  281. return reason;
  282. }
  283. RetCode Coda9VpuClearInterrupt(Uint32 coreIdx)
  284. {
  285. VpuWriteReg(coreIdx, BIT_INT_REASON, 0); // tell to F/W that HOST received an interrupt.
  286. return RETCODE_SUCCESS;
  287. }
  288. RetCode Coda9VpuReset(Uint32 coreIdx, SWResetMode resetMode)
  289. {
  290. Uint32 cmd;
  291. Int32 productId = Coda9VpuGetProductId(coreIdx);
  292. if (productId == PRODUCT_ID_960 || productId == PRODUCT_ID_980) {
  293. if (resetMode != SW_RESET_ON_BOOT) {
  294. cmd = VpuReadReg(coreIdx, BIT_RUN_COMMAND);
  295. if (cmd == DEC_SEQ_INIT || cmd == PIC_RUN) {
  296. if (VpuReadReg(coreIdx, BIT_BUSY_FLAG) || VpuReadReg(coreIdx, BIT_INT_REASON)) {
  297. #define MBC_SET_SUBBLK_EN (MBC_BASE+0xA0) // subblk_man_mode[20] cr_subblk_man_en[19:0]
  298. // stop all of pipeline
  299. VpuWriteReg(coreIdx, MBC_SET_SUBBLK_EN, ((1<<20) | 0));
  300. // force to set the end of Bitstream to be decoded.
  301. cmd = VpuReadReg(coreIdx, BIT_BIT_STREAM_PARAM);
  302. cmd |= 1 << 2;
  303. VpuWriteReg(coreIdx, BIT_BIT_STREAM_PARAM, cmd);
  304. cmd = VpuReadReg(coreIdx, BIT_RD_PTR);
  305. VpuWriteReg(coreIdx, BIT_WR_PTR, cmd);
  306. cmd = vdi_wait_interrupt(coreIdx, __VPU_BUSY_TIMEOUT, BIT_INT_REASON);
  307. if ((Int32)cmd != INTERRUPT_TIMEOUT_VALUE) {
  308. VpuWriteReg(coreIdx, BIT_INT_REASON, 0);
  309. VpuWriteReg(coreIdx, BIT_INT_CLEAR, 1); // clear HW signal
  310. }
  311. // now all of hardwares would be stop.
  312. }
  313. }
  314. }
  315. // Waiting for completion of BWB transaction first
  316. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, GDI_BWB_STATUS) == -1) {
  317. vdi_log(coreIdx, 0x10, 2);
  318. return RETCODE_VPU_RESPONSE_TIMEOUT;
  319. }
  320. // Waiting for completion of bus transaction
  321. // Step1 : No more request
  322. VpuWriteReg(coreIdx, GDI_BUS_CTRL, 0x11); // no more request {3'b0,no_more_req_sec,3'b0,no_more_req}
  323. // Step2 : Waiting for completion of bus transaction
  324. if (vdi_wait_bus_busy(coreIdx, __VPU_BUSY_TIMEOUT, GDI_BUS_STATUS) == -1) {
  325. VpuWriteReg(coreIdx, GDI_BUS_CTRL, 0x00);
  326. vdi_log(coreIdx, 0x10, 2);
  327. return RETCODE_VPU_RESPONSE_TIMEOUT;
  328. }
  329. cmd = 0;
  330. // Software Reset Trigger
  331. if (resetMode != SW_RESET_ON_BOOT)
  332. cmd = VPU_SW_RESET_BPU_CORE | VPU_SW_RESET_BPU_BUS;
  333. cmd |= VPU_SW_RESET_VCE_CORE | VPU_SW_RESET_VCE_BUS;
  334. if (resetMode == SW_RESET_ON_BOOT)
  335. cmd |= VPU_SW_RESET_GDI_CORE | VPU_SW_RESET_GDI_BUS;// If you reset GDI, tiled map should be reconfigured
  336. VpuWriteReg(coreIdx, BIT_SW_RESET, cmd);
  337. // wait until reset is done
  338. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, BIT_SW_RESET_STATUS) == -1) {
  339. VpuWriteReg(coreIdx, BIT_SW_RESET, 0x00);
  340. VpuWriteReg(coreIdx, GDI_BUS_CTRL, 0x00);
  341. vdi_log(coreIdx, 0x10, 2);
  342. return RETCODE_VPU_RESPONSE_TIMEOUT;
  343. }
  344. VpuWriteReg(coreIdx, BIT_SW_RESET, 0);
  345. // Step3 : must clear GDI_BUS_CTRL after done SW_RESET
  346. VpuWriteReg(coreIdx, GDI_BUS_CTRL, 0x00);
  347. }
  348. else {
  349. vdi_log(coreIdx, 0x10, 0);
  350. return RETCODE_NOT_FOUND_VPU_DEVICE;
  351. }
  352. return RETCODE_SUCCESS;
  353. }
  354. RetCode Coda9VpuSleepWake(Uint32 coreIdx, int iSleepWake, const Uint16* code, Uint32 size)
  355. {
  356. static unsigned int regBk[64];
  357. int i=0;
  358. const Uint16* bit_code = NULL;
  359. if (code && size > 0)
  360. bit_code = code;
  361. if (!bit_code)
  362. return RETCODE_INVALID_PARAM;
  363. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1) {
  364. return RETCODE_VPU_RESPONSE_TIMEOUT;
  365. }
  366. if(iSleepWake==1)
  367. {
  368. for ( i = 0 ; i < 64 ; i++)
  369. regBk[i] = VpuReadReg(coreIdx, BIT_BASE + 0x100 + (i * 4));
  370. }
  371. else
  372. {
  373. VpuWriteReg(coreIdx, BIT_CODE_RUN, 0);
  374. for ( i = 0 ; i < 64 ; i++)
  375. VpuWriteReg(coreIdx, BIT_BASE + 0x100 + (i * 4), regBk[i]);
  376. VpuWriteReg(coreIdx, BIT_BUSY_FLAG, 1);
  377. VpuWriteReg(coreIdx, BIT_CODE_RESET, 1);
  378. VpuWriteReg(coreIdx, BIT_CODE_RUN, 1);
  379. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1) {
  380. return RETCODE_VPU_RESPONSE_TIMEOUT;
  381. }
  382. }
  383. return RETCODE_SUCCESS;
  384. }
  385. static RetCode SetupDecCodecInstance(Int32 productId, CodecInst* pCodec)
  386. {
  387. DecInfo* pDecInfo = &pCodec->CodecInfo->decInfo;
  388. pDecInfo->streamRdPtrRegAddr = BIT_RD_PTR;
  389. pDecInfo->streamWrPtrRegAddr = BIT_WR_PTR;
  390. pDecInfo->frameDisplayFlagRegAddr = BIT_FRM_DIS_FLG;
  391. pDecInfo->currentPC = BIT_CUR_PC;
  392. pDecInfo->busyFlagAddr = BIT_BUSY_FLAG;
  393. if (productId == PRODUCT_ID_960) {
  394. pDecInfo->dramCfg.rasBit = EM_RAS;
  395. pDecInfo->dramCfg.casBit = EM_CAS;
  396. pDecInfo->dramCfg.bankBit = EM_BANK;
  397. pDecInfo->dramCfg.busBit = EM_WIDTH;
  398. }
  399. return RETCODE_SUCCESS;
  400. }
  401. static RetCode SetupEncCodecInstance(Int32 productId, CodecInst* pCodec)
  402. {
  403. EncInfo* pEncInfo = &pCodec->CodecInfo->encInfo;
  404. pEncInfo->streamRdPtrRegAddr = BIT_RD_PTR;
  405. pEncInfo->streamWrPtrRegAddr = BIT_WR_PTR;
  406. pEncInfo->currentPC = BIT_CUR_PC;
  407. pEncInfo->busyFlagAddr = BIT_BUSY_FLAG;
  408. if (productId == PRODUCT_ID_960) {
  409. pEncInfo->dramCfg.rasBit = EM_RAS;
  410. pEncInfo->dramCfg.casBit = EM_CAS;
  411. pEncInfo->dramCfg.bankBit = EM_BANK;
  412. pEncInfo->dramCfg.busBit = EM_WIDTH;
  413. }
  414. return RETCODE_SUCCESS;
  415. }
  416. RetCode Coda9VpuBuildUpDecParam(CodecInst* pCodec, DecOpenParam* param)
  417. {
  418. RetCode ret = RETCODE_SUCCESS;
  419. Uint32 coreIdx;
  420. Uint32 productId;
  421. DecInfo* pDecInfo = &pCodec->CodecInfo->decInfo;
  422. coreIdx = pCodec->coreIdx;
  423. productId = Coda9VpuGetProductId(coreIdx);
  424. if ((ret=SetupDecCodecInstance(productId, pCodec)) != RETCODE_SUCCESS)
  425. return ret;
  426. if (param->vbWork.size) {
  427. pDecInfo->vbWork = param->vbWork;
  428. pDecInfo->workBufferAllocExt = 1;
  429. }
  430. else {
  431. pDecInfo->vbWork.size = WORK_BUF_SIZE;
  432. if (pCodec->codecMode == AVC_DEC)
  433. pDecInfo->vbWork.size += PS_SAVE_SIZE;
  434. if (vdi_allocate_dma_memory(pCodec->coreIdx, &pDecInfo->vbWork) < 0)
  435. return RETCODE_INSUFFICIENT_RESOURCE;
  436. param->vbWork = pDecInfo->vbWork;
  437. pDecInfo->workBufferAllocExt = 0;
  438. }
  439. if (productId == PRODUCT_ID_960) {
  440. pDecInfo->dramCfg.bankBit = EM_BANK;
  441. pDecInfo->dramCfg.casBit = EM_CAS;
  442. pDecInfo->dramCfg.rasBit = EM_RAS;
  443. pDecInfo->dramCfg.busBit = EM_WIDTH;
  444. }
  445. else {
  446. /* CODA980 */
  447. pDecInfo->targetSubLayerId = AVC_MAX_SUB_LAYER_ID;
  448. }
  449. return ret;
  450. }
  451. RetCode Coda9VpuDecInitSeq(DecHandle handle)
  452. {
  453. CodecInst* pCodecInst = (CodecInst*)handle;
  454. DecInfo* pDecInfo = &pCodecInst->CodecInfo->decInfo;
  455. Uint32 val = 0;
  456. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_BB_START, pDecInfo->streamBufStartAddr);
  457. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_BB_SIZE, pDecInfo->streamBufSize / 1024); // size in KBytes
  458. if(pDecInfo->userDataEnable == TRUE) {
  459. val = 0;
  460. val |= (pDecInfo->userDataReportMode << 10);
  461. val |= (pDecInfo->userDataEnable << 5);
  462. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_USER_DATA_OPTION, val);
  463. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_USER_DATA_BASE_ADDR, pDecInfo->userDataBufAddr);
  464. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_USER_DATA_BUF_SIZE, pDecInfo->userDataBufSize);
  465. }
  466. else {
  467. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_USER_DATA_OPTION, 0);
  468. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_USER_DATA_BASE_ADDR, 0);
  469. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_USER_DATA_BUF_SIZE, 0);
  470. }
  471. val = 0;
  472. val |= (pDecInfo->reorderEnable<<1) & 0x2;
  473. val |= (pDecInfo->openParam.mp4DeblkEnable & 0x1);
  474. val |= (pDecInfo->avcErrorConcealMode << 2);
  475. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_OPTION, val);
  476. switch(pCodecInst->codecMode) {
  477. case VC1_DEC:
  478. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_VC1_STREAM_FMT, (0 << 3) & 0x08);
  479. break;
  480. case MP4_DEC:
  481. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_MP4_ASP_CLASS, (VPU_GMC_PROCESS_METHOD<<3)|pDecInfo->openParam.mp4Class);
  482. break;
  483. case AVC_DEC:
  484. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_X264_MV_EN, VPU_AVC_X264_SUPPORT);
  485. break;
  486. }
  487. if( pCodecInst->codecMode == AVC_DEC )
  488. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_SPP_CHUNK_SIZE, VPU_GBU_SIZE);
  489. VpuWriteReg(pCodecInst->coreIdx, pDecInfo->streamWrPtrRegAddr, pDecInfo->streamWrPtr);
  490. VpuWriteReg(pCodecInst->coreIdx, pDecInfo->streamRdPtrRegAddr, pDecInfo->streamRdPtr);
  491. if (pCodecInst->productId == PRODUCT_ID_980 || pCodecInst->productId == PRODUCT_ID_960) {
  492. pDecInfo->streamEndflag &= ~(3<<3);
  493. if (pDecInfo->openParam.bitstreamMode == BS_MODE_PIC_END)
  494. pDecInfo->streamEndflag |= (2<<3);
  495. else { // Interrupt Mode
  496. if (pDecInfo->seqInitEscape) {
  497. pDecInfo->streamEndflag |= (2<<3);
  498. }
  499. }
  500. }
  501. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_PARAM, pDecInfo->streamEndflag);
  502. val = pDecInfo->openParam.streamEndian;
  503. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_CTRL, val);
  504. if (pCodecInst->productId == PRODUCT_ID_980) {
  505. val = 0;
  506. val |= (pDecInfo->openParam.bwbEnable<<15);
  507. val |= (pDecInfo->wtlMode<<17)|(pDecInfo->tiled2LinearMode<<13)|(FORMAT_420<<6);
  508. val |= ((pDecInfo->openParam.cbcrInterleave)<<2); // Interleave bit position is modified
  509. val |= pDecInfo->openParam.frameEndian;
  510. val |= pDecInfo->openParam.nv21<<3;
  511. VpuWriteReg(pCodecInst->coreIdx, BIT_FRAME_MEM_CTRL, val);
  512. }
  513. else if (pCodecInst->productId == PRODUCT_ID_960) {
  514. val = 0;
  515. val |= (pDecInfo->wtlEnable<<17);
  516. val |= (pDecInfo->openParam.bwbEnable<<12);
  517. val |= ((pDecInfo->openParam.cbcrInterleave)<<2); // Interleave bit position is modified
  518. val |= pDecInfo->openParam.frameEndian;
  519. VpuWriteReg(pCodecInst->coreIdx, BIT_FRAME_MEM_CTRL, val);
  520. }
  521. else {
  522. return RETCODE_NOT_FOUND_VPU_DEVICE;
  523. }
  524. VpuWriteReg(pCodecInst->coreIdx, pDecInfo->frameDisplayFlagRegAddr, 0);
  525. Coda9BitIssueCommand(pCodecInst->coreIdx, pCodecInst, DEC_SEQ_INIT);
  526. return RETCODE_SUCCESS;
  527. }
  528. RetCode Coda9VpuFiniSeq(CodecInst* instance)
  529. {
  530. Coda9BitIssueCommand(instance->coreIdx, instance, DEC_SEQ_END);
  531. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1) {
  532. return RETCODE_VPU_RESPONSE_TIMEOUT;
  533. }
  534. return RETCODE_SUCCESS;
  535. }
  536. RetCode Coda9VpuDecode(CodecInst* instance, DecParam* param)
  537. {
  538. CodecInst* pCodecInst;
  539. DecInfo* pDecInfo;
  540. Uint32 rotMir;
  541. Int32 val;
  542. vpu_instance_pool_t *vip;
  543. pCodecInst = instance;
  544. pDecInfo = &pCodecInst->CodecInfo->decInfo;
  545. vip = (vpu_instance_pool_t *)vdi_get_instance_pool(pCodecInst->coreIdx);
  546. if (!vip) {
  547. return RETCODE_INVALID_HANDLE;
  548. }
  549. rotMir = 0;
  550. if (pDecInfo->rotationEnable) {
  551. rotMir |= 0x10; // Enable rotator
  552. switch (pDecInfo->rotationAngle) {
  553. case 0:
  554. rotMir |= 0x0;
  555. break;
  556. case 90:
  557. rotMir |= 0x1;
  558. break;
  559. case 180:
  560. rotMir |= 0x2;
  561. break;
  562. case 270:
  563. rotMir |= 0x3;
  564. break;
  565. }
  566. }
  567. if (pDecInfo->mirrorEnable) {
  568. rotMir |= 0x10; // Enable rotator
  569. switch (pDecInfo->mirrorDirection) {
  570. case MIRDIR_NONE :
  571. rotMir |= 0x0;
  572. break;
  573. case MIRDIR_VER :
  574. rotMir |= 0x4;
  575. break;
  576. case MIRDIR_HOR :
  577. rotMir |= 0x8;
  578. break;
  579. case MIRDIR_HOR_VER :
  580. rotMir |= 0xc;
  581. break;
  582. }
  583. }
  584. if (pDecInfo->tiled2LinearEnable) {
  585. rotMir |= 0x10;
  586. }
  587. if (pDecInfo->deringEnable) {
  588. rotMir |= 0x20; // Enable Dering Filter
  589. }
  590. if (rotMir && !pDecInfo->rotatorOutputValid) {
  591. return RETCODE_ROTATOR_OUTPUT_NOT_SET;
  592. }
  593. VpuWriteReg(pCodecInst->coreIdx, RET_DEC_PIC_CROP_LEFT_RIGHT, 0); // frame crop information(left, right)
  594. VpuWriteReg(pCodecInst->coreIdx, RET_DEC_PIC_CROP_TOP_BOTTOM, 0); // frame crop information(top, bottom)
  595. if (pCodecInst->productId == PRODUCT_ID_960) {
  596. if (pDecInfo->mapType>LINEAR_FRAME_MAP && pDecInfo->mapType<=TILED_MIXED_V_MAP) {
  597. SetTiledFrameBase(pCodecInst->coreIdx, pDecInfo->mapCfg.tiledBaseAddr);
  598. }
  599. else {
  600. SetTiledFrameBase(pCodecInst->coreIdx, 0);
  601. }
  602. }
  603. if (pDecInfo->mapType != LINEAR_FRAME_MAP && pDecInfo->mapType != LINEAR_FIELD_MAP) {
  604. val = SetTiledMapType(pCodecInst->coreIdx, &pDecInfo->mapCfg, pDecInfo->mapType,
  605. (pDecInfo->stride > pDecInfo->frameBufferHeight)?pDecInfo->stride: pDecInfo->frameBufferHeight,
  606. pDecInfo->openParam.cbcrInterleave, &pDecInfo->dramCfg);
  607. } else {
  608. val = SetTiledMapType(pCodecInst->coreIdx, &pDecInfo->mapCfg, pDecInfo->mapType,
  609. pDecInfo->stride, pDecInfo->openParam.cbcrInterleave, &pDecInfo->dramCfg);
  610. }
  611. if (val == 0) {
  612. return RETCODE_INVALID_PARAM;
  613. }
  614. if (rotMir & 0x30) { // rotator or dering or tiled2linear enabled
  615. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_MODE, rotMir);
  616. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_INDEX, pDecInfo->rotatorOutput.myIndex);
  617. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_ADDR_Y, pDecInfo->rotatorOutput.bufY);
  618. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_ADDR_CB, pDecInfo->rotatorOutput.bufCb);
  619. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_ADDR_CR, pDecInfo->rotatorOutput.bufCr);
  620. if (pCodecInst->productId == PRODUCT_ID_980) {
  621. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_BOTTOM_Y, pDecInfo->rotatorOutput.bufYBot);
  622. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_BOTTOM_CB, pDecInfo->rotatorOutput.bufCbBot);
  623. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_BOTTOM_CR, pDecInfo->rotatorOutput.bufCrBot);
  624. }
  625. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_STRIDE, pDecInfo->rotatorStride);
  626. }
  627. else {
  628. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_MODE, rotMir);
  629. }
  630. if(pDecInfo->userDataEnable) {
  631. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_USER_DATA_BASE_ADDR, pDecInfo->userDataBufAddr);
  632. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_USER_DATA_BUF_SIZE, pDecInfo->userDataBufSize);
  633. }
  634. else {
  635. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_USER_DATA_BASE_ADDR, 0);
  636. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_USER_DATA_BUF_SIZE, 0);
  637. }
  638. val = 0;
  639. if (param->iframeSearchEnable == TRUE) { // if iframeSearch is Enable, other bit is ignore;
  640. val |= (pDecInfo->userDataReportMode <<10);
  641. if (pCodecInst->codecMode == AVC_DEC || pCodecInst->codecMode == VC1_DEC) {
  642. if (param->iframeSearchEnable==1)
  643. val |= (1<< 11) | (1<<2);
  644. else if (param->iframeSearchEnable==2)
  645. val |= (1<<2);
  646. }
  647. else {
  648. val |= (( param->iframeSearchEnable &0x1) << 2 );
  649. }
  650. }
  651. else {
  652. val |= (pDecInfo->userDataReportMode <<10);
  653. val |= (pDecInfo->userDataEnable << 5);
  654. val |= (param->skipframeMode << 3);
  655. }
  656. if (pCodecInst->productId == PRODUCT_ID_980) {
  657. if (pCodecInst->codecMode == AVC_DEC && pDecInfo->lowDelayInfo.lowDelayEn) {
  658. val |= (pDecInfo->lowDelayInfo.lowDelayEn <<18 );
  659. }
  660. }
  661. if (pCodecInst->codecMode == MP2_DEC) {
  662. val |= ((param->DecStdParam.mp2PicFlush&1)<<15);
  663. }
  664. if (pCodecInst->codecMode == RV_DEC) {
  665. val |= ((param->DecStdParam.rvDbkMode&0x0f)<<16);
  666. }
  667. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_OPTION, val);
  668. if (pCodecInst->productId == PRODUCT_ID_980) {
  669. if (pDecInfo->lowDelayInfo.lowDelayEn == TRUE) {
  670. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_NUM_ROWS, pDecInfo->lowDelayInfo.numRows);
  671. }
  672. else {
  673. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_NUM_ROWS, 0);
  674. }
  675. }
  676. val = 0;
  677. val = (
  678. (pDecInfo->secAxiInfo.u.coda9.useBitEnable&0x01)<<0 |
  679. (pDecInfo->secAxiInfo.u.coda9.useIpEnable&0x01)<<1 |
  680. (pDecInfo->secAxiInfo.u.coda9.useDbkYEnable&0x01)<<2 |
  681. (pDecInfo->secAxiInfo.u.coda9.useDbkCEnable&0x01)<<3 |
  682. (pDecInfo->secAxiInfo.u.coda9.useOvlEnable&0x01)<<4 |
  683. (pDecInfo->secAxiInfo.u.coda9.useBtpEnable&0x01)<<5 |
  684. (pDecInfo->secAxiInfo.u.coda9.useBitEnable&0x01)<<8 |
  685. (pDecInfo->secAxiInfo.u.coda9.useIpEnable&0x01)<<9 |
  686. (pDecInfo->secAxiInfo.u.coda9.useDbkYEnable&0x01)<<10 |
  687. (pDecInfo->secAxiInfo.u.coda9.useDbkCEnable&0x01)<<11 |
  688. (pDecInfo->secAxiInfo.u.coda9.useOvlEnable&0x01)<<12 |
  689. (pDecInfo->secAxiInfo.u.coda9.useBtpEnable&0x01)<<13 );
  690. VpuWriteReg(pCodecInst->coreIdx, BIT_AXI_SRAM_USE, val);
  691. VpuWriteReg(pCodecInst->coreIdx, pDecInfo->streamWrPtrRegAddr, pDecInfo->streamWrPtr);
  692. VpuWriteReg(pCodecInst->coreIdx, pDecInfo->streamRdPtrRegAddr, pDecInfo->streamRdPtr);
  693. pDecInfo->streamEndflag &= ~(3<<3);
  694. if (pDecInfo->openParam.bitstreamMode == BS_MODE_PIC_END)
  695. pDecInfo->streamEndflag |= (2<<3);
  696. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_PARAM, pDecInfo->streamEndflag);
  697. if (pCodecInst->productId == PRODUCT_ID_980) {
  698. val = 0;
  699. val |= (pDecInfo->openParam.bwbEnable<<15);
  700. val |= (pDecInfo->wtlMode<<17)|(pDecInfo->tiled2LinearMode<<13)|(pDecInfo->mapType<<9)|(FORMAT_420<<6);
  701. if (pDecInfo->openParam.cbcrInterleave == 1)
  702. val |= pDecInfo->openParam.nv21 << 3;
  703. }
  704. else if (pCodecInst->productId == PRODUCT_ID_960) {
  705. val = 0;
  706. val |= (pDecInfo->wtlEnable<<17);
  707. val |= (pDecInfo->openParam.bwbEnable<<12);
  708. if (pDecInfo->mapType) {
  709. if (pDecInfo->mapType == TILED_FRAME_MB_RASTER_MAP || pDecInfo->mapType == TILED_FIELD_MB_RASTER_MAP)
  710. val |= (pDecInfo->tiled2LinearEnable<<11)|(0x03<<9)|(FORMAT_420<<6);
  711. else
  712. val |= (pDecInfo->tiled2LinearEnable<<11)|(0x02<<9)|(FORMAT_420<<6);
  713. }
  714. }
  715. else {
  716. return RETCODE_NOT_FOUND_VPU_DEVICE;
  717. }
  718. val |= ((pDecInfo->openParam.cbcrInterleave)<<2); // Interleave bit position is modified
  719. val |= pDecInfo->openParam.frameEndian;
  720. VpuWriteReg(pCodecInst->coreIdx, BIT_FRAME_MEM_CTRL, val);
  721. val = pDecInfo->openParam.streamEndian;
  722. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_CTRL, val);
  723. if (PRODUCT_ID_980 == pCodecInst->productId && AVC_DEC == pCodecInst->codecMode) {
  724. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_SVC_INFO, pDecInfo->targetSubLayerId);
  725. }
  726. Coda9BitIssueCommand(pCodecInst->coreIdx, pCodecInst, PIC_RUN);
  727. return RETCODE_SUCCESS;
  728. }
  729. RetCode Coda9VpuDecGetResult(CodecInst* instance, DecOutputInfo* result)
  730. {
  731. CodecInst* pCodecInst;
  732. DecInfo* pDecInfo;
  733. Uint32 val = 0;
  734. pCodecInst = instance;
  735. pDecInfo = &pCodecInst->CodecInfo->decInfo;
  736. if (pCodecInst->loggingEnable)
  737. vdi_log(pCodecInst->coreIdx, PIC_RUN, 0);
  738. result->warnInfo = 0;
  739. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_SUCCESS);
  740. result->decodingSuccess = val;
  741. if (result->decodingSuccess & (1UL<<31)) {
  742. return RETCODE_MEMORY_ACCESS_VIOLATION;
  743. }
  744. if( pCodecInst->codecMode == AVC_DEC ) {
  745. result->notSufficientPsBuffer = (val >> 3) & 0x1;
  746. result->notSufficientSliceBuffer = (val >> 2) & 0x1;
  747. result->refMissingFrameFlag = (val>>21) & 0x1;
  748. }
  749. result->chunkReuseRequired = 0;
  750. if (pDecInfo->openParam.bitstreamMode == BS_MODE_PIC_END) {
  751. switch (pCodecInst->codecMode) {
  752. case AVC_DEC:
  753. result->chunkReuseRequired = ((val >> 16) & 0x01); // in case of NPF frame
  754. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_DECODED_IDX);
  755. if (val == (Uint32)-1) {
  756. result->chunkReuseRequired = TRUE;
  757. }
  758. break;
  759. case MP2_DEC:
  760. case MP4_DEC:
  761. result->chunkReuseRequired = ((val >> 16) & 0x01);
  762. break;
  763. default:
  764. break;
  765. }
  766. }
  767. result->indexFrameDecoded = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_DECODED_IDX);
  768. result->indexFrameDisplay = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_DISPLAY_IDX);
  769. if (pDecInfo->mapType == LINEAR_FRAME_MAP) {
  770. result->indexFrameDecodedForTiled = -1;
  771. result->indexFrameDisplayForTiled = -1;
  772. }
  773. else {
  774. result->indexFrameDecodedForTiled = result->indexFrameDecoded;
  775. result->indexFrameDisplayForTiled = result->indexFrameDisplay;
  776. }
  777. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_SIZE); // decoding picture size
  778. result->decPicWidth = (val>>16) & 0xFFFF;
  779. result->decPicHeight = (val) & 0xFFFF;
  780. if (result->indexFrameDecoded >= 0 && result->indexFrameDecoded < MAX_GDI_IDX) {
  781. switch (pCodecInst->codecMode) {
  782. case VPX_DEC:
  783. if ( pCodecInst->codecModeAux == VPX_AUX_VP8 ) {
  784. // VP8 specific header information
  785. // h_scale[31:30] v_scale[29:28] pic_width[27:14] pic_height[13:0]
  786. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_VP8_SCALE_INFO);
  787. result->vp8ScaleInfo.hScaleFactor = (val >> 30) & 0x03;
  788. result->vp8ScaleInfo.vScaleFactor = (val >> 28) & 0x03;
  789. result->vp8ScaleInfo.picWidth = (val >> 14) & 0x3FFF;
  790. result->vp8ScaleInfo.picHeight = (val >> 0) & 0x3FFF;
  791. // ref_idx_gold[31:24], ref_idx_altr[23:16], ref_idx_last[15: 8],
  792. // version_number[3:1], show_frame[0]
  793. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_VP8_PIC_REPORT);
  794. result->vp8PicInfo.refIdxGold = (val >> 24) & 0x0FF;
  795. result->vp8PicInfo.refIdxAltr = (val >> 16) & 0x0FF;
  796. result->vp8PicInfo.refIdxLast = (val >> 8) & 0x0FF;
  797. result->vp8PicInfo.versionNumber = (val >> 1) & 0x07;
  798. result->vp8PicInfo.showFrame = (val >> 0) & 0x01;
  799. }
  800. break;
  801. case AVC_DEC:
  802. case AVS_DEC:
  803. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_CROP_LEFT_RIGHT); // frame crop information(left, right)
  804. pDecInfo->initialInfo.picCropRect.left = (val>>16) & 0xffff;
  805. pDecInfo->initialInfo.picCropRect.right = pDecInfo->initialInfo.picWidth - (val&0xffff);
  806. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_CROP_TOP_BOTTOM); // frame crop information(top, bottom)
  807. pDecInfo->initialInfo.picCropRect.top = (val>>16) & 0xffff;
  808. pDecInfo->initialInfo.picCropRect.bottom = pDecInfo->initialInfo.picHeight - (val&0xffff);
  809. break;
  810. case MP2_DEC:
  811. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_MP2_BAR_LEFT_RIGHT);
  812. pDecInfo->initialInfo.mp2BardataInfo.barLeft = ((val>>16) & 0xFFFF);
  813. pDecInfo->initialInfo.mp2BardataInfo.barRight = (val&0xFFFF);
  814. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_MP2_BAR_TOP_BOTTOM);
  815. pDecInfo->initialInfo.mp2BardataInfo.barTop = ((val>>16) & 0xFFFF);
  816. pDecInfo->initialInfo.mp2BardataInfo.barBottom = (val&0xFFFF);
  817. result->mp2BardataInfo = pDecInfo->initialInfo.mp2BardataInfo;
  818. result->mp2PicDispExtInfo.offsetNum = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_MP2_OFFSET_NUM);
  819. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_MP2_OFFSET1);
  820. result->mp2PicDispExtInfo.horizontalOffset1 = (Int16) (val >> 16) & 0xFFFF;
  821. result->mp2PicDispExtInfo.verticalOffset1 = (Int16) (val & 0xFFFF);
  822. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_MP2_OFFSET2);
  823. result->mp2PicDispExtInfo.horizontalOffset2 = (Int16) (val >> 16) & 0xFFFF;
  824. result->mp2PicDispExtInfo.verticalOffset2 = (Int16) (val & 0xFFFF);
  825. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_MP2_OFFSET3);
  826. result->mp2PicDispExtInfo.horizontalOffset3 = (Int16) (val >> 16) & 0xFFFF;
  827. result->mp2PicDispExtInfo.verticalOffset3 = (Int16) (val & 0xFFFF);
  828. break;
  829. }
  830. }
  831. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_TYPE);
  832. result->interlacedFrame = (val >> 18) & 0x1;
  833. result->topFieldFirst = (val >> 21) & 0x0001; // TopFieldFirst[21]
  834. if (result->interlacedFrame) {
  835. result->picTypeFirst = (val & 0x38) >> 3; // pic_type of 1st field
  836. result->picType = val & 7; // pic_type of 2nd field
  837. }
  838. else {
  839. result->picTypeFirst = PIC_TYPE_MAX; // no meaning
  840. result->picType = val & 7;
  841. }
  842. result->pictureStructure = (val >> 19) & 0x0003; // MbAffFlag[17], FieldPicFlag[16]
  843. result->repeatFirstField = (val >> 22) & 0x0001;
  844. result->progressiveFrame = (val >> 23) & 0x0003;
  845. if( pCodecInst->codecMode == AVC_DEC)
  846. {
  847. result->decFrameInfo = (val >> 15) & 0x0001;
  848. result->picStrPresent = (val >> 27) & 0x0001;
  849. result->picTimingStruct = (val >> 28) & 0x000f;
  850. //update picture type when IDR frame
  851. if (val & 0x40) { // 6th bit
  852. if (result->interlacedFrame)
  853. result->picTypeFirst = PIC_TYPE_IDR;
  854. else
  855. result->picType = PIC_TYPE_IDR;
  856. }
  857. result->decFrameInfo = (val >> 16) & 0x0003;
  858. if (result->indexFrameDisplay >= 0) {
  859. if (result->indexFrameDisplay == result->indexFrameDecoded)
  860. result->avcNpfFieldInfo = result->decFrameInfo;
  861. else
  862. result->avcNpfFieldInfo = pDecInfo->decOutInfo[result->indexFrameDisplay].decFrameInfo;
  863. }
  864. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_HRD_INFO);
  865. result->avcHrdInfo.cpbMinus1 = val>>2;
  866. result->avcHrdInfo.vclHrdParamFlag = (val>>1)&1;
  867. result->avcHrdInfo.nalHrdParamFlag = val&1;
  868. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_VUI_INFO);
  869. result->avcVuiInfo.fixedFrameRateFlag = val &1;
  870. result->avcVuiInfo.timingInfoPresent = (val>>1) & 0x01;
  871. result->avcVuiInfo.chromaLocBotField = (val>>2) & 0x07;
  872. result->avcVuiInfo.chromaLocTopField = (val>>5) & 0x07;
  873. result->avcVuiInfo.chromaLocInfoPresent = (val>>8) & 0x01;
  874. result->avcVuiInfo.colorPrimaries = (val>>16) & 0xff;
  875. result->avcVuiInfo.colorDescPresent = (val>>24) & 0x01;
  876. result->avcVuiInfo.isExtSAR = (val>>25) & 0x01;
  877. result->avcVuiInfo.vidFullRange = (val>>26) & 0x01;
  878. result->avcVuiInfo.vidFormat = (val>>27) & 0x07;
  879. result->avcVuiInfo.vidSigTypePresent = (val>>30) & 0x01;
  880. result->avcVuiInfo.vuiParamPresent = (val>>31) & 0x01;
  881. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_VUI_PIC_STRUCT);
  882. result->avcVuiInfo.vuiPicStructPresent = (val & 0x1);
  883. result->avcVuiInfo.vuiPicStruct = (val>>1);
  884. }
  885. if( pCodecInst->codecMode == MP2_DEC)
  886. {
  887. result->fieldSequence = (val >> 25) & 0x0007;
  888. result->frameDct = (val >> 28) & 0x0001;
  889. result->progressiveSequence = (val >> 29) & 0x0001;
  890. }
  891. result->fRateNumerator = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_FRATE_NR); //Frame rate, Aspect ratio can be changed frame by frame.
  892. result->fRateDenominator = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_FRATE_DR);
  893. if (pCodecInst->codecMode == AVC_DEC && result->fRateDenominator > 0)
  894. result->fRateDenominator *= 2;
  895. if (pCodecInst->codecMode == MP4_DEC)
  896. {
  897. result->mp4ModuloTimeBase = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_MODULO_TIME_BASE);
  898. result->mp4TimeIncrement = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_VOP_TIME_INCREMENT);
  899. }
  900. if (pCodecInst->codecMode == RV_DEC) {
  901. result->rvTr = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_RV_TR);
  902. result->rvTrB = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_RV_TR_BFRAME);
  903. }
  904. if (pCodecInst->codecMode == VPX_DEC) {
  905. result->aspectRateInfo = 0;
  906. }
  907. else {
  908. result->aspectRateInfo = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_ASPECT);
  909. }
  910. // User Data
  911. if (pDecInfo->userDataEnable) {
  912. int userDataNum;
  913. int userDataSize;
  914. BYTE tempBuf[8] = {0,};
  915. VpuReadMem(pCodecInst->coreIdx, pDecInfo->userDataBufAddr + 0, tempBuf, 8, VPU_USER_DATA_ENDIAN);
  916. val = ((tempBuf[0]<<24) & 0xFF000000) |
  917. ((tempBuf[1]<<16) & 0x00FF0000) |
  918. ((tempBuf[2]<< 8) & 0x0000FF00) |
  919. ((tempBuf[3]<< 0) & 0x000000FF);
  920. userDataNum = (val >> 16) & 0xFFFF;
  921. userDataSize = (val >> 0) & 0xFFFF;
  922. if (userDataNum == 0)
  923. userDataSize = 0;
  924. result->decOutputExtData.userDataNum = userDataNum;
  925. result->decOutputExtData.userDataSize = userDataSize;
  926. val = ((tempBuf[4]<<24) & 0xFF000000) |
  927. ((tempBuf[5]<<16) & 0x00FF0000) |
  928. ((tempBuf[6]<< 8) & 0x0000FF00) |
  929. ((tempBuf[7]<< 0) & 0x000000FF);
  930. if (userDataNum == 0)
  931. result->decOutputExtData.userDataBufFull = 0;
  932. else
  933. result->decOutputExtData.userDataBufFull = (val >> 16) & 0xFFFF;
  934. result->decOutputExtData.activeFormat = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_ATSC_USER_DATA_INFO)&0xf;
  935. }
  936. result->numOfErrMBs = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_ERR_MB);
  937. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_SUCCESS);
  938. result->sequenceChanged = ((val>>20) & 0x1);
  939. result->streamEndFlag = ((pDecInfo->streamEndflag>>2) & 0x01);
  940. if (pCodecInst->codecMode == VC1_DEC && result->indexFrameDisplay != -3) {
  941. if (pDecInfo->vc1BframeDisplayValid == 0) {
  942. if (result->picType == 2) {
  943. result->indexFrameDisplay = -3;
  944. } else {
  945. pDecInfo->vc1BframeDisplayValid = 1;
  946. }
  947. }
  948. }
  949. if (pCodecInst->codecMode == AVC_DEC && pCodecInst->codecModeAux == AVC_AUX_MVC)
  950. {
  951. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_MVC_REPORT);
  952. result->mvcPicInfo.viewIdxDisplay = (val>>0) & 1;
  953. result->mvcPicInfo.viewIdxDecoded = (val>>1) & 1;
  954. }
  955. if (pCodecInst->codecMode == AVC_DEC)
  956. {
  957. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_AVC_FPA_SEI0);
  958. if ((int)val < 0) {
  959. result->avcFpaSei.exist = 0;
  960. }
  961. else {
  962. result->avcFpaSei.exist = 1;
  963. result->avcFpaSei.framePackingArrangementId = val;
  964. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_AVC_FPA_SEI1);
  965. result->avcFpaSei.contentInterpretationType = val&0x3F; // [5:0]
  966. result->avcFpaSei.framePackingArrangementType = (val >> 6)&0x7F; // [12:6]
  967. result->avcFpaSei.framePackingArrangementExtensionFlag = (val >> 13)&0x01; // [13]
  968. result->avcFpaSei.frame1SelfContainedFlag = (val >> 14)&0x01; // [14]
  969. result->avcFpaSei.frame0SelfContainedFlag = (val >> 15)&0x01; // [15]
  970. result->avcFpaSei.currentFrameIsFrame0Flag = (val >> 16)&0x01; // [16]
  971. result->avcFpaSei.fieldViewsFlag = (val >> 17)&0x01; // [17]
  972. result->avcFpaSei.frame0FlippedFlag = (val >> 18)&0x01; // [18]
  973. result->avcFpaSei.spatialFlippingFlag = (val >> 19)&0x01; // [19]
  974. result->avcFpaSei.quincunxSamplingFlag = (val >> 20)&0x01; // [20]
  975. result->avcFpaSei.framePackingArrangementCancelFlag = (val >> 21)&0x01; // [21]
  976. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_AVC_FPA_SEI2);
  977. result->avcFpaSei.framePackingArrangementRepetitionPeriod = val&0x7FFF; // [14:0]
  978. result->avcFpaSei.frame1GridPositionY = (val >> 16)&0x0F; // [19:16]
  979. result->avcFpaSei.frame1GridPositionX = (val >> 20)&0x0F; // [23:20]
  980. result->avcFpaSei.frame0GridPositionY = (val >> 24)&0x0F; // [27:24]
  981. result->avcFpaSei.frame0GridPositionX = (val >> 28)&0x0F; // [31:28]
  982. }
  983. result->avcPocTop = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_POC_TOP);
  984. result->avcPocBot = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_POC_BOT);
  985. if (result->interlacedFrame)
  986. {
  987. if (result->avcPocTop > result->avcPocBot) {
  988. result->avcPocPic = result->avcPocBot;
  989. } else {
  990. result->avcPocPic = result->avcPocTop;
  991. }
  992. }
  993. else
  994. result->avcPocPic = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_POC);
  995. result->avcTemporalId = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_TID_INFO);
  996. }
  997. if (pCodecInst->codecMode == AVC_DEC)
  998. {
  999. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_AVC_SEI_RP_INFO);
  1000. if ((int)val < 0) {
  1001. result->avcRpSei.exist = 0;
  1002. }
  1003. else {
  1004. result->avcRpSei.exist = 1;
  1005. result->avcRpSei.changingSliceGroupIdc = val & 0x3; // [1:0]
  1006. result->avcRpSei.brokenLinkFlag = (val >> 2)&0x01; // [2]
  1007. result->avcRpSei.exactMatchFlag = (val >> 3)&0x01; // [3]
  1008. result->avcRpSei.recoveryFrameCnt = (val >> 4)&0x3F; // [9:4]
  1009. }
  1010. }
  1011. result->bytePosFrameStart = VpuReadReg(pCodecInst->coreIdx, BIT_BYTE_POS_FRAME_START);
  1012. result->bytePosFrameEnd = VpuReadReg(pCodecInst->coreIdx, BIT_BYTE_POS_FRAME_END);
  1013. if (result->indexFrameDecoded >= 0 && result->indexFrameDecoded < MAX_GDI_IDX)
  1014. pDecInfo->decOutInfo[result->indexFrameDecoded] = *result;
  1015. result->frameDisplayFlag = pDecInfo->frameDisplayFlag;
  1016. result->frameCycle = VpuReadReg(pCodecInst->coreIdx, BIT_FRAME_CYCLE);
  1017. return RETCODE_SUCCESS;
  1018. }
  1019. RetCode Coda9VpuDecSetBitstreamFlag(CodecInst* instance, BOOL running, BOOL eos)
  1020. {
  1021. Uint32 val;
  1022. DecInfo* pDecInfo;
  1023. pDecInfo = &instance->CodecInfo->decInfo;
  1024. if (eos&0x01) {
  1025. val = VpuReadReg(instance->coreIdx, BIT_BIT_STREAM_PARAM);
  1026. val |= 1 << 2;
  1027. pDecInfo->streamEndflag = val;
  1028. if (running == TRUE)
  1029. VpuWriteReg(instance->coreIdx, BIT_BIT_STREAM_PARAM, val);
  1030. return RETCODE_SUCCESS;
  1031. }
  1032. else {
  1033. val = VpuReadReg(instance->coreIdx, BIT_BIT_STREAM_PARAM);
  1034. val &= ~(1 << 2);
  1035. pDecInfo->streamEndflag = val;
  1036. if (running == TRUE)
  1037. VpuWriteReg(instance->coreIdx, BIT_BIT_STREAM_PARAM, val);
  1038. return RETCODE_SUCCESS;
  1039. }
  1040. }
  1041. RetCode Coda9VpuDecCpbFlush(CodecInst* instance)
  1042. {
  1043. Uint32 val;
  1044. DecInfo* pDecInfo;
  1045. pDecInfo = &instance->CodecInfo->decInfo;
  1046. if (pDecInfo->openParam.bitstreamMode != BS_MODE_INTERRUPT) {
  1047. return RETCODE_INVALID_COMMAND;
  1048. }
  1049. val = VpuReadReg(instance->coreIdx, BIT_BIT_STREAM_PARAM);
  1050. val &= ~(3<<3);
  1051. val |= (2<<3); // set to pic_end mode
  1052. VpuWriteReg(instance->coreIdx, BIT_BIT_STREAM_PARAM, val);
  1053. return RETCODE_SUCCESS;
  1054. }
  1055. RetCode Coda9VpuDecGetSeqInfo(CodecInst* instance, DecInitialInfo* info)
  1056. {
  1057. CodecInst* pCodecInst = NULL;
  1058. DecInfo* pDecInfo = NULL;
  1059. Uint32 val, val2;
  1060. pCodecInst = instance;
  1061. pDecInfo = &pCodecInst->CodecInfo->decInfo;
  1062. if (pCodecInst->loggingEnable) {
  1063. vdi_log(pCodecInst->coreIdx, DEC_SEQ_INIT, 0);
  1064. }
  1065. info->warnInfo = 0;
  1066. if (pDecInfo->openParam.bitstreamMode == BS_MODE_INTERRUPT && pDecInfo->seqInitEscape) {
  1067. pDecInfo->streamEndflag &= ~(3<<3);
  1068. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_PARAM, pDecInfo->streamEndflag);
  1069. pDecInfo->seqInitEscape = 0;
  1070. }
  1071. pDecInfo->streamRdPtr = VpuReadReg(instance->coreIdx, pDecInfo->streamRdPtrRegAddr);
  1072. pDecInfo->frameDisplayFlag = VpuReadReg(pCodecInst->coreIdx, pDecInfo->frameDisplayFlagRegAddr);
  1073. pDecInfo->streamEndflag = VpuReadReg(pCodecInst->coreIdx, BIT_BIT_STREAM_PARAM);
  1074. info->seqInitErrReason = 0;
  1075. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_SUCCESS);
  1076. if (val & (1UL<<31)) {
  1077. return RETCODE_MEMORY_ACCESS_VIOLATION;
  1078. }
  1079. if ( pDecInfo->openParam.bitstreamMode == BS_MODE_PIC_END) {
  1080. if (val & (1<<4)) {
  1081. info->seqInitErrReason = (VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_SEQ_ERR_REASON));
  1082. return RETCODE_FAILURE;
  1083. }
  1084. }
  1085. if (val == 0) {
  1086. info->seqInitErrReason = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_SEQ_ERR_REASON);
  1087. return RETCODE_FAILURE;
  1088. }
  1089. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_SRC_SIZE);
  1090. info->picWidth = ( (val >> 16) & 0xffff );
  1091. info->picHeight = ( val & 0xffff );
  1092. info->lumaBitdepth = 8;
  1093. info->chromaBitdepth = 8;
  1094. info->fRateNumerator = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_FRATE_NR);
  1095. info->fRateDenominator = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_FRATE_DR);
  1096. if (pCodecInst->codecMode == AVC_DEC && info->fRateDenominator > 0) {
  1097. info->fRateDenominator *= 2;
  1098. }
  1099. if (pCodecInst->codecMode == MP4_DEC) {
  1100. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_INFO);
  1101. info->mp4ShortVideoHeader = (val >> 2) & 1;
  1102. info->mp4DataPartitionEnable = val & 1;
  1103. info->mp4ReversibleVlcEnable = info->mp4DataPartitionEnable ? ((val >> 1) & 1) : 0;
  1104. info->h263AnnexJEnable = (val >> 3) & 1;
  1105. }
  1106. else if (pCodecInst->codecMode == VPX_DEC && pCodecInst->codecModeAux == VPX_AUX_VP8) {
  1107. // h_scale[31:30] v_scale[29:28] pic_width[27:14] pic_height[13:0]
  1108. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_VP8_SCALE_INFO);
  1109. info->vp8ScaleInfo.hScaleFactor = (val >> 30) & 0x03;
  1110. info->vp8ScaleInfo.vScaleFactor = (val >> 28) & 0x03;
  1111. info->vp8ScaleInfo.picWidth = (val >> 14) & 0x3FFF;
  1112. info->vp8ScaleInfo.picHeight = (val >> 0) & 0x3FFF;
  1113. }
  1114. info->minFrameBufferCount = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_FRAME_NEED);
  1115. info->frameBufDelay = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_FRAME_DELAY);
  1116. if (pCodecInst->codecMode == AVC_DEC || pCodecInst->codecMode == MP2_DEC || pCodecInst->codecMode == AVS_DEC) {
  1117. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_CROP_LEFT_RIGHT);
  1118. val2 = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_CROP_TOP_BOTTOM);
  1119. info->picCropRect.left = ((val>>16) & 0xFFFF);
  1120. info->picCropRect.right = info->picWidth - (val & 0xFFFF);;
  1121. info->picCropRect.top = ((val2>>16) & 0xFFFF);
  1122. info->picCropRect.bottom = info->picHeight - (val2 & 0xFFFF);
  1123. val = (info->picWidth * info->picHeight * 3 / 2) / 1024;
  1124. info->normalSliceSize = val / 4;
  1125. info->worstSliceSize = val / 2;
  1126. }
  1127. else {
  1128. info->picCropRect.left = 0;
  1129. info->picCropRect.right = info->picWidth;
  1130. info->picCropRect.top = 0;
  1131. info->picCropRect.bottom = info->picHeight;
  1132. }
  1133. if (pCodecInst->codecMode == MP2_DEC) {
  1134. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_MP2_BAR_LEFT_RIGHT);
  1135. val2 = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_MP2_BAR_TOP_BOTTOM);
  1136. info->mp2BardataInfo.barLeft = ((val>>16) & 0xFFFF);
  1137. info->mp2BardataInfo.barRight = (val&0xFFFF);
  1138. info->mp2BardataInfo.barTop = ((val2>>16) & 0xFFFF);
  1139. info->mp2BardataInfo.barBottom = (val2&0xFFFF);
  1140. }
  1141. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_HEADER_REPORT);
  1142. info->profile = (val >> 0) & 0xFF;
  1143. info->level = (val >> 8) & 0xFF;
  1144. info->interlace = (val >> 16) & 0x01;
  1145. info->direct8x8Flag = (val >> 17) & 0x01;
  1146. info->vc1Psf = (val >> 18) & 0x01;
  1147. info->constraint_set_flag[0] = (val >> 19) & 0x01;
  1148. info->constraint_set_flag[1] = (val >> 20) & 0x01;
  1149. info->constraint_set_flag[2] = (val >> 21) & 0x01;
  1150. info->constraint_set_flag[3] = (val >> 22) & 0x01;
  1151. info->chromaFormatIDC = (val >> 23) & 0x03;
  1152. info->isExtSAR = (val >> 25) & 0x01;
  1153. info->maxNumRefFrm = (val >> 27) & 0x0f;
  1154. info->maxNumRefFrmFlag = (val >> 31) & 0x01;
  1155. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_ASPECT);
  1156. info->aspectRateInfo = val;
  1157. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_BIT_RATE);
  1158. info->bitRate = val;
  1159. if (pCodecInst->codecMode == AVC_DEC) {
  1160. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_VUI_INFO);
  1161. info->avcVuiInfo.fixedFrameRateFlag = val &1;
  1162. info->avcVuiInfo.timingInfoPresent = (val>>1) & 0x01;
  1163. info->avcVuiInfo.chromaLocBotField = (val>>2) & 0x07;
  1164. info->avcVuiInfo.chromaLocTopField = (val>>5) & 0x07;
  1165. info->avcVuiInfo.chromaLocInfoPresent = (val>>8) & 0x01;
  1166. info->avcVuiInfo.colorPrimaries = (val>>16) & 0xff;
  1167. info->avcVuiInfo.colorDescPresent = (val>>24) & 0x01;
  1168. info->avcVuiInfo.isExtSAR = (val>>25) & 0x01;
  1169. info->avcVuiInfo.vidFullRange = (val>>26) & 0x01;
  1170. info->avcVuiInfo.vidFormat = (val>>27) & 0x07;
  1171. info->avcVuiInfo.vidSigTypePresent = (val>>30) & 0x01;
  1172. info->avcVuiInfo.vuiParamPresent = (val>>31) & 0x01;
  1173. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_VUI_PIC_STRUCT);
  1174. info->avcVuiInfo.vuiPicStructPresent = (val & 0x1);
  1175. info->avcVuiInfo.vuiPicStruct = (val>>1);
  1176. }
  1177. if (pCodecInst->codecMode == MP2_DEC) {
  1178. // seq_ext info
  1179. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_EXT_INFO);
  1180. info->mp2LowDelay = val & 1;
  1181. info->mp2DispVerSize = (val>>1) & 0x3fff;
  1182. info->mp2DispHorSize = (val>>15) & 0x3fff;
  1183. if (pDecInfo->userDataEnable) {
  1184. Uint32 userDataNum = 0;
  1185. Uint32 userDataSize = 0;
  1186. BYTE tempBuf[8] = {0,};
  1187. // user data
  1188. VpuReadMem(pCodecInst->coreIdx, pDecInfo->userDataBufAddr, tempBuf, 8, VPU_USER_DATA_ENDIAN);
  1189. val = ((tempBuf[0]<<24) & 0xFF000000) |
  1190. ((tempBuf[1]<<16) & 0x00FF0000) |
  1191. ((tempBuf[2]<< 8) & 0x0000FF00) |
  1192. ((tempBuf[3]<< 0) & 0x000000FF);
  1193. userDataNum = (val >> 16) & 0xFFFF;
  1194. userDataSize = (val >> 0) & 0xFFFF;
  1195. if (userDataNum == 0) {
  1196. userDataSize = 0;
  1197. }
  1198. info->userDataNum = userDataNum;
  1199. info->userDataSize = userDataSize;
  1200. val = ((tempBuf[4]<<24) & 0xFF000000) |
  1201. ((tempBuf[5]<<16) & 0x00FF0000) |
  1202. ((tempBuf[6]<< 8) & 0x0000FF00) |
  1203. ((tempBuf[7]<< 0) & 0x000000FF);
  1204. if (userDataNum == 0) {
  1205. info->userDataBufFull = 0;
  1206. }
  1207. else {
  1208. info->userDataBufFull = (val >> 16) & 0xFFFF;
  1209. }
  1210. }
  1211. }
  1212. return RETCODE_SUCCESS;
  1213. }
  1214. RetCode Coda9VpuDecRegisterFramebuffer(CodecInst* instance)
  1215. {
  1216. CodecInst* pCodecInst;
  1217. DecInfo* pDecInfo;
  1218. PhysicalAddress paraBuffer;
  1219. vpu_buffer_t vb;
  1220. Uint32 val;
  1221. int i;
  1222. BYTE frameAddr[MAX_GDI_IDX][3][4];
  1223. BYTE colMvAddr[MAX_GDI_IDX][4];
  1224. pCodecInst = instance;
  1225. pDecInfo = &pCodecInst->CodecInfo->decInfo;
  1226. vdi_get_common_memory(pCodecInst->coreIdx, &vb);
  1227. paraBuffer = vb.phys_addr + CODE_BUF_SIZE + TEMP_BUF_SIZE;
  1228. pDecInfo->mapCfg.productId = pCodecInst->productId;
  1229. if (pDecInfo->mapType != LINEAR_FRAME_MAP && pDecInfo->mapType != LINEAR_FIELD_MAP) {
  1230. val = SetTiledMapType(pCodecInst->coreIdx, &pDecInfo->mapCfg, pDecInfo->mapType, (pDecInfo->stride > pDecInfo->frameBufferHeight)?pDecInfo->stride:pDecInfo->frameBufferHeight,
  1231. pDecInfo->openParam.cbcrInterleave, &pDecInfo->dramCfg);
  1232. }
  1233. else {
  1234. val = SetTiledMapType(pCodecInst->coreIdx, &pDecInfo->mapCfg, pDecInfo->mapType,pDecInfo->stride, pDecInfo->openParam.cbcrInterleave, &pDecInfo->dramCfg);
  1235. }
  1236. if (val == 0) {
  1237. return RETCODE_INVALID_PARAM;
  1238. }
  1239. //Allocate frame buffer
  1240. for (i=0; i<pDecInfo->numFbsForDecoding; i++) {
  1241. frameAddr[i][0][0] = (pDecInfo->frameBufPool[i].bufY >> 24) & 0xFF;
  1242. frameAddr[i][0][1] = (pDecInfo->frameBufPool[i].bufY >> 16) & 0xFF;
  1243. frameAddr[i][0][2] = (pDecInfo->frameBufPool[i].bufY >> 8) & 0xFF;
  1244. frameAddr[i][0][3] = (pDecInfo->frameBufPool[i].bufY >> 0) & 0xFF;
  1245. if (pDecInfo->openParam.cbcrOrder == CBCR_ORDER_NORMAL) {
  1246. frameAddr[i][1][0] = (pDecInfo->frameBufPool[i].bufCb >> 24) & 0xFF;
  1247. frameAddr[i][1][1] = (pDecInfo->frameBufPool[i].bufCb >> 16) & 0xFF;
  1248. frameAddr[i][1][2] = (pDecInfo->frameBufPool[i].bufCb >> 8) & 0xFF;
  1249. frameAddr[i][1][3] = (pDecInfo->frameBufPool[i].bufCb >> 0) & 0xFF;
  1250. frameAddr[i][2][0] = (pDecInfo->frameBufPool[i].bufCr >> 24) & 0xFF;
  1251. frameAddr[i][2][1] = (pDecInfo->frameBufPool[i].bufCr >> 16) & 0xFF;
  1252. frameAddr[i][2][2] = (pDecInfo->frameBufPool[i].bufCr >> 8) & 0xFF;
  1253. frameAddr[i][2][3] = (pDecInfo->frameBufPool[i].bufCr >> 0) & 0xFF;
  1254. }
  1255. else {
  1256. frameAddr[i][2][0] = (pDecInfo->frameBufPool[i].bufCb >> 24) & 0xFF;
  1257. frameAddr[i][2][1] = (pDecInfo->frameBufPool[i].bufCb >> 16) & 0xFF;
  1258. frameAddr[i][2][2] = (pDecInfo->frameBufPool[i].bufCb >> 8) & 0xFF;
  1259. frameAddr[i][2][3] = (pDecInfo->frameBufPool[i].bufCb >> 0) & 0xFF;
  1260. frameAddr[i][1][0] = (pDecInfo->frameBufPool[i].bufCr >> 24) & 0xFF;
  1261. frameAddr[i][1][1] = (pDecInfo->frameBufPool[i].bufCr >> 16) & 0xFF;
  1262. frameAddr[i][1][2] = (pDecInfo->frameBufPool[i].bufCr >> 8) & 0xFF;
  1263. frameAddr[i][1][3] = (pDecInfo->frameBufPool[i].bufCr >> 0) & 0xFF;
  1264. }
  1265. }
  1266. VpuWriteMem(pCodecInst->coreIdx, paraBuffer, (BYTE*)frameAddr, sizeof(frameAddr), VDI_BIG_ENDIAN);
  1267. // MV allocation and register
  1268. if (pCodecInst->codecMode == AVC_DEC || pCodecInst->codecMode == VC1_DEC || pCodecInst->codecMode == MP4_DEC ||
  1269. pCodecInst->codecMode == RV_DEC || pCodecInst->codecMode == AVS_DEC)
  1270. {
  1271. int size_mvcolbuf;
  1272. vpu_buffer_t vbBuffer;
  1273. size_mvcolbuf = ((pDecInfo->initialInfo.picWidth+31)&~31)*((pDecInfo->initialInfo.picHeight+31)&~31);
  1274. size_mvcolbuf = (size_mvcolbuf*3)/2;
  1275. size_mvcolbuf = (size_mvcolbuf+4)/5;
  1276. size_mvcolbuf = ((size_mvcolbuf+7)/8)*8;
  1277. vbBuffer.size = size_mvcolbuf;
  1278. vbBuffer.phys_addr = 0;
  1279. for (i=0 ; i<pDecInfo->numFbsForDecoding ; i++) {
  1280. if (vdi_allocate_dma_memory(pCodecInst->coreIdx, &vbBuffer)<0){
  1281. return RETCODE_FAILURE;
  1282. }
  1283. pDecInfo->vbMV[i] = vbBuffer;
  1284. }
  1285. if (pCodecInst->codecMode == AVC_DEC) {
  1286. for (i=0; i<pDecInfo->numFbsForDecoding; i++) {
  1287. colMvAddr[i][0] = (pDecInfo->vbMV[i].phys_addr >> 24) & 0xFF;
  1288. colMvAddr[i][1] = (pDecInfo->vbMV[i].phys_addr >> 16) & 0xFF;
  1289. colMvAddr[i][2] = (pDecInfo->vbMV[i].phys_addr >> 8) & 0xFF;
  1290. colMvAddr[i][3] = (pDecInfo->vbMV[i].phys_addr >> 0) & 0xFF;
  1291. }
  1292. }
  1293. else {
  1294. colMvAddr[0][0] = (pDecInfo->vbMV[0].phys_addr >> 24) & 0xFF;
  1295. colMvAddr[0][1] = (pDecInfo->vbMV[0].phys_addr >> 16) & 0xFF;
  1296. colMvAddr[0][2] = (pDecInfo->vbMV[0].phys_addr >> 8) & 0xFF;
  1297. colMvAddr[0][3] = (pDecInfo->vbMV[0].phys_addr >> 0) & 0xFF;
  1298. }
  1299. VpuWriteMem(pCodecInst->coreIdx, paraBuffer+384, (BYTE*)colMvAddr, sizeof(colMvAddr), VDI_BIG_ENDIAN);
  1300. }
  1301. if (pCodecInst->productId == PRODUCT_ID_980) {
  1302. for (i=0; i<pDecInfo->numFbsForDecoding; i++) {
  1303. frameAddr[i][0][0] = (pDecInfo->frameBufPool[i].bufYBot >> 24) & 0xFF;
  1304. frameAddr[i][0][1] = (pDecInfo->frameBufPool[i].bufYBot >> 16) & 0xFF;
  1305. frameAddr[i][0][2] = (pDecInfo->frameBufPool[i].bufYBot >> 8) & 0xFF;
  1306. frameAddr[i][0][3] = (pDecInfo->frameBufPool[i].bufYBot >> 0) & 0xFF;
  1307. if (pDecInfo->openParam.cbcrOrder == CBCR_ORDER_NORMAL) {
  1308. frameAddr[i][1][0] = (pDecInfo->frameBufPool[i].bufCbBot >> 24) & 0xFF;
  1309. frameAddr[i][1][1] = (pDecInfo->frameBufPool[i].bufCbBot >> 16) & 0xFF;
  1310. frameAddr[i][1][2] = (pDecInfo->frameBufPool[i].bufCbBot >> 8) & 0xFF;
  1311. frameAddr[i][1][3] = (pDecInfo->frameBufPool[i].bufCbBot >> 0) & 0xFF;
  1312. frameAddr[i][2][0] = (pDecInfo->frameBufPool[i].bufCrBot >> 24) & 0xFF;
  1313. frameAddr[i][2][1] = (pDecInfo->frameBufPool[i].bufCrBot >> 16) & 0xFF;
  1314. frameAddr[i][2][2] = (pDecInfo->frameBufPool[i].bufCrBot >> 8) & 0xFF;
  1315. frameAddr[i][2][3] = (pDecInfo->frameBufPool[i].bufCrBot >> 0) & 0xFF;
  1316. }
  1317. else {
  1318. frameAddr[i][2][0] = (pDecInfo->frameBufPool[i].bufCbBot >> 24) & 0xFF;
  1319. frameAddr[i][2][1] = (pDecInfo->frameBufPool[i].bufCbBot >> 16) & 0xFF;
  1320. frameAddr[i][2][2] = (pDecInfo->frameBufPool[i].bufCbBot >> 8) & 0xFF;
  1321. frameAddr[i][2][3] = (pDecInfo->frameBufPool[i].bufCbBot >> 0) & 0xFF;
  1322. frameAddr[i][1][0] = (pDecInfo->frameBufPool[i].bufCrBot >> 24) & 0xFF;
  1323. frameAddr[i][1][1] = (pDecInfo->frameBufPool[i].bufCrBot >> 16) & 0xFF;
  1324. frameAddr[i][1][2] = (pDecInfo->frameBufPool[i].bufCrBot >> 8) & 0xFF;
  1325. frameAddr[i][1][3] = (pDecInfo->frameBufPool[i].bufCrBot >> 0) & 0xFF;
  1326. }
  1327. }
  1328. VpuWriteMem(pCodecInst->coreIdx, paraBuffer+384+128, (BYTE*)frameAddr, sizeof(frameAddr), VDI_BIG_ENDIAN);
  1329. if (pDecInfo->wtlEnable) {
  1330. int num = pDecInfo->numFbsForDecoding; /* start index of WTL fb array */
  1331. int end = pDecInfo->numFrameBuffers;
  1332. for (i=num; i<end; i++) {
  1333. frameAddr[i-num][0][0] = (pDecInfo->frameBufPool[i].bufY >> 24) & 0xFF;
  1334. frameAddr[i-num][0][1] = (pDecInfo->frameBufPool[i].bufY >> 16) & 0xFF;
  1335. frameAddr[i-num][0][2] = (pDecInfo->frameBufPool[i].bufY >> 8) & 0xFF;
  1336. frameAddr[i-num][0][3] = (pDecInfo->frameBufPool[i].bufY >> 0) & 0xFF;
  1337. if (pDecInfo->openParam.cbcrOrder == CBCR_ORDER_NORMAL) {
  1338. frameAddr[i-num][1][0] = (pDecInfo->frameBufPool[i].bufCb >> 24) & 0xFF;
  1339. frameAddr[i-num][1][1] = (pDecInfo->frameBufPool[i].bufCb >> 16) & 0xFF;
  1340. frameAddr[i-num][1][2] = (pDecInfo->frameBufPool[i].bufCb >> 8) & 0xFF;
  1341. frameAddr[i-num][1][3] = (pDecInfo->frameBufPool[i].bufCb >> 0) & 0xFF;
  1342. frameAddr[i-num][2][0] = (pDecInfo->frameBufPool[i].bufCr >> 24) & 0xFF;
  1343. frameAddr[i-num][2][1] = (pDecInfo->frameBufPool[i].bufCr >> 16) & 0xFF;
  1344. frameAddr[i-num][2][2] = (pDecInfo->frameBufPool[i].bufCr >> 8) & 0xFF;
  1345. frameAddr[i-num][2][3] = (pDecInfo->frameBufPool[i].bufCr >> 0) & 0xFF;
  1346. }
  1347. else {
  1348. frameAddr[i-num][2][0] = (pDecInfo->frameBufPool[i].bufCb >> 24) & 0xFF;
  1349. frameAddr[i-num][2][1] = (pDecInfo->frameBufPool[i].bufCb >> 16) & 0xFF;
  1350. frameAddr[i-num][2][2] = (pDecInfo->frameBufPool[i].bufCb >> 8) & 0xFF;
  1351. frameAddr[i-num][2][3] = (pDecInfo->frameBufPool[i].bufCb >> 0) & 0xFF;
  1352. frameAddr[i-num][1][0] = (pDecInfo->frameBufPool[i].bufCr >> 24) & 0xFF;
  1353. frameAddr[i-num][1][1] = (pDecInfo->frameBufPool[i].bufCr >> 16) & 0xFF;
  1354. frameAddr[i-num][1][2] = (pDecInfo->frameBufPool[i].bufCr >> 8) & 0xFF;
  1355. frameAddr[i-num][1][3] = (pDecInfo->frameBufPool[i].bufCr >> 0) & 0xFF;
  1356. }
  1357. }
  1358. VpuWriteMem(pCodecInst->coreIdx, paraBuffer+384+128+384, (BYTE*)frameAddr, sizeof(frameAddr), VDI_BIG_ENDIAN);
  1359. if (pDecInfo->wtlMode == FF_FIELD ) {
  1360. for (i=num; i<num*2; i++) {
  1361. frameAddr[i-num][0][0] = (pDecInfo->frameBufPool[i].bufYBot >> 24) & 0xFF;
  1362. frameAddr[i-num][0][1] = (pDecInfo->frameBufPool[i].bufYBot >> 16) & 0xFF;
  1363. frameAddr[i-num][0][2] = (pDecInfo->frameBufPool[i].bufYBot >> 8) & 0xFF;
  1364. frameAddr[i-num][0][3] = (pDecInfo->frameBufPool[i].bufYBot >> 0) & 0xFF;
  1365. if (pDecInfo->openParam.cbcrOrder == CBCR_ORDER_NORMAL) {
  1366. frameAddr[i-num][1][0] = (pDecInfo->frameBufPool[i].bufCbBot >> 24) & 0xFF;
  1367. frameAddr[i-num][1][1] = (pDecInfo->frameBufPool[i].bufCbBot >> 16) & 0xFF;
  1368. frameAddr[i-num][1][2] = (pDecInfo->frameBufPool[i].bufCbBot >> 8) & 0xFF;
  1369. frameAddr[i-num][1][3] = (pDecInfo->frameBufPool[i].bufCbBot >> 0) & 0xFF;
  1370. frameAddr[i-num][2][0] = (pDecInfo->frameBufPool[i].bufCrBot >> 24) & 0xFF;
  1371. frameAddr[i-num][2][1] = (pDecInfo->frameBufPool[i].bufCrBot >> 16) & 0xFF;
  1372. frameAddr[i-num][2][2] = (pDecInfo->frameBufPool[i].bufCrBot >> 8) & 0xFF;
  1373. frameAddr[i-num][2][3] = (pDecInfo->frameBufPool[i].bufCrBot >> 0) & 0xFF;
  1374. }
  1375. else {
  1376. frameAddr[i-num][2][0] = (pDecInfo->frameBufPool[i].bufCbBot >> 24) & 0xFF;
  1377. frameAddr[i-num][2][1] = (pDecInfo->frameBufPool[i].bufCbBot >> 16) & 0xFF;
  1378. frameAddr[i-num][2][2] = (pDecInfo->frameBufPool[i].bufCbBot >> 8) & 0xFF;
  1379. frameAddr[i-num][2][3] = (pDecInfo->frameBufPool[i].bufCbBot >> 0) & 0xFF;
  1380. frameAddr[i-num][1][0] = (pDecInfo->frameBufPool[i].bufCrBot >> 24) & 0xFF;
  1381. frameAddr[i-num][1][1] = (pDecInfo->frameBufPool[i].bufCrBot >> 16) & 0xFF;
  1382. frameAddr[i-num][1][2] = (pDecInfo->frameBufPool[i].bufCrBot >> 8) & 0xFF;
  1383. frameAddr[i-num][1][3] = (pDecInfo->frameBufPool[i].bufCrBot >> 0) & 0xFF;
  1384. }
  1385. }
  1386. VpuWriteMem(pCodecInst->coreIdx, paraBuffer+384+128+384+384, (BYTE*)frameAddr, sizeof(frameAddr), VDI_BIG_ENDIAN);
  1387. }
  1388. }
  1389. }
  1390. else {
  1391. if (pDecInfo->wtlEnable) {
  1392. int num = pDecInfo->numFbsForDecoding; /* start index of WTL fb array */
  1393. int end = pDecInfo->numFrameBuffers;
  1394. for (i=num; i<end; i++) {
  1395. frameAddr[i-num][0][0] = (pDecInfo->frameBufPool[i].bufY >> 24) & 0xFF;
  1396. frameAddr[i-num][0][1] = (pDecInfo->frameBufPool[i].bufY >> 16) & 0xFF;
  1397. frameAddr[i-num][0][2] = (pDecInfo->frameBufPool[i].bufY >> 8) & 0xFF;
  1398. frameAddr[i-num][0][3] = (pDecInfo->frameBufPool[i].bufY >> 0) & 0xFF;
  1399. if (pDecInfo->openParam.cbcrOrder == CBCR_ORDER_NORMAL) {
  1400. frameAddr[i-num][1][0] = (pDecInfo->frameBufPool[i].bufCb >> 24) & 0xFF;
  1401. frameAddr[i-num][1][1] = (pDecInfo->frameBufPool[i].bufCb >> 16) & 0xFF;
  1402. frameAddr[i-num][1][2] = (pDecInfo->frameBufPool[i].bufCb >> 8) & 0xFF;
  1403. frameAddr[i-num][1][3] = (pDecInfo->frameBufPool[i].bufCb >> 0) & 0xFF;
  1404. frameAddr[i-num][2][0] = (pDecInfo->frameBufPool[i].bufCr >> 24) & 0xFF;
  1405. frameAddr[i-num][2][1] = (pDecInfo->frameBufPool[i].bufCr >> 16) & 0xFF;
  1406. frameAddr[i-num][2][2] = (pDecInfo->frameBufPool[i].bufCr >> 8) & 0xFF;
  1407. frameAddr[i-num][2][3] = (pDecInfo->frameBufPool[i].bufCr >> 0) & 0xFF;
  1408. }
  1409. else {
  1410. frameAddr[i-num][2][0] = (pDecInfo->frameBufPool[i].bufCb >> 24) & 0xFF;
  1411. frameAddr[i-num][2][1] = (pDecInfo->frameBufPool[i].bufCb >> 16) & 0xFF;
  1412. frameAddr[i-num][2][2] = (pDecInfo->frameBufPool[i].bufCb >> 8) & 0xFF;
  1413. frameAddr[i-num][2][3] = (pDecInfo->frameBufPool[i].bufCb >> 0) & 0xFF;
  1414. frameAddr[i-num][1][0] = (pDecInfo->frameBufPool[i].bufCr >> 24) & 0xFF;
  1415. frameAddr[i-num][1][1] = (pDecInfo->frameBufPool[i].bufCr >> 16) & 0xFF;
  1416. frameAddr[i-num][1][2] = (pDecInfo->frameBufPool[i].bufCr >> 8) & 0xFF;
  1417. frameAddr[i-num][1][3] = (pDecInfo->frameBufPool[i].bufCr >> 0) & 0xFF;
  1418. }
  1419. }
  1420. VpuWriteMem(pCodecInst->coreIdx, paraBuffer+384+128+384, (BYTE*)frameAddr, sizeof(frameAddr), VDI_BIG_ENDIAN);
  1421. }
  1422. }
  1423. if (!ConfigSecAXICoda9(pCodecInst->coreIdx, pCodecInst->codecMode, &pDecInfo->secAxiInfo, pDecInfo->stride,
  1424. pDecInfo->frameBufferHeight, pDecInfo->initialInfo.profile&0xff)) {
  1425. return RETCODE_INSUFFICIENT_RESOURCE;
  1426. }
  1427. for (i=0; i<pDecInfo->numFrameBuffers; i++) {
  1428. pDecInfo->frameBufPool[i].nv21 = pDecInfo->openParam.nv21 & pDecInfo->openParam.cbcrInterleave;
  1429. }
  1430. // Tell the decoder how much frame buffers were allocated.
  1431. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_BUF_NUM, pDecInfo->numFrameBuffers);
  1432. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_BUF_STRIDE, pDecInfo->stride);
  1433. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_BIT_ADDR, pDecInfo->secAxiInfo.u.coda9.bufBitUse);
  1434. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_IPACDC_ADDR, pDecInfo->secAxiInfo.u.coda9.bufIpAcDcUse);
  1435. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_DBKY_ADDR, pDecInfo->secAxiInfo.u.coda9.bufDbkYUse);
  1436. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_DBKC_ADDR, pDecInfo->secAxiInfo.u.coda9.bufDbkCUse);
  1437. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_OVL_ADDR, pDecInfo->secAxiInfo.u.coda9.bufOvlUse);
  1438. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_BTP_ADDR, pDecInfo->secAxiInfo.u.coda9.bufBtpUse);
  1439. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_DELAY, pDecInfo->frameDelay);
  1440. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_CACHE_CONFIG, pDecInfo->cacheConfig.type2.CacheMode);
  1441. if (pCodecInst->codecMode == VPX_DEC) {
  1442. vpu_buffer_t *pvbSlice = &pDecInfo->vbSlice;
  1443. if (pvbSlice->size == 0) {
  1444. pvbSlice->size = VP8_MB_SAVE_SIZE;
  1445. if (vdi_allocate_dma_memory(pCodecInst->coreIdx, pvbSlice) < 0) {
  1446. return RETCODE_INSUFFICIENT_RESOURCE;
  1447. }
  1448. }
  1449. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_MB_BUF_BASE, pvbSlice->phys_addr);
  1450. }
  1451. if (pCodecInst->codecMode == AVC_DEC) {
  1452. vpu_buffer_t *pvbSlice = &pDecInfo->vbSlice;
  1453. if (pvbSlice->size == 0) {
  1454. pvbSlice->size = SLICE_SAVE_SIZE;
  1455. if (vdi_allocate_dma_memory(pCodecInst->coreIdx, pvbSlice) < 0) {
  1456. return RETCODE_INSUFFICIENT_RESOURCE;
  1457. }
  1458. }
  1459. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_SLICE_BB_START, pvbSlice->phys_addr);
  1460. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_SLICE_BB_SIZE, (pvbSlice->size/1024));
  1461. }
  1462. if (pCodecInst->productId == PRODUCT_ID_980) {
  1463. val = 0;
  1464. val |= (pDecInfo->openParam.bwbEnable<<15);
  1465. val |= (pDecInfo->wtlMode<<17)|(pDecInfo->tiled2LinearMode<<13)|(pDecInfo->mapType<<9)|(FORMAT_420<<6);
  1466. val |= ((pDecInfo->openParam.cbcrInterleave)<<2); // Interleave bit position is modified
  1467. val |= pDecInfo->openParam.frameEndian;
  1468. VpuWriteReg(pCodecInst->coreIdx, BIT_FRAME_MEM_CTRL, val);
  1469. }
  1470. else if (pCodecInst->productId == PRODUCT_ID_960) {
  1471. val = 0;
  1472. val |= (pDecInfo->wtlEnable<<17);
  1473. val |= (pDecInfo->openParam.bwbEnable<<12);
  1474. if (pDecInfo->mapType) {
  1475. if (pDecInfo->mapType == TILED_FRAME_MB_RASTER_MAP || pDecInfo->mapType == TILED_FIELD_MB_RASTER_MAP)
  1476. val |= (pDecInfo->tiled2LinearEnable<<11)|(0x03<<9)|(FORMAT_420<<6);
  1477. else
  1478. val |= (pDecInfo->tiled2LinearEnable<<11)|(0x02<<9)|(FORMAT_420<<6);
  1479. }
  1480. val |= ((pDecInfo->openParam.cbcrInterleave)<<2); // Interleave bit position is modified
  1481. val |= pDecInfo->openParam.frameEndian;
  1482. VpuWriteReg(pCodecInst->coreIdx, BIT_FRAME_MEM_CTRL, val);
  1483. }
  1484. else {
  1485. return RETCODE_NOT_FOUND_VPU_DEVICE;
  1486. }
  1487. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_MAX_DEC_SIZE, 0); // Must set to zero at API 2.1.5 version
  1488. Coda9BitIssueCommand(pCodecInst->coreIdx, pCodecInst, SET_FRAME_BUF);
  1489. if (vdi_wait_vpu_busy(pCodecInst->coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1) {
  1490. if (pCodecInst->loggingEnable)
  1491. vdi_log(pCodecInst->coreIdx, SET_FRAME_BUF, 2);
  1492. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1493. }
  1494. if (pCodecInst->loggingEnable)
  1495. vdi_log(pCodecInst->coreIdx, SET_FRAME_BUF, 0);
  1496. if (VpuReadReg(pCodecInst->coreIdx, RET_SET_FRAME_SUCCESS) & (1UL<<31)) {
  1497. return RETCODE_MEMORY_ACCESS_VIOLATION;
  1498. }
  1499. return RETCODE_SUCCESS;
  1500. }
  1501. RetCode Coda9VpuDecFlush(CodecInst* instance, FramebufferIndex* framebufferIndexes, Uint32 size)
  1502. {
  1503. Uint32 i;
  1504. DecInfo* pDecInfo = &instance->CodecInfo->decInfo;
  1505. Coda9BitIssueCommand(instance->coreIdx, instance, DEC_BUF_FLUSH);
  1506. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1) {
  1507. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1508. }
  1509. pDecInfo->frameDisplayFlag = 0;
  1510. if (framebufferIndexes != NULL) {
  1511. for (i=0; i<size; i++) {
  1512. framebufferIndexes[i].linearIndex = -2;
  1513. framebufferIndexes[i].tiledIndex = -2;
  1514. }
  1515. }
  1516. return RETCODE_SUCCESS;
  1517. }
  1518. /************************************************************************/
  1519. /* Encoder */
  1520. /************************************************************************/
  1521. RetCode Coda9VpuBuildUpEncParam(CodecInst* pCodec, EncOpenParam* param)
  1522. {
  1523. RetCode ret = RETCODE_SUCCESS;
  1524. Uint32 coreIdx;
  1525. Int32 productId;
  1526. EncInfo* pEncInfo = &pCodec->CodecInfo->encInfo;
  1527. coreIdx = pCodec->coreIdx;
  1528. productId = Coda9VpuGetProductId(coreIdx);
  1529. if ((ret=SetupEncCodecInstance(productId, pCodec)) != RETCODE_SUCCESS)
  1530. return ret;
  1531. if (param->bitstreamFormat == STD_MPEG4 || param->bitstreamFormat == STD_H263)
  1532. pCodec->codecMode = MP4_ENC;
  1533. else if (param->bitstreamFormat == STD_AVC)
  1534. pCodec->codecMode = AVC_ENC;
  1535. pCodec->codecModeAux = 0;
  1536. if (param->bitstreamFormat == STD_AVC && param->EncStdParam.avcParam.svcExtension)
  1537. pCodec->codecModeAux = AVC_AUX_SVC;
  1538. if (productId == PRODUCT_ID_980) {
  1539. pEncInfo->ActivePPSIdx = 0;
  1540. pEncInfo->frameIdx = 0;
  1541. pEncInfo->fieldDone = 0;
  1542. }
  1543. pEncInfo->vbWork.size = WORK_BUF_SIZE;
  1544. if (vdi_allocate_dma_memory(pCodec->coreIdx, &pEncInfo->vbWork) < 0)
  1545. return RETCODE_INSUFFICIENT_RESOURCE;
  1546. pEncInfo->streamRdPtr = param->bitstreamBuffer;
  1547. pEncInfo->streamWrPtr = param->bitstreamBuffer;
  1548. pEncInfo->lineBufIntEn = param->lineBufIntEn;
  1549. pEncInfo->streamBufStartAddr = param->bitstreamBuffer;
  1550. pEncInfo->streamBufSize = param->bitstreamBufferSize;
  1551. pEncInfo->streamBufEndAddr = param->bitstreamBuffer + param->bitstreamBufferSize;
  1552. pEncInfo->stride = 0;
  1553. pEncInfo->vbFrame.size = 0;
  1554. pEncInfo->vbPPU.size = 0;
  1555. pEncInfo->frameAllocExt = 0;
  1556. pEncInfo->ppuAllocExt = 0;
  1557. pEncInfo->secAxiInfo.u.coda9.useBitEnable = 0;
  1558. pEncInfo->secAxiInfo.u.coda9.useIpEnable = 0;
  1559. pEncInfo->secAxiInfo.u.coda9.useDbkYEnable = 0;
  1560. pEncInfo->secAxiInfo.u.coda9.useDbkCEnable = 0;
  1561. pEncInfo->secAxiInfo.u.coda9.useOvlEnable = 0;
  1562. pEncInfo->rotationEnable = 0;
  1563. pEncInfo->mirrorEnable = 0;
  1564. pEncInfo->mirrorDirection = MIRDIR_NONE;
  1565. pEncInfo->rotationAngle = 0;
  1566. pEncInfo->initialInfoObtained = 0;
  1567. pEncInfo->ringBufferEnable = param->ringBufferEnable;
  1568. pEncInfo->linear2TiledEnable = param->linear2TiledEnable;
  1569. pEncInfo->linear2TiledMode = param->linear2TiledMode; // coda980 only
  1570. if (!pEncInfo->linear2TiledEnable)
  1571. pEncInfo->linear2TiledMode = 0;
  1572. /* Maverick Cache I */
  1573. osal_memset((void*)&pEncInfo->cacheConfig, 0x00, sizeof(MaverickCacheConfig));
  1574. if (productId == PRODUCT_ID_960) {
  1575. pEncInfo->dramCfg.bankBit = EM_BANK;
  1576. pEncInfo->dramCfg.casBit = EM_CAS;
  1577. pEncInfo->dramCfg.rasBit = EM_RAS;
  1578. pEncInfo->dramCfg.busBit = EM_WIDTH;
  1579. }
  1580. return ret;
  1581. }
  1582. RetCode Coda9VpuEncSetup(CodecInst* pCodecInst)
  1583. {
  1584. Int32 picWidth, picHeight;
  1585. Int32 data, val;
  1586. Int32 productId, rcEnable;
  1587. EncInfo* pEncInfo = &pCodecInst->CodecInfo->encInfo;
  1588. rcEnable = pEncInfo->openParam.rcEnable&0xf;
  1589. #ifdef SUPPORT_980_RC_LIB
  1590. //======================================================================================
  1591. // using RC library,
  1592. // 1. calculate non-roi QP considering target bitrate when rc mode == 4 && roi enabled.
  1593. // 2. calculate picQp (rc mode==4). if rc mode is 4(picture level RC) && roi disabled
  1594. //======================================================================================
  1595. {
  1596. int pic_width, pic_height;
  1597. int bps = pEncInfo->openParam.bitRate*1000;
  1598. int buf_size_ms = pEncInfo->openParam.rcInitDelay;// * bps;
  1599. int frame_rate = (pEncInfo->openParam.frameRateInfo & 0xffff) /((pEncInfo->openParam.frameRateInfo >> 16) + 1);
  1600. int gop_size = pEncInfo->openParam.gopSize ;
  1601. int is_first_pic = (pEncInfo->frameIdx == 0);
  1602. pEncInfo->prevWrPtr = pEncInfo->streamBufStartAddr; // to calculate real encoded bit when ringbuffer enabled.
  1603. if (pEncInfo->rotationAngle == 90 || pEncInfo->rotationAngle == 270) {
  1604. pic_width = pEncInfo->openParam.picHeight;
  1605. pic_height= pEncInfo->openParam.picWidth;
  1606. }
  1607. else {
  1608. pic_width = pEncInfo->openParam.picWidth;
  1609. pic_height= pEncInfo->openParam.picHeight;
  1610. }
  1611. if(pEncInfo->openParam.EncStdParam.avcParam.fieldFlag)
  1612. {
  1613. pic_height = pic_height >> 1;
  1614. frame_rate = frame_rate << 1;
  1615. if(gop_size != 1)
  1616. gop_size = pEncInfo->openParam.gopSize << 1;
  1617. }
  1618. if (pCodecInst->productId == PRODUCT_ID_980 && pEncInfo->openParam.bitstreamFormat == STD_AVC)
  1619. {
  1620. int gamma = pEncInfo->openParam.userGamma;
  1621. #ifdef CLIP_PIC_DELTA_QP
  1622. int max_delta_qp_minus = pEncInfo->openParam.userMinDeltaQp;
  1623. int max_delta_qp_plus = pEncInfo->openParam.userMaxDeltaQp;
  1624. #endif
  1625. if(gamma == -1)
  1626. gamma = 1;
  1627. #ifdef CLIP_PIC_DELTA_QP
  1628. if(max_delta_qp_minus == -1)
  1629. max_delta_qp_minus = 51;
  1630. if(max_delta_qp_plus == -1)
  1631. max_delta_qp_plus = 51;
  1632. #endif
  1633. frm_rc_seq_init(&pEncInfo->frm_rc, bps, buf_size_ms, frame_rate, pic_width, pic_height, gop_size, pEncInfo->openParam.rcEnable,
  1634. pEncInfo->openParam.set_dqp_pic_num,
  1635. pEncInfo->openParam.gopEntry,
  1636. pEncInfo->openParam.LongTermDeltaQp,
  1637. pEncInfo->openParam.RcInitialQp
  1638. , is_first_pic,
  1639. gamma,
  1640. pEncInfo->openParam.rcWeightFactor
  1641. #ifdef CLIP_PIC_DELTA_QP
  1642. , max_delta_qp_minus,
  1643. max_delta_qp_plus
  1644. #endif
  1645. );
  1646. #ifdef AUTO_FRM_SKIP_DROP
  1647. frm_rc_set_auto_skip_param(
  1648. &pEncInfo->frm_rc,
  1649. pEncInfo->openParam.enAutoFrmSkip,
  1650. pEncInfo->openParam.enAutoFrmDrop,
  1651. pEncInfo->openParam.vbvThreshold,
  1652. pEncInfo->openParam.qpThreshold,
  1653. pEncInfo->openParam.maxContinuosFrameSkipNum,
  1654. pEncInfo->openParam.maxContinuosFrameDropNum
  1655. );
  1656. #endif
  1657. }
  1658. }
  1659. #endif
  1660. if(pEncInfo->openParam.bitstreamFormat == STD_AVC && pCodecInst->codecModeAux == AVC_AUX_SVC)
  1661. productId = pCodecInst->productId;
  1662. picWidth = pEncInfo->openParam.picWidth;
  1663. picHeight = pEncInfo->openParam.picHeight;
  1664. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_BB_START, pEncInfo->streamBufStartAddr);
  1665. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_BB_SIZE, pEncInfo->streamBufSize / 1024); // size in KB
  1666. // Rotation Left 90 or 270 case : Swap XY resolution for VPU internal usage
  1667. if (pEncInfo->rotationAngle == 90 || pEncInfo->rotationAngle == 270)
  1668. data = (picHeight<< 16) | picWidth;
  1669. else
  1670. data = (picWidth << 16) | picHeight;
  1671. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_SRC_SIZE, data);
  1672. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_SRC_F_RATE, pEncInfo->openParam.frameRateInfo);
  1673. if (pEncInfo->openParam.bitstreamFormat == STD_MPEG4) {
  1674. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_COD_STD, 3);
  1675. data = pEncInfo->openParam.EncStdParam.mp4Param.mp4IntraDcVlcThr << 2 |
  1676. pEncInfo->openParam.EncStdParam.mp4Param.mp4ReversibleVlcEnable << 1 |
  1677. pEncInfo->openParam.EncStdParam.mp4Param.mp4DataPartitionEnable;
  1678. data |= ((pEncInfo->openParam.EncStdParam.mp4Param.mp4HecEnable >0)? 1:0)<<5;
  1679. data |= ((pEncInfo->openParam.EncStdParam.mp4Param.mp4Verid == 2)? 0:1) << 6;
  1680. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_MP4_PARA, data);
  1681. if (productId == PRODUCT_ID_980)
  1682. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_ME_OPTION, (VPU_ME_LINEBUFFER_MODE << 9) |
  1683. (pEncInfo->openParam.meBlkMode << 5) |
  1684. (pEncInfo->openParam.MEUseZeroPmv << 4) |
  1685. (pEncInfo->openParam.MESearchRangeY<<2) |
  1686. pEncInfo->openParam.MESearchRangeX);
  1687. else
  1688. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_ME_OPTION, (pEncInfo->openParam.meBlkMode << 3) |
  1689. (pEncInfo->openParam.MEUseZeroPmv << 2) |
  1690. pEncInfo->openParam.MESearchRange);
  1691. }
  1692. else if (pEncInfo->openParam.bitstreamFormat == STD_H263) {
  1693. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_COD_STD, 11);
  1694. data = pEncInfo->openParam.EncStdParam.h263Param.h263AnnexIEnable << 3 |
  1695. pEncInfo->openParam.EncStdParam.h263Param.h263AnnexJEnable << 2 |
  1696. pEncInfo->openParam.EncStdParam.h263Param.h263AnnexKEnable << 1|
  1697. pEncInfo->openParam.EncStdParam.h263Param.h263AnnexTEnable;
  1698. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_263_PARA, data);
  1699. if (productId == PRODUCT_ID_980)
  1700. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_ME_OPTION, (VPU_ME_LINEBUFFER_MODE << 9) |
  1701. (pEncInfo->openParam.meBlkMode << 5) |
  1702. (pEncInfo->openParam.MEUseZeroPmv << 4) |
  1703. (pEncInfo->openParam.MESearchRangeY<<2) |
  1704. pEncInfo->openParam.MESearchRangeX);
  1705. else
  1706. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_ME_OPTION, (pEncInfo->openParam.meBlkMode << 3) |
  1707. (pEncInfo->openParam.MEUseZeroPmv << 2) |
  1708. pEncInfo->openParam.MESearchRange);
  1709. }
  1710. else if (pEncInfo->openParam.bitstreamFormat == STD_AVC) {
  1711. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_COD_STD, 0x0);
  1712. data = (pEncInfo->openParam.EncStdParam.avcParam.deblkFilterOffsetBeta & 15) << 12 |
  1713. (pEncInfo->openParam.EncStdParam.avcParam.deblkFilterOffsetAlpha & 15) << 8 |
  1714. pEncInfo->openParam.EncStdParam.avcParam.disableDeblk << 6 |
  1715. pEncInfo->openParam.EncStdParam.avcParam.constrainedIntraPredFlag << 5 |
  1716. (pEncInfo->openParam.EncStdParam.avcParam.chromaQpOffset & 31);
  1717. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_264_PARA, data);
  1718. if (productId == PRODUCT_ID_980) {
  1719. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_ME_OPTION, (VPU_ME_LINEBUFFER_MODE << 9) |
  1720. (pEncInfo->openParam.meBlkMode << 5) |
  1721. (pEncInfo->openParam.MEUseZeroPmv << 4) |
  1722. (pEncInfo->openParam.MESearchRangeY<<2) |
  1723. pEncInfo->openParam.MESearchRangeX);
  1724. }
  1725. else {
  1726. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_ME_OPTION, (pEncInfo->openParam.meBlkMode << 3) | (pEncInfo->openParam.MEUseZeroPmv << 2) | pEncInfo->openParam.MESearchRange);
  1727. }
  1728. }
  1729. if (productId == PRODUCT_ID_980) {
  1730. data = 0;
  1731. if (pEncInfo->openParam.sliceMode.sliceMode!=0) {
  1732. data = pEncInfo->openParam.sliceMode.sliceSize << 2 |
  1733. (pEncInfo->openParam.sliceMode.sliceSizeMode+1); // encoding mode 0,1,2
  1734. }
  1735. }
  1736. else {
  1737. data = pEncInfo->openParam.sliceMode.sliceSize << 2 |
  1738. pEncInfo->openParam.sliceMode.sliceSizeMode << 1 |
  1739. pEncInfo->openParam.sliceMode.sliceMode;
  1740. }
  1741. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_SLICE_MODE, data);
  1742. if (rcEnable) { // rate control enabled
  1743. if (productId == PRODUCT_ID_980) {
  1744. if (pEncInfo->openParam.bitstreamFormat == STD_AVC) {
  1745. int MinDeltaQp, MaxDeltaQp, QpMin, QpMax;
  1746. data = (pEncInfo->openParam.idrInterval << 21) | (pEncInfo->openParam.rcGopIQpOffsetEn<<20) | ((pEncInfo->openParam.rcGopIQpOffset & 0xF)<<16) | pEncInfo->openParam.gopSize ;
  1747. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_GOP_NUM, data);
  1748. #ifdef SUPPORT_980_RC_LIB
  1749. data = (pEncInfo->openParam.frameSkipDisable<< 31) |
  1750. (pEncInfo->openParam.rcInitDelay << 16) |
  1751. (pEncInfo->openParam.RcHvsMaxDeltaQp);
  1752. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA, data);
  1753. data = (pEncInfo->openParam.HvsQpScaleDiv2 << 25) |(pEncInfo->openParam.EnHvsQp <<24) | (pEncInfo->openParam.EnRowLevelRc <<23) | (pEncInfo->openParam.bitRate<<4)|(rcEnable);
  1754. #else
  1755. data = (pEncInfo->openParam.frameSkipDisable) << 31 |
  1756. pEncInfo->openParam.rcInitDelay << 16 | 0;
  1757. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA, data);
  1758. data = (pEncInfo->openParam.bitRate<<4)|(rcEnable);
  1759. #endif
  1760. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA2, data);
  1761. data = 0;
  1762. if (pEncInfo->openParam.maxIntraSize>0)
  1763. data = (1<<16) | (pEncInfo->openParam.maxIntraSize & 0xFFFF);
  1764. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_MAX_INTRA_SIZE, data);
  1765. if (pEncInfo->openParam.userMinDeltaQp<0)
  1766. MinDeltaQp = 0;
  1767. else
  1768. MinDeltaQp = (1<<6)|pEncInfo->openParam.userMinDeltaQp;
  1769. if (pEncInfo->openParam.userMaxDeltaQp<0)
  1770. MaxDeltaQp = 0;
  1771. else
  1772. MaxDeltaQp = (1<<6)|pEncInfo->openParam.userMaxDeltaQp;
  1773. if (pEncInfo->openParam.userQpMin<0)
  1774. QpMin = 0;
  1775. else
  1776. QpMin = (1<<6)|pEncInfo->openParam.userQpMin;
  1777. if (pEncInfo->openParam.userQpMax<0)
  1778. QpMax = 0;
  1779. else
  1780. QpMax = (1<<6)|pEncInfo->openParam.userQpMax;
  1781. data = MinDeltaQp<<24 | MaxDeltaQp<<16 | QpMin<<8 | QpMax;
  1782. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_QP_RANGE_SET, data);
  1783. }
  1784. else { // MP4
  1785. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_GOP_NUM, pEncInfo->openParam.gopSize);
  1786. #ifdef SUPPORT_980_RC_LIB
  1787. data = (pEncInfo->openParam.frameSkipDisable) << 31 |
  1788. pEncInfo->openParam.rcInitDelay << 16;
  1789. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA, data);
  1790. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_QP_RANGE_SET, 0);
  1791. data = (pEncInfo->openParam.bitRate<<4)|1;
  1792. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA2, data);
  1793. #else
  1794. data = (pEncInfo->openParam.frameSkipDisable) << 31 |
  1795. pEncInfo->openParam.rcInitDelay << 16 |
  1796. pEncInfo->openParam.bitRate<<1 | 1;
  1797. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA, data);
  1798. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_QP_RANGE_SET, 0);
  1799. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA2, 0);
  1800. #endif
  1801. }
  1802. }
  1803. else {
  1804. /* coda960 ENCODER */
  1805. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_GOP_NUM, pEncInfo->openParam.gopSize);
  1806. data = (pEncInfo->openParam.frameSkipDisable) << 31 |
  1807. pEncInfo->openParam.rcInitDelay << 16 |
  1808. pEncInfo->openParam.bitRate<<1 | 1;
  1809. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA, data);
  1810. }
  1811. }
  1812. else {
  1813. if (pEncInfo->openParam.bitstreamFormat == STD_AVC)
  1814. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_GOP_NUM, (pEncInfo->openParam.idrInterval << 21) | pEncInfo->openParam.gopSize);
  1815. else
  1816. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_GOP_NUM, pEncInfo->openParam.gopSize);
  1817. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA, 0);
  1818. if (productId == PRODUCT_ID_980) {
  1819. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_QP_RANGE_SET, 0);
  1820. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA2, 0);
  1821. }
  1822. }
  1823. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_BUF_SIZE, pEncInfo->openParam.vbvBufferSize);
  1824. data = pEncInfo->openParam.intraRefreshNum | pEncInfo->openParam.ConscIntraRefreshEnable<<16;
  1825. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_INTRA_REFRESH, data);
  1826. data = 0;
  1827. if(pEncInfo->openParam.rcIntraQp>=0) {
  1828. data = (1 << 5);
  1829. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_INTRA_QP, pEncInfo->openParam.rcIntraQp);
  1830. }
  1831. else {
  1832. data = 0;
  1833. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_INTRA_QP, (Uint32)-1);
  1834. }
  1835. if(pEncInfo->openParam.userQpMax>=0) {
  1836. data |= (1<<6);
  1837. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_QP_MAX, pEncInfo->openParam.userQpMax);
  1838. }
  1839. else {
  1840. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_QP_MAX, 0);
  1841. }
  1842. if(pEncInfo->openParam.userGamma >= 0) {
  1843. data |= (1<<7);
  1844. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_GAMMA, pEncInfo->openParam.userGamma);
  1845. }
  1846. else {
  1847. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_GAMMA, 0);
  1848. }
  1849. if (pCodecInst->codecMode == AVC_ENC) {
  1850. data |= (pEncInfo->openParam.EncStdParam.avcParam.audEnable << 2);
  1851. }
  1852. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_OPTION, data);
  1853. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_INTERVAL_MODE, (pEncInfo->openParam.mbInterval<<2) | pEncInfo->openParam.rcIntervalMode);
  1854. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_INTRA_WEIGHT, pEncInfo->openParam.intraCostWeight);
  1855. VpuWriteReg(pCodecInst->coreIdx, pEncInfo->streamWrPtrRegAddr, pEncInfo->streamWrPtr);
  1856. VpuWriteReg(pCodecInst->coreIdx, pEncInfo->streamRdPtrRegAddr, pEncInfo->streamRdPtr);
  1857. SetEncFrameMemInfo(pCodecInst);
  1858. val = 0;
  1859. if (pEncInfo->ringBufferEnable == 0) {
  1860. if (pEncInfo->lineBufIntEn)
  1861. val |= (0x1<<6);
  1862. val |= (0x1<<5);
  1863. val |= (0x1<<4);
  1864. }
  1865. else {
  1866. val |= (0x1<<3);
  1867. }
  1868. val |= pEncInfo->openParam.streamEndian;
  1869. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_CTRL, val);
  1870. Coda9BitIssueCommand(pCodecInst->coreIdx, pCodecInst, ENC_SEQ_INIT);
  1871. if (vdi_wait_interrupt(pCodecInst->coreIdx, __VPU_BUSY_TIMEOUT, BIT_INT_REASON) == -1) {
  1872. if (pCodecInst->loggingEnable)
  1873. vdi_log(pCodecInst->coreIdx, ENC_SEQ_INIT, 2);
  1874. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1875. }
  1876. VpuWriteReg(pCodecInst->coreIdx, BIT_INT_CLEAR, 1); // that is OK. HW signal already is clear by device driver
  1877. VpuWriteReg(pCodecInst->coreIdx, BIT_INT_REASON, 0);
  1878. if (pCodecInst->loggingEnable)
  1879. vdi_log(pCodecInst->coreIdx, ENC_SEQ_INIT, 0);
  1880. if (VpuReadReg(pCodecInst->coreIdx, RET_ENC_SEQ_END_SUCCESS) & (1UL<<31))
  1881. return RETCODE_MEMORY_ACCESS_VIOLATION;
  1882. if (VpuReadReg(pCodecInst->coreIdx, RET_ENC_SEQ_END_SUCCESS) == 0)
  1883. return RETCODE_FAILURE;
  1884. pEncInfo->streamWrPtr = VpuReadReg(pCodecInst->coreIdx, pEncInfo->streamWrPtrRegAddr);
  1885. pEncInfo->streamEndflag = VpuReadReg(pCodecInst->coreIdx, BIT_BIT_STREAM_PARAM);
  1886. return RETCODE_SUCCESS;
  1887. }
  1888. RetCode Coda9VpuEncRegisterFramebuffer(CodecInst* instance)
  1889. {
  1890. CodecInst* pCodecInst = instance;
  1891. EncInfo* pEncInfo;
  1892. Int32 i, val;
  1893. RetCode ret;
  1894. PhysicalAddress paraBuffer;
  1895. BYTE frameAddr[MAX_FRAMEBUFFER_COUNT][3][4];
  1896. Int32 stride, height, mapType, num;
  1897. VpuAttr* pAttr = &g_VpuCoreAttributes[instance->coreIdx];
  1898. pEncInfo = &instance->CodecInfo->encInfo;
  1899. stride = pEncInfo->stride;
  1900. height = pEncInfo->frameBufferHeight;
  1901. mapType = pEncInfo->mapType;
  1902. if (pCodecInst->productId == PRODUCT_ID_960) {
  1903. pEncInfo->mapCfg.tiledBaseAddr = pEncInfo->vbFrame.phys_addr;
  1904. }
  1905. if (!ConfigSecAXICoda9(pCodecInst->coreIdx, instance->codecMode, &pEncInfo->secAxiInfo, stride, height, 0))
  1906. return RETCODE_INSUFFICIENT_RESOURCE;
  1907. if (pCodecInst->productId == PRODUCT_ID_960) {
  1908. val = SetTiledMapType(pCodecInst->coreIdx, &pEncInfo->mapCfg, mapType,stride, pEncInfo->openParam.cbcrInterleave, &pEncInfo->dramCfg);
  1909. }
  1910. else {
  1911. if (mapType != LINEAR_FRAME_MAP && mapType != LINEAR_FIELD_MAP)
  1912. val = SetTiledMapType(pCodecInst->coreIdx, &pEncInfo->mapCfg, mapType, (stride > height)?stride:height, pEncInfo->openParam.cbcrInterleave, &pEncInfo->dramCfg);
  1913. else
  1914. val = SetTiledMapType(pCodecInst->coreIdx, &pEncInfo->mapCfg, mapType,stride, pEncInfo->openParam.cbcrInterleave, &pEncInfo->dramCfg);
  1915. }
  1916. if (val == 0)
  1917. return RETCODE_INVALID_PARAM;
  1918. SetEncFrameMemInfo(pCodecInst);
  1919. paraBuffer = VpuReadReg(pCodecInst->coreIdx, BIT_PARA_BUF_ADDR);
  1920. // Let the decoder know the addresses of the frame buffers.
  1921. for (i=0; i<pEncInfo->numFrameBuffers; i++)
  1922. {
  1923. frameAddr[i][0][0] = (pEncInfo->frameBufPool[i].bufY >> 24) & 0xFF;
  1924. frameAddr[i][0][1] = (pEncInfo->frameBufPool[i].bufY >> 16) & 0xFF;
  1925. frameAddr[i][0][2] = (pEncInfo->frameBufPool[i].bufY >> 8) & 0xFF;
  1926. frameAddr[i][0][3] = (pEncInfo->frameBufPool[i].bufY >> 0) & 0xFF;
  1927. frameAddr[i][1][0] = (pEncInfo->frameBufPool[i].bufCb >> 24) & 0xFF;
  1928. frameAddr[i][1][1] = (pEncInfo->frameBufPool[i].bufCb >> 16) & 0xFF;
  1929. frameAddr[i][1][2] = (pEncInfo->frameBufPool[i].bufCb >> 8) & 0xFF;
  1930. frameAddr[i][1][3] = (pEncInfo->frameBufPool[i].bufCb >> 0) & 0xFF;
  1931. frameAddr[i][2][0] = (pEncInfo->frameBufPool[i].bufCr >> 24) & 0xFF;
  1932. frameAddr[i][2][1] = (pEncInfo->frameBufPool[i].bufCr >> 16) & 0xFF;
  1933. frameAddr[i][2][2] = (pEncInfo->frameBufPool[i].bufCr >> 8) & 0xFF;
  1934. frameAddr[i][2][3] = (pEncInfo->frameBufPool[i].bufCr >> 0) & 0xFF;
  1935. }
  1936. VpuWriteMem(pCodecInst->coreIdx, paraBuffer, (BYTE *)frameAddr, sizeof(frameAddr), VDI_BIG_ENDIAN);
  1937. if (pCodecInst->productId == PRODUCT_ID_980) {
  1938. for (i=0; i<pEncInfo->numFrameBuffers; i++) {
  1939. frameAddr[i][0][0] = (pEncInfo->frameBufPool[i].bufYBot >> 24) & 0xFF;
  1940. frameAddr[i][0][1] = (pEncInfo->frameBufPool[i].bufYBot >> 16) & 0xFF;
  1941. frameAddr[i][0][2] = (pEncInfo->frameBufPool[i].bufYBot >> 8) & 0xFF;
  1942. frameAddr[i][0][3] = (pEncInfo->frameBufPool[i].bufYBot >> 0) & 0xFF;
  1943. frameAddr[i][1][0] = (pEncInfo->frameBufPool[i].bufCbBot >> 24) & 0xFF;
  1944. frameAddr[i][1][1] = (pEncInfo->frameBufPool[i].bufCbBot >> 16) & 0xFF;
  1945. frameAddr[i][1][2] = (pEncInfo->frameBufPool[i].bufCbBot >> 8) & 0xFF;
  1946. frameAddr[i][1][3] = (pEncInfo->frameBufPool[i].bufCbBot >> 0) & 0xFF;
  1947. frameAddr[i][2][0] = (pEncInfo->frameBufPool[i].bufCrBot >> 24) & 0xFF;
  1948. frameAddr[i][2][1] = (pEncInfo->frameBufPool[i].bufCrBot >> 16) & 0xFF;
  1949. frameAddr[i][2][2] = (pEncInfo->frameBufPool[i].bufCrBot >> 8) & 0xFF;
  1950. frameAddr[i][2][3] = (pEncInfo->frameBufPool[i].bufCrBot >> 0) & 0xFF;
  1951. }
  1952. VpuWriteMem(pCodecInst->coreIdx, paraBuffer+384+128, (BYTE *)frameAddr, sizeof(frameAddr), VDI_BIG_ENDIAN);
  1953. }
  1954. // Tell the codec how much frame buffers were allocated.
  1955. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_BUF_NUM, pEncInfo->numFrameBuffers);
  1956. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_BUF_STRIDE, stride);
  1957. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_BIT_ADDR, pEncInfo->secAxiInfo.u.coda9.bufBitUse);
  1958. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_IPACDC_ADDR, pEncInfo->secAxiInfo.u.coda9.bufIpAcDcUse);
  1959. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_DBKY_ADDR, pEncInfo->secAxiInfo.u.coda9.bufDbkYUse);
  1960. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_DBKC_ADDR, pEncInfo->secAxiInfo.u.coda9.bufDbkCUse);
  1961. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_OVL_ADDR, pEncInfo->secAxiInfo.u.coda9.bufOvlUse);
  1962. if (pAttr->framebufferCacheType == FramebufCacheMaverickII) {
  1963. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_CACHE_CONFIG, pEncInfo->cacheConfig.type2.CacheMode);
  1964. }
  1965. else if (pAttr->framebufferCacheType == FramebufCacheMaverickI) {
  1966. // Maverick Cache Configuration
  1967. val = (pEncInfo->cacheConfig.type1.luma.cfg.PageSizeX << 28) |
  1968. (pEncInfo->cacheConfig.type1.luma.cfg.PageSizeY << 24) |
  1969. (pEncInfo->cacheConfig.type1.luma.cfg.CacheSizeX << 20) |
  1970. (pEncInfo->cacheConfig.type1.luma.cfg.CacheSizeY << 16) |
  1971. (pEncInfo->cacheConfig.type1.chroma.cfg.PageSizeX << 12) |
  1972. (pEncInfo->cacheConfig.type1.chroma.cfg.PageSizeY << 8) |
  1973. (pEncInfo->cacheConfig.type1.chroma.cfg.CacheSizeX << 4) |
  1974. (pEncInfo->cacheConfig.type1.chroma.cfg.CacheSizeY << 0);
  1975. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_CACHE_SIZE, val);
  1976. val = (pEncInfo->cacheConfig.type1.Bypass << 4) |
  1977. (pEncInfo->cacheConfig.type1.DualConf << 2) |
  1978. (pEncInfo->cacheConfig.type1.PageMerge << 0);
  1979. val = val << 24;
  1980. val |= (pEncInfo->cacheConfig.type1.luma.cfg.BufferSize << 16) |
  1981. (pEncInfo->cacheConfig.type1.chroma.cfg.BufferSize << 8) |
  1982. (pEncInfo->cacheConfig.type1.chroma.cfg.BufferSize << 8);
  1983. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_CACHE_CONFIG, val);
  1984. }
  1985. num = pEncInfo->numFrameBuffers;
  1986. if (pCodecInst->productId == PRODUCT_ID_960) {
  1987. Uint32 subsampleLumaSize = stride*height;
  1988. Uint32 subsampleChromaSize = stride*height/4; // FORMAT_420
  1989. vpu_buffer_t vbBuf;
  1990. FrameBuffer* pFb;
  1991. vbBuf.size = subsampleLumaSize + 2*subsampleChromaSize;
  1992. vbBuf.phys_addr = (PhysicalAddress)0;
  1993. if (vdi_allocate_dma_memory(pCodecInst->coreIdx, &vbBuf) < 0) {
  1994. pEncInfo->vbSubSampFrame.size = 0;
  1995. pEncInfo->vbSubSampFrame.phys_addr = 0;
  1996. return RETCODE_INSUFFICIENT_RESOURCE;
  1997. }
  1998. pFb = &pEncInfo->frameBufPool[num];
  1999. pFb->bufY = vbBuf.phys_addr;
  2000. pFb->bufCb = (PhysicalAddress)-1;
  2001. pFb->bufCr = (PhysicalAddress)-1;
  2002. pFb->updateFbInfo = TRUE;
  2003. ret = AllocateLinearFrameBuffer(LINEAR_FRAME_MAP, pFb, 1, subsampleLumaSize, subsampleChromaSize);
  2004. if (ret != RETCODE_SUCCESS) {
  2005. pEncInfo->vbSubSampFrame.size = 0;
  2006. pEncInfo->vbSubSampFrame.phys_addr = 0;
  2007. return RETCODE_INSUFFICIENT_RESOURCE;
  2008. }
  2009. pEncInfo->vbSubSampFrame = vbBuf;
  2010. num++;
  2011. // Set Sub-Sampling buffer for ME-Reference and DBK-Reconstruction
  2012. // BPU will swap below two buffer internally every pic by pic
  2013. val = GetXY2AXIAddr(&pEncInfo->mapCfg, 0, 0, 0, stride, pFb);
  2014. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_SUBSAMP_A, val);
  2015. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_SUBSAMP_B, val+(stride*height/2));
  2016. if (pCodecInst->codecMode == AVC_ENC && pCodecInst->codecModeAux == AVC_AUX_MVC) {
  2017. vbBuf.size = subsampleLumaSize + 2*subsampleChromaSize;
  2018. vbBuf.phys_addr = (PhysicalAddress)0;
  2019. if (vdi_allocate_dma_memory(pCodecInst->coreIdx, &vbBuf) < 0) {
  2020. pEncInfo->vbSubSampFrame.size = 0;
  2021. pEncInfo->vbSubSampFrame.phys_addr = 0;
  2022. return RETCODE_INSUFFICIENT_RESOURCE;
  2023. }
  2024. pFb = &pEncInfo->frameBufPool[num];
  2025. pFb->bufY = vbBuf.phys_addr;
  2026. pFb->bufCb = (PhysicalAddress)-1;
  2027. pFb->bufCr = (PhysicalAddress)-1;
  2028. pFb->updateFbInfo = TRUE;
  2029. ret = AllocateLinearFrameBuffer(LINEAR_FRAME_MAP, pFb, 1, subsampleLumaSize, subsampleChromaSize);
  2030. if (ret != RETCODE_SUCCESS) {
  2031. pEncInfo->vbMvcSubSampFrame.size = 0;
  2032. pEncInfo->vbMvcSubSampFrame.phys_addr = 0;
  2033. return RETCODE_INSUFFICIENT_RESOURCE;
  2034. }
  2035. pEncInfo->vbMvcSubSampFrame = vbBuf;
  2036. val = GetXY2AXIAddr(&pEncInfo->mapCfg, 0, 0, 0, stride, pFb);
  2037. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_SUBSAMP_A_MVC, val);
  2038. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_SUBSAMP_B_MVC, val+(stride*height/2));
  2039. }
  2040. }
  2041. if (pCodecInst->codecMode == MP4_ENC) {
  2042. // MPEG4 Encoder Data-Partitioned bitstream temporal buffer
  2043. pEncInfo->vbScratch.size = SIZE_MP4ENC_DATA_PARTITION;
  2044. if (vdi_allocate_dma_memory(pCodecInst->coreIdx, &pEncInfo->vbScratch)<0)
  2045. return RETCODE_INSUFFICIENT_RESOURCE;
  2046. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_DP_BUF_BASE, pEncInfo->vbScratch.phys_addr);
  2047. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_DP_BUF_SIZE, pEncInfo->vbScratch.size>>10);
  2048. }
  2049. SetPendingInst(pCodecInst->coreIdx, pCodecInst);
  2050. Coda9BitIssueCommand(pCodecInst->coreIdx, pCodecInst, SET_FRAME_BUF);
  2051. if (vdi_wait_vpu_busy(pCodecInst->coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1) {
  2052. if (pCodecInst->loggingEnable)
  2053. vdi_log(pCodecInst->coreIdx, SET_FRAME_BUF, 2);
  2054. return RETCODE_VPU_RESPONSE_TIMEOUT;
  2055. }
  2056. if (pCodecInst->loggingEnable)
  2057. vdi_log(pCodecInst->coreIdx, SET_FRAME_BUF, 0);
  2058. if (VpuReadReg(pCodecInst->coreIdx, RET_SET_FRAME_SUCCESS) & (1UL<<31)) {
  2059. return RETCODE_MEMORY_ACCESS_VIOLATION;
  2060. }
  2061. return RETCODE_SUCCESS;
  2062. }
  2063. RetCode Coda9VpuEncode(CodecInst* pCodecInst, EncParam* param)
  2064. {
  2065. EncInfo* pEncInfo;
  2066. FrameBuffer* pSrcFrame;
  2067. Uint32 rotMirMode;
  2068. Uint32 val;
  2069. vpu_instance_pool_t *vip;
  2070. #ifdef SUPPORT_980_RC_LIB
  2071. int outQp = 0;
  2072. int target_pic_bit = 0;
  2073. int hrd_buf_level = 0;
  2074. int hrd_buf_size = 0;
  2075. #endif
  2076. #ifdef CLIP_PIC_DELTA_QP
  2077. int row_max_dqp_minus = 0;
  2078. int row_max_dqp_plus = 0;
  2079. #endif
  2080. pEncInfo = &pCodecInst->CodecInfo->encInfo;
  2081. vip = (vpu_instance_pool_t *)vdi_get_instance_pool(pCodecInst->coreIdx);
  2082. if (!vip) {
  2083. return RETCODE_INVALID_HANDLE;
  2084. }
  2085. pSrcFrame = param->sourceFrame;
  2086. rotMirMode = 0;
  2087. if (pEncInfo->rotationEnable == TRUE) {
  2088. switch (pEncInfo->rotationAngle) {
  2089. case 0:
  2090. rotMirMode |= 0x0;
  2091. break;
  2092. case 90:
  2093. rotMirMode |= 0x1;
  2094. break;
  2095. case 180:
  2096. rotMirMode |= 0x2;
  2097. break;
  2098. case 270:
  2099. rotMirMode |= 0x3;
  2100. break;
  2101. }
  2102. }
  2103. if (pEncInfo->mirrorEnable == TRUE) {
  2104. switch (pEncInfo->mirrorDirection) {
  2105. case MIRDIR_NONE :
  2106. rotMirMode |= 0x0;
  2107. break;
  2108. case MIRDIR_VER :
  2109. rotMirMode |= 0x4;
  2110. break;
  2111. case MIRDIR_HOR :
  2112. rotMirMode |= 0x8;
  2113. break;
  2114. case MIRDIR_HOR_VER :
  2115. rotMirMode |= 0xc;
  2116. break;
  2117. }
  2118. }
  2119. #ifdef SUPPORT_980_RC_LIB
  2120. // @ Step 1 :
  2121. // Get Qp for non-roi region
  2122. //====================================
  2123. if (pCodecInst->productId == PRODUCT_ID_980 && pCodecInst->codecMode == AVC_ENC && pEncInfo->openParam.rcEnable == 4) {
  2124. // outQp will be returned a QP for non-roi region when rc mode==4 && roi enabled.
  2125. // outQp will be returned a QP for one picture when rc mode==4 && roi disabled.
  2126. int min_qp;
  2127. int max_qp;
  2128. int pic_idx;
  2129. int gop_num;
  2130. int slice_type; // 0 = Intra, 1 =inter
  2131. int mvc_second_view;
  2132. int is_all_i = (pEncInfo->openParam.gopSize == 1) ;
  2133. pic_idx = pEncInfo->openParam.EncStdParam.avcParam.fieldFlag ? 2*pEncInfo->frameIdx+pEncInfo->fieldDone: pEncInfo->frameIdx;
  2134. gop_num = pEncInfo->openParam.EncStdParam.avcParam.fieldFlag ? 2*pEncInfo->openParam.gopSize : pEncInfo->openParam.gopSize;
  2135. mvc_second_view = 0;
  2136. UNREFERENCED_PARAMETER(mvc_second_view);
  2137. if (gop_num == 0) // Only first I
  2138. {
  2139. if (pic_idx == 0 || (pic_idx == 1))
  2140. slice_type=0;
  2141. else
  2142. slice_type=1;
  2143. }
  2144. else if (is_all_i ) // All I
  2145. {
  2146. slice_type =0;
  2147. }
  2148. else
  2149. {
  2150. if ((pic_idx % gop_num) == 0 ||(pic_idx % gop_num) == 1) // I frame
  2151. slice_type=0;
  2152. else // P frame
  2153. slice_type=1;
  2154. }
  2155. min_qp = pEncInfo->openParam.userQpMin;
  2156. max_qp = pEncInfo->openParam.userQpMax;
  2157. #ifdef AUTO_FRM_SKIP_DROP
  2158. frm_rc_pic_init(&pEncInfo->frm_rc, !slice_type,
  2159. min_qp, max_qp,
  2160. pEncInfo->openParam.bitRate,
  2161. #ifdef CLIP_PIC_DELTA_QP
  2162. &row_max_dqp_minus, &row_max_dqp_plus,
  2163. #endif
  2164. pEncInfo->curr_long_term,
  2165. &outQp, &target_pic_bit, &hrd_buf_level, &hrd_buf_size);
  2166. if(pEncInfo->frm_rc.rc_pic.frame_drop)
  2167. return RETCODE_FRAME_DROP;
  2168. #else
  2169. frm_rc_pic_init(&pEncInfo->frm_rc, !slice_type,
  2170. min_qp, max_qp,
  2171. #ifdef CLIP_PIC_DELTA_QP
  2172. &row_max_dqp_minus, &row_max_dqp_plus,
  2173. #endif
  2174. pEncInfo->curr_long_term,
  2175. &outQp, &target_pic_bit, &hrd_buf_level, &hrd_buf_size);
  2176. #endif
  2177. }
  2178. else if(pCodecInst->productId == PRODUCT_ID_980 && pCodecInst->codecMode == AVC_ENC)// && pCodecInst->codecModeAux == AVC_AUX_SVC)
  2179. {
  2180. outQp = get_temporal_dqp( &pEncInfo->frm_rc, pEncInfo->enc_idx_modulo, pEncInfo->slice_type, pEncInfo->curr_long_term, param->quantParam);
  2181. }
  2182. else
  2183. outQp = param->quantParam;
  2184. #endif
  2185. if (pCodecInst->productId == PRODUCT_ID_980) {
  2186. rotMirMode |= ((pSrcFrame->endian&0x03)<<16);
  2187. rotMirMode |= ((pSrcFrame->cbcrInterleave&0x01)<<18);
  2188. rotMirMode |= ((pSrcFrame->sourceLBurstEn&0x01)<<4);
  2189. }
  2190. else {
  2191. rotMirMode |= ((pSrcFrame->sourceLBurstEn&0x01)<<4);
  2192. rotMirMode |= ((pSrcFrame->cbcrInterleave&0x01)<<18);
  2193. rotMirMode |= pEncInfo->openParam.nv21 << 21;
  2194. }
  2195. if (pCodecInst->productId == PRODUCT_ID_980 && pCodecInst->codecMode == AVC_ENC)
  2196. {
  2197. }
  2198. if (pCodecInst->productId == PRODUCT_ID_960) {
  2199. if (pEncInfo->mapType > LINEAR_FRAME_MAP && pEncInfo->mapType <= TILED_MIXED_V_MAP) {
  2200. SetTiledFrameBase(pCodecInst->coreIdx, pEncInfo->vbFrame.phys_addr);
  2201. }
  2202. else {
  2203. SetTiledFrameBase(pCodecInst->coreIdx, 0);
  2204. }
  2205. }
  2206. if (pEncInfo->mapType != LINEAR_FRAME_MAP && pEncInfo->mapType != LINEAR_FIELD_MAP) {
  2207. if (pEncInfo->stride > pEncInfo->frameBufferHeight)
  2208. val = SetTiledMapType(pCodecInst->coreIdx, &pEncInfo->mapCfg, pEncInfo->mapType, pEncInfo->stride, pEncInfo->openParam.cbcrInterleave, &pEncInfo->dramCfg);
  2209. else
  2210. val = SetTiledMapType(pCodecInst->coreIdx, &pEncInfo->mapCfg, pEncInfo->mapType, pEncInfo->frameBufferHeight, pEncInfo->openParam.cbcrInterleave, &pEncInfo->dramCfg);
  2211. } else {
  2212. val = SetTiledMapType(pCodecInst->coreIdx, &pEncInfo->mapCfg, pEncInfo->mapType, pEncInfo->stride, pEncInfo->openParam.cbcrInterleave, &pEncInfo->dramCfg);
  2213. }
  2214. if (val == 0) {
  2215. return RETCODE_INVALID_PARAM;
  2216. }
  2217. rotMirMode |= pEncInfo->openParam.nv21 << 21;
  2218. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_ROT_MODE, rotMirMode);
  2219. #ifdef SUPPORT_980_RC_LIB
  2220. //=========================================================================================================================
  2221. // @ Step 3 :
  2222. // set Qp for non-roi region or Qp for picture.
  2223. //=========================================================================================================================
  2224. if (pCodecInst->productId == PRODUCT_ID_980 && pCodecInst->codecMode == AVC_ENC )
  2225. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_QS, outQp);
  2226. else
  2227. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_QS, param->quantParam);
  2228. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_TARGET_BIT, target_pic_bit);
  2229. #ifdef ROI_MB_RC
  2230. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_RC_BUF_LEVEL, hrd_buf_level);
  2231. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_RC_BUF_SIZE, hrd_buf_size);
  2232. #ifdef AUTO_FRM_SKIP_DROP
  2233. pEncInfo->frm_rc.rc_pic.frame_skip |= param->skipPicture;
  2234. #ifdef CLIP_PIC_DELTA_QP
  2235. if(param->coda9RoiEnable)
  2236. {
  2237. row_max_dqp_plus = pEncInfo->openParam.roi_max_delta_qp_plus;
  2238. row_max_dqp_minus = pEncInfo->openParam.roi_max_delta_qp_minus;
  2239. }
  2240. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_RC_QP,
  2241. (row_max_dqp_minus << 26 )|
  2242. (row_max_dqp_plus << 20)|
  2243. (pEncInfo->frm_rc.rc_pic.frame_drop << 19) |
  2244. (pEncInfo->frm_rc.rc_pic.frame_skip << 18) |
  2245. (outQp << 12) |
  2246. (pEncInfo->openParam.roi_max_delta_qp_plus << 6) |
  2247. pEncInfo->openParam.roi_max_delta_qp_minus);// (outQp << 12) | (pEncInfo->openParam.roi_max_delta_qp_plus << 6) | pEncInfo->openParam.roi_max_delta_qp_minus );
  2248. #else
  2249. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_RC_QP,
  2250. (pEncInfo->frm_rc.rc_pic.frame_drop << 19) |
  2251. (pEncInfo->frm_rc.rc_pic.frame_skip << 18) |
  2252. (outQp << 12) |
  2253. (pEncInfo->openParam.roi_max_delta_qp_plus << 6) |
  2254. pEncInfo->openParam.roi_max_delta_qp_minus);// (outQp << 12) | (pEncInfo->openParam.roi_max_delta_qp_plus << 6) | pEncInfo->openParam.roi_max_delta_qp_minus );
  2255. #endif
  2256. #else
  2257. #ifdef CLIP_PIC_DELTA_QP
  2258. if(param->coda9RoiEnable)
  2259. {
  2260. row_max_dqp_plus = pEncInfo->openParam.roi_max_delta_qp_plus;
  2261. row_max_dqp_minus = pEncInfo->openParam.roi_max_delta_qp_minus;
  2262. }
  2263. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_RC_QP,(row_max_dqp_minus << 26 )| (row_max_dqp_plus << 20)| 0 << 18 | (outQp << 12) | (pEncInfo->openParam.roi_max_delta_qp_plus << 6) | pEncInfo->openParam.roi_max_delta_qp_minus);// (outQp << 12) | (pEncInfo->openParam.roi_max_delta_qp_plus << 6) | pEncInfo->openParam.roi_max_delta_qp_minus );
  2264. #else
  2265. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_RC_QP,0 << 18 | (outQp << 12) | (pEncInfo->openParam.roi_max_delta_qp_plus << 6) | pEncInfo->openParam.roi_max_delta_qp_minus);// (outQp << 12) | (pEncInfo->openParam.roi_max_delta_qp_plus << 6) | pEncInfo->openParam.roi_max_delta_qp_minus );
  2266. #endif
  2267. #endif
  2268. #else
  2269. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_QP, outQp);
  2270. #endif
  2271. #else
  2272. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_QS, param->quantParam);
  2273. #endif
  2274. if (param->skipPicture) {
  2275. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_OPTION, 1);
  2276. }
  2277. else {
  2278. // Registering Source Frame Buffer information
  2279. // Hide GDI IF under FW level
  2280. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_INDEX, pSrcFrame->myIndex);
  2281. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_STRIDE, pSrcFrame->stride);
  2282. if (pEncInfo->openParam.cbcrOrder == CBCR_ORDER_NORMAL) {
  2283. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_ADDR_Y, pSrcFrame->bufY);
  2284. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_ADDR_CB, pSrcFrame->bufCb);
  2285. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_ADDR_CR, pSrcFrame->bufCr);
  2286. }
  2287. else { // CBCR_ORDER_REVERSED (YV12)
  2288. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_ADDR_Y, pSrcFrame->bufY);
  2289. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_ADDR_CB, pSrcFrame->bufCr);
  2290. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_ADDR_CR, pSrcFrame->bufCb);
  2291. }
  2292. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_OPTION, (param->forceIPicture << 1 & 0x2));
  2293. }
  2294. if (pEncInfo->ringBufferEnable == 0) {
  2295. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_BB_START, param->picStreamBufferAddr);
  2296. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_BB_SIZE, param->picStreamBufferSize/1024); // size in KB
  2297. VpuWriteReg(pCodecInst->coreIdx, pEncInfo->streamRdPtrRegAddr, param->picStreamBufferAddr);
  2298. pEncInfo->streamRdPtr = param->picStreamBufferAddr;
  2299. }
  2300. val = 0;
  2301. val = (
  2302. (pEncInfo->secAxiInfo.u.coda9.useBitEnable&0x01)<<0 |
  2303. (pEncInfo->secAxiInfo.u.coda9.useIpEnable&0x01)<<1 |
  2304. (pEncInfo->secAxiInfo.u.coda9.useDbkYEnable&0x01)<<2 |
  2305. (pEncInfo->secAxiInfo.u.coda9.useDbkCEnable&0x01)<<3 |
  2306. (pEncInfo->secAxiInfo.u.coda9.useOvlEnable&0x01)<<4 |
  2307. (pEncInfo->secAxiInfo.u.coda9.useBtpEnable&0x01)<<5 |
  2308. (pEncInfo->secAxiInfo.u.coda9.useBitEnable&0x01)<<8 |
  2309. (pEncInfo->secAxiInfo.u.coda9.useIpEnable&0x01)<<9 |
  2310. (pEncInfo->secAxiInfo.u.coda9.useDbkYEnable&0x01)<<10 |
  2311. (pEncInfo->secAxiInfo.u.coda9.useDbkCEnable&0x01)<<11 |
  2312. (pEncInfo->secAxiInfo.u.coda9.useOvlEnable&0x01)<<12 |
  2313. (pEncInfo->secAxiInfo.u.coda9.useBtpEnable&0x01)<<13 );
  2314. VpuWriteReg(pCodecInst->coreIdx, BIT_AXI_SRAM_USE, val);
  2315. VpuWriteReg(pCodecInst->coreIdx, pEncInfo->streamWrPtrRegAddr, pEncInfo->streamWrPtr);
  2316. VpuWriteReg(pCodecInst->coreIdx, pEncInfo->streamRdPtrRegAddr, pEncInfo->streamRdPtr);
  2317. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_PARAM, pEncInfo->streamEndflag);
  2318. SetEncFrameMemInfo(pCodecInst);
  2319. val = 0;
  2320. if (pEncInfo->ringBufferEnable == 0) {
  2321. if (pEncInfo->lineBufIntEn)
  2322. val |= (0x1<<6);
  2323. val |= (0x1<<5);
  2324. val |= (0x1<<4);
  2325. }
  2326. else {
  2327. val |= (0x1<<3);
  2328. }
  2329. val |= pEncInfo->openParam.streamEndian;
  2330. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_CTRL, val);
  2331. Coda9BitIssueCommand(pCodecInst->coreIdx, pCodecInst, PIC_RUN);
  2332. return RETCODE_SUCCESS;
  2333. }
  2334. RetCode Coda9VpuEncGetResult(CodecInst* pCodecInst, EncOutputInfo* info)
  2335. {
  2336. EncInfo* pEncInfo;
  2337. PhysicalAddress rdPtr;
  2338. PhysicalAddress wrPtr;
  2339. Uint32 pic_enc_result;
  2340. pEncInfo = &pCodecInst->CodecInfo->encInfo;
  2341. if (pCodecInst->loggingEnable)
  2342. vdi_log(pCodecInst->coreIdx, PIC_RUN, 0);
  2343. pic_enc_result = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_SUCCESS);
  2344. if (pic_enc_result & (1UL<<31)) {
  2345. return RETCODE_MEMORY_ACCESS_VIOLATION;
  2346. }
  2347. #ifdef SUPPORT_980_RC_LIB
  2348. #ifdef AUTO_FRM_SKIP_DROP
  2349. if (pCodecInst->productId == PRODUCT_ID_980 && pCodecInst->codecMode == AVC_ENC && pEncInfo->openParam.rcEnable == 4) {
  2350. if (pEncInfo->frm_rc.rc_pic.frame_drop) {
  2351. info->picDropped = 1;
  2352. frm_rc_pic_end(&pEncInfo->frm_rc, 0, 0, 1);
  2353. return RETCODE_SUCCESS;
  2354. }
  2355. info->picDropped = 0;
  2356. }
  2357. #endif
  2358. #endif
  2359. if (pCodecInst->productId == PRODUCT_ID_980) {
  2360. if (pic_enc_result & 2) { //top field coding done
  2361. if (!pEncInfo->fieldDone)
  2362. pEncInfo->fieldDone = 1;
  2363. }
  2364. else
  2365. {
  2366. pEncInfo->frameIdx = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_FRAME_NUM);
  2367. pEncInfo->fieldDone = 0;
  2368. }
  2369. }
  2370. info->picType = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_TYPE);
  2371. if (pEncInfo->ringBufferEnable == 0) {
  2372. rdPtr = VpuReadReg(pCodecInst->coreIdx, pEncInfo->streamRdPtrRegAddr);
  2373. wrPtr = VpuReadReg(pCodecInst->coreIdx, pEncInfo->streamWrPtrRegAddr);
  2374. info->bitstreamBuffer = rdPtr;
  2375. info->bitstreamSize = wrPtr - rdPtr;
  2376. }
  2377. info->numOfSlices = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_SLICE_NUM);
  2378. info->bitstreamWrapAround = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_FLAG);
  2379. info->reconFrameIndex = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_FRAME_IDX);
  2380. if (info->reconFrameIndex < MAX_REG_FRAME) {
  2381. info->reconFrame = pEncInfo->frameBufPool[info->reconFrameIndex];
  2382. }
  2383. info->encSrcIdx = info->reconFrameIndex;
  2384. pEncInfo->streamWrPtr = VpuReadReg(pCodecInst->coreIdx, pEncInfo->streamWrPtrRegAddr);
  2385. pEncInfo->streamEndflag = VpuReadReg(pCodecInst->coreIdx, BIT_BIT_STREAM_PARAM);
  2386. #ifdef SUPPORT_PIC_INFO_REPORT
  2387. info->intraMbNum = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_INTRA_MB_NUM);
  2388. info->skippedMbNum = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_SKPPED_MB_NUM);
  2389. info->sumQp = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_SUM_QP);
  2390. info->sadSumLuma = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_SAD_LUMA);
  2391. info->sadSumChroma = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_SAD_CHROMA);
  2392. #endif
  2393. info->frameCycle = VpuReadReg(pCodecInst->coreIdx, BIT_FRAME_CYCLE);
  2394. info->rdPtr = pEncInfo->streamRdPtr;
  2395. info->wrPtr = pEncInfo->streamWrPtr;
  2396. #ifdef SUPPORT_980_RC_LIB
  2397. //=========================================================================================================================
  2398. // @ Step 3 :
  2399. // set Qp for non-roi region or Qp for picture.
  2400. //=========================================================================================================================
  2401. if (pCodecInst->productId == PRODUCT_ID_980 && pCodecInst->codecMode == AVC_ENC && pEncInfo->openParam.rcEnable == 4) {
  2402. Uint32 real_pic_bit;
  2403. int temp;
  2404. temp = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_RC);
  2405. real_pic_bit = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_USED_BIT);
  2406. frm_rc_pic_end(&pEncInfo->frm_rc, real_pic_bit, (temp & 0x7E) >>1, pEncInfo->frm_rc.rc_pic.frame_skip & 0x1);
  2407. pEncInfo->prevWrPtr = info->wrPtr;
  2408. }
  2409. if (pCodecInst->productId == PRODUCT_ID_980 && pCodecInst->codecMode == AVC_ENC && pCodecInst->codecModeAux == AVC_AUX_SVC)
  2410. {
  2411. int i;
  2412. for(i = 0; i < pEncInfo->num_mmco1; i++)
  2413. pEncInfo->frm[pEncInfo->mmco1_frmidx[i]].used_for_ref = 0;
  2414. if(pEncInfo->is_skip_picture)
  2415. {
  2416. if (pEncInfo->curr_long_term)
  2417. {
  2418. if (pEncInfo->longterm_frmidx >= 0)
  2419. pEncInfo->curr_frm->used_for_ref = 0;
  2420. pEncInfo->longterm_frmidx = pEncInfo->curr_frm - pEncInfo->frm;
  2421. }
  2422. pEncInfo->frm[pEncInfo->ref_pic_list].frame_num = pEncInfo->curr_frm->frame_num;
  2423. pEncInfo->frm[pEncInfo->ref_pic_list].poc = pEncInfo->curr_frm->poc;
  2424. pEncInfo->frm[pEncInfo->ref_pic_list].slice_type = pEncInfo->curr_frm->slice_type;
  2425. pEncInfo->frm[pEncInfo->ref_pic_list].used_for_ref = pEncInfo->curr_frm->used_for_ref;
  2426. pEncInfo->curr_frm->used_for_ref = 0;
  2427. }
  2428. else
  2429. {
  2430. if (pEncInfo->curr_long_term)
  2431. {
  2432. if (pEncInfo->longterm_frmidx >= 0)
  2433. pEncInfo->frm[pEncInfo->longterm_frmidx].used_for_ref = 0;
  2434. pEncInfo->longterm_frmidx = pEncInfo->curr_frm - pEncInfo->frm;
  2435. }
  2436. }
  2437. pEncInfo->enc_idx_modulo++;
  2438. if(pEncInfo->enc_idx_modulo == pEncInfo->gop_size)
  2439. {
  2440. pEncInfo->enc_idx_modulo = 0;
  2441. pEncInfo->enc_idx_gop += pEncInfo->gop_size;
  2442. }
  2443. }
  2444. #endif
  2445. return RETCODE_SUCCESS;
  2446. }
  2447. RetCode Coda9VpuEncGiveCommand(CodecInst* pCodecInst, CodecCommand cmd, void* param)
  2448. {
  2449. RetCode ret = RETCODE_SUCCESS;
  2450. UNREFERENCED_PARAMETER(cmd);
  2451. UNREFERENCED_PARAMETER(param);
  2452. switch (cmd) {
  2453. default:
  2454. ret = RETCODE_NOT_SUPPORTED_FEATURE;
  2455. }
  2456. return ret;
  2457. }