debug.c 63 KB

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  1. // SPDX-License-Identifier: LGPL-2.1 OR BSD-3-Clause
  2. //--=========================================================================--
  3. // This file is a part of VPU Reference API project
  4. //-----------------------------------------------------------------------------
  5. //
  6. // This confidential and proprietary software may be used only
  7. // as authorized by a licensing agreement from Chips&Media Inc.
  8. // In the event of publication, the following notice is applicable:
  9. //
  10. // (C) COPYRIGHT CHIPS&MEDIA INC.
  11. // ALL RIGHTS RESERVED
  12. //
  13. // The entire notice above must be reproduced on all authorized
  14. // copies.
  15. //
  16. //--=========================================================================--
  17. #include "config.h"
  18. #include <stdio.h>
  19. #include <assert.h>
  20. #include <string.h>
  21. #include <time.h>
  22. #include "wave/common/common_regdefine.h"
  23. #include "wave/wave4/wave4_regdefine.h"
  24. #include "wave/wave5/wave5_regdefine.h"
  25. #include "wave/wave5/wave5.h"
  26. #include "coda9/coda9_regdefine.h"
  27. #include "wave/common/common_vpuconfig.h"
  28. #if defined(PLATFORM_LINUX) || defined(PLATFORM_QNX)
  29. #include <sys/types.h>
  30. #include <sys/stat.h>
  31. #include <errno.h>
  32. #include <unistd.h>
  33. #include <time.h>
  34. #endif
  35. #include "main_helper.h"
  36. #include "misc/debug.h"
  37. enum { False, True };
  38. void InitializeDebugEnv(
  39. Uint32 productId,
  40. Uint32 options
  41. )
  42. {
  43. UNREFERENCED_PARAMETER(productId);
  44. }
  45. void ReleaseDebugEnv(
  46. void
  47. )
  48. {
  49. }
  50. static void DisplayVceEncDebugCommon(int core_idx, int vcore_idx, int set_mode, int debug0, int debug1, int debug2)
  51. {
  52. int reg_val;
  53. VLOG(ERR, "---------------Common Debug INFO-----------------\n");
  54. WriteRegVCE(core_idx,vcore_idx, set_mode,0 );
  55. reg_val = ReadRegVCE(core_idx, vcore_idx, debug0);
  56. VLOG(ERR,"\t- pipe_on : 0x%x\n", ((reg_val >> 8) & 0xf));
  57. VLOG(ERR,"\t- cur_pipe : 0x%x\n", ((reg_val >> 12) & 0xf));
  58. VLOG(ERR,"\t- cur_s2ime : 0x%x\n", ((reg_val >> 16) & 0xf));
  59. VLOG(ERR,"\t- cur_s2cache : 0x%x\n", ((reg_val >> 20) & 0x7));
  60. VLOG(ERR,"\t- subblok_done : 0x%x\n", ((reg_val >> 24) & 0x7f));
  61. reg_val = ReadRegVCE(core_idx, vcore_idx, debug1);
  62. VLOG(ERR,"\t- subblok_done : SFU 0x%x LF 0x%x RDO 0x%x IMD 0x%x FME 0x%x IME 0x%x\n", ((reg_val >> 5) & 0x1), ((reg_val >> 4) & 0x1), ((reg_val >> 3) & 0x1), ((reg_val >> 2) & 0x1), ((reg_val >> 1) & 0x1), ((reg_val >> 0) & 0x1));
  63. VLOG(ERR,"\t- pipe_on : 0x%x\n", ((reg_val >> 8) & 0xf));
  64. VLOG(ERR,"\t- cur_pipe : 0x%x\n", ((reg_val >> 12) & 0xf));
  65. VLOG(ERR,"\t- cur_s2cache : 0x%x\n", ((reg_val >> 16) & 0x7));
  66. VLOG(ERR,"\t- cur_s2ime : 0x%x\n", ((reg_val >> 24) & 0xf));
  67. reg_val = ReadRegVCE(core_idx, vcore_idx, debug2);
  68. VLOG(ERR,"\t- main_ctu_ypos : 0x%x\n", ((reg_val >> 0) & 0xff));
  69. VLOG(ERR,"\t- main_ctu_xpos : 0x%x\n", ((reg_val >> 8) & 0xff));
  70. VLOG(ERR,"\t- o_prp_ctu_ypos: 0x%x\n", ((reg_val >> 16) & 0xff));
  71. VLOG(ERR,"\t- o_prp_ctu_xpos: 0x%x\n", ((reg_val >> 24) & 0xff));
  72. SetClockGate(0, 1);
  73. reg_val = vdi_fio_read_register(core_idx, W4_GDI_VCORE0_BUS_STATUS);
  74. VLOG(ERR,"\t- =========== GDI_BUS_STATUS ========== \n");
  75. VLOG(ERR,"\t- pri_bus_busy: 0x%x\n", ((reg_val >> 0) & 0x1));
  76. VLOG(ERR,"\t- sec_bus_busy: 0x%x\n", ((reg_val >> 16) & 0x1));
  77. reg_val= VpuReadReg(core_idx, W4_RET_ENC_PIC_TYPE);
  78. VLOG(ERR,"[DEBUG] ret_core1_init : %d\n", (reg_val >> 16) & 0x3ff);
  79. reg_val = VpuReadReg(core_idx, W4_RET_ENC_PIC_FLAG);
  80. VLOG(ERR,"[DEBUG] ret_core0_init : %d\n", (reg_val >> 5) & 0x3ff);
  81. SetClockGate(0, 0);
  82. VLOG(ERR, "\n");
  83. VLOG(ERR, "\n");
  84. VLOG(ERR, "\n");
  85. VLOG(ERR, "\n");
  86. }
  87. static void DisplayVceEncDebugDCI(int core_idx, int vcore_idx, int set_mode, int* debug)
  88. {
  89. int reg_val;
  90. VLOG(ERR,"----------- MODE 0 : DCI DEBUG INFO----------\n");
  91. WriteRegVCE(core_idx,vcore_idx, set_mode,0 );
  92. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[3]);
  93. VLOG(ERR,"\t- i_cnt_dci_rd_tuh : 0x%x\n", ((reg_val >> 16) & 0xffff));
  94. VLOG(ERR,"\t- i_cnt_dci_wd_tuh : 0x%x\n", ((reg_val >> 0) & 0xffff));
  95. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[4]);
  96. VLOG(ERR,"\t- i_cnt_dci_rd_cu : 0x%x\n", ((reg_val >> 16) & 0xffff));
  97. VLOG(ERR,"\t- i_cnt_dci_wd_cu : 0x%x\n", ((reg_val >> 0) & 0xffff));
  98. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[5]);
  99. VLOG(ERR,"\t- i_cnt_dci_rd_ctu : 0x%x\n", ((reg_val >> 16) & 0xffff));
  100. VLOG(ERR,"\t- i_cnt_dci_2d_ctu : 0x%x\n", ((reg_val >> 0) & 0xffff));
  101. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[6]);
  102. VLOG(ERR,"\t- i_cnt_dci_rd_coef : 0x%x\n", ((reg_val >> 16) & 0xffff));
  103. VLOG(ERR,"\t- i_cnt_dci_wd_coef : 0x%x\n", ((reg_val >> 0) & 0xffff));
  104. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[7]);
  105. VLOG(ERR,"\t- i_dci_full_empty_flag : 0x%x\n", reg_val);
  106. VLOG(ERR,"----------- MODE 0 : VCE_CTRL DEBUG INFO----------\n");
  107. // HW_PARAM
  108. reg_val = ReadRegVCE(core_idx, vcore_idx, 0x0b08);
  109. VLOG(ERR,"\t- r_cnt_enable : 0x%x\n", (reg_val >> 8) & 0x1);
  110. VLOG(ERR,"\t- r_pic_done_sel : 0x%x\n", (reg_val >> 9) & 0x1);
  111. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[8]);
  112. VLOG(ERR,"\t- vce_cnt : 0x%x\n", reg_val);
  113. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[8]);
  114. VLOG(ERR,"\t- prp_cnt : 0x%x\n", reg_val);
  115. VLOG(ERR, "\n");
  116. VLOG(ERR, "\n");
  117. VLOG(ERR, "\n");
  118. VLOG(ERR, "\n");
  119. }
  120. static void DisplayVceEncDebugRDO(int core_idx, int vcore_idx, int set_mode, int* debug)
  121. {
  122. int reg_val;
  123. int reg_val_sub;
  124. VLOG(ERR,"----------- MODE 1 : RDO DEBUG INFO ----------\n");
  125. WriteRegVCE(core_idx,vcore_idx, set_mode,1 );
  126. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[3]);
  127. VLOG(ERR,"\t- o_rdo_cu_root_cb : 0x%x\n", ((reg_val >> 0) & 0x1));
  128. VLOG(ERR,"\t- o_rdo_tu_cbf_y : 0x%x\n", ((reg_val >> 1) & 0x1));
  129. VLOG(ERR,"\t- o_rdo_tu_cbf_u : 0x%x\n", ((reg_val >> 2) & 0x1));
  130. VLOG(ERR,"\t- o_rdo_tu_cbf_v : 0x%x\n", ((reg_val >> 3) & 0x1));
  131. VLOG(ERR,"\t- w_rdo_wdma_wait : 0x%x\n", ((reg_val >> 4) & 0x1));
  132. VLOG(ERR,"\t- |o_rdo_tu_sb_luma_csbf[63: 0] : 0x%x\n", ((reg_val >> 5) & 0x1));
  133. VLOG(ERR,"\t- |o_rdo_tu_sb_chro_csbf[31:16] : 0x%x\n", ((reg_val >> 6) & 0x1));
  134. VLOG(ERR,"\t- |o_rdo_tu_sb_chro_csbf[15: 0] : 0x%x\n", ((reg_val >> 7) & 0x1));
  135. VLOG(ERR,"\t- o_sub_ctu_coe_ready : 0x%x\n", ((reg_val >> 8) & 0x1));
  136. VLOG(ERR,"\t- o_sub_ctu_rec_ready : 0x%x\n", ((reg_val >> 9) & 0x1));
  137. VLOG(ERR,"\t- o_rdo_wdma_busy : 0x%x\n", ((reg_val >> 10) & 0x1));
  138. VLOG(ERR,"\t- w_rdo_rdma_wait : 0x%x\n", ((reg_val >> 11) & 0x1));
  139. VLOG(ERR,"\t- o_log2_cu_size[07:06] : 0x%x\n", ((reg_val >> 12) & 0x3));
  140. VLOG(ERR,"\t- o_log2_cu_size[15:14] : 0x%x\n", ((reg_val >> 14) & 0x3));
  141. VLOG(ERR,"\t- o_log2_cu_size[23:22] : 0x%x\n", ((reg_val >> 16) & 0x3));
  142. VLOG(ERR,"\t- o_log2_cu_size[31:30] : 0x%x\n", ((reg_val >> 18) & 0x3));
  143. VLOG(ERR,"\t- o_rdo_dbk_valid : 0x%x\n", ((reg_val >> 20) & 0x1));
  144. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[4]);
  145. VLOG(ERR,"\t- debug_status_ctrl : 0x%x\n", ((reg_val >> 0) & 0xff));
  146. reg_val_sub = (reg_val >> 0) & 0xff;
  147. VLOG(ERR,"\t- debug_status_ctrl.fsm_main_cur : 0x%x\n", ((reg_val_sub >> 0) & 0x7));
  148. VLOG(ERR,"\t- debug_status_ctrl.i_rdo_wdma_wait : 0x%x\n", ((reg_val_sub >> 3) & 0x1));
  149. VLOG(ERR,"\t- debug_status_ctrl.fsm_cu08_cur : 0x%x\n", ((reg_val_sub >> 4) & 0x7));
  150. VLOG(ERR,"\t- debug_status_ctrl.init_hold : 0x%x\n", ((reg_val_sub >> 7) & 0x1));
  151. VLOG(ERR,"\t- debug_status_nb : 0x%x\n", ((reg_val >> 8) & 0xff));
  152. reg_val_sub =(reg_val >> 8) & 0xff;
  153. VLOG(ERR,"\t- debug_status_nb.fsm_save_cur : 0x%x\n", ((reg_val_sub >> 0) & 0x7));
  154. VLOG(ERR,"\t- debug_status_nb.fsm_load_cur : 0x%x\n", ((reg_val_sub >> 4) & 0x7));
  155. VLOG(ERR,"\t- debug_status_rec : 0x%x\n", ((reg_val >> 16) & 0xf));
  156. reg_val_sub = (reg_val >> 16) & 0xf;
  157. VLOG(ERR,"\t- debug_status_rec.fsm_obuf_cur : 0x%x\n", ((reg_val_sub >> 0) & 0x7));
  158. VLOG(ERR,"\t- debug_status_coe : 0x%x\n", ((reg_val >> 20) & 0xf));
  159. reg_val_sub = (reg_val >> 20) & 0xf;
  160. VLOG(ERR,"\t- debug_status_coe.fsm_obuf_cur : 0x%x\n", ((reg_val_sub >> 0) & 0x7));
  161. VLOG(ERR,"\t- debug_status_para : 0x%x\n", ((reg_val >> 24) & 0xff));
  162. reg_val_sub = (reg_val >> 24) & 0xff;
  163. VLOG(ERR,"\t- debug_status_para.cur_sfu_rd_state : 0x%x\n", ((reg_val_sub >> 0) & 0xf));
  164. VLOG(ERR,"\t- debug_status_para.cur_para_state : 0x%x\n", ((reg_val_sub >> 4) & 0xf));
  165. VLOG(ERR, "\n");
  166. VLOG(ERR, "\n");
  167. VLOG(ERR, "\n");
  168. VLOG(ERR, "\n");
  169. }
  170. static void DisplayVceEncDebugLF(int core_idx, int vcore_idx, int set_mode, int* debug)
  171. {
  172. int reg_val;
  173. VLOG(ERR,"----------- MODE 2 : LF DEBUG INFO----------\n");
  174. WriteRegVCE(core_idx,vcore_idx, set_mode,2 );
  175. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[3]);
  176. VLOG(ERR,"\t- cur_enc_main_state : 0x%x \n", (reg_val>>27)&0x1F);
  177. VLOG(ERR,"\t- i_sao_para_valie : 0x%x \n", (reg_val>>26)&0x1);
  178. VLOG(ERR,"\t- i_sao_fetch_done : 0x%x \n", (reg_val>>25)&0x1);
  179. VLOG(ERR,"\t- i_global_encode_en : 0x%x \n", (reg_val>>24)&0x1);
  180. VLOG(ERR,"\t- i_bs_valid : 0x%x \n", (reg_val>>23)&0x1);
  181. VLOG(ERR,"\t- i_rec_buf_rdo_ready : 0x%x \n", (reg_val>>22)&0x1);
  182. VLOG(ERR,"\t- o_rec_buf_dbk_hold : 0x%x \n", (reg_val>>21)&0x1);
  183. VLOG(ERR,"\t- cur_main_state : 0x%x \n", (reg_val>>16)&0x1F);
  184. VLOG(ERR,"\t- r_lf_pic_dbk_disable : 0x%x \n", (reg_val>>15)&0x1);
  185. VLOG(ERR,"\t- r_lf_pic_sao_disable : 0x%x \n", (reg_val>>14)&0x1);
  186. VLOG(ERR,"\t- para_load_done : 0x%x \n", (reg_val>>13)&0x1);
  187. VLOG(ERR,"\t- i_rdma_ack_wait : 0x%x \n", (reg_val>>12)&0x1);
  188. VLOG(ERR,"\t- i_sao_intl_col_done : 0x%x \n", (reg_val>>11)&0x1);
  189. VLOG(ERR,"\t- i_sao_outbuf_full : 0x%x \n", (reg_val>>10)&0x1);
  190. VLOG(ERR,"\t- lf_sub_done : 0x%x \n", (reg_val>>9)&0x1);
  191. VLOG(ERR,"\t- i_wdma_ack_wait : 0x%x \n", (reg_val>>8)&0x1);
  192. VLOG(ERR,"\t- lf_all_sub_done : 0x%x \n", (reg_val>>6)&0x1);
  193. VLOG(ERR,"\t- cur_ycbcr : 0x%x \n", (reg_val>>5)&0x3);
  194. VLOG(ERR,"\t- sub8x8_done : 0x%x \n", (reg_val>>0)&0xF);
  195. VLOG(ERR,"----------- MODE 2 : SYNC_Y_POS DEBUG INFO----------\n");
  196. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[4]);
  197. VLOG(ERR,"\t- fbc_y_pos : 0x%x \n", (reg_val>>0)&0xff);
  198. VLOG(ERR,"\t- bwb_y_pos : 0x%x \n", (reg_val>>16)&0xff);
  199. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[5]);
  200. VLOG(ERR,"\t- trace_frame : 0x%x\n", ((reg_val >> 0) & 0xffff));
  201. VLOG(ERR, "\n");
  202. VLOG(ERR, "\n");
  203. VLOG(ERR, "\n");
  204. VLOG(ERR, "\n");
  205. }
  206. static void DisplayVceEncDebugSFU(int core_idx, int vcore_idx, int set_mode, int* debug)
  207. {
  208. int reg_val;
  209. VLOG(ERR,"----------- MODE 3 : SFU DEBUG INFO----------\n");
  210. WriteRegVCE(core_idx,vcore_idx, set_mode,3 );
  211. reg_val = ReadRegVCE(0, vcore_idx, debug[3]);
  212. VLOG(ERR,"\t- i_sub_ctu_pos_y : 0x%x \n", (reg_val>>0)&0xff);
  213. VLOG(ERR,"\t- i_sub_ctu_pos_x : 0x%x \n", (reg_val>>8)&0xff);
  214. VLOG(ERR,"\t- i_cu_fifo_wvalid : 0x%x \n", (reg_val>>16)&0x1);
  215. VLOG(ERR,"\t- i_ctu_busy : 0x%x \n", (reg_val>>20)&0x1);
  216. VLOG(ERR,"\t- i_cs_sctu : 0x%x \n", (reg_val>>24)&0x7);
  217. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[4]);
  218. VLOG(ERR,"\t- i_ctu_pos_y : 0x%x \n", (reg_val>>0)&0xff);
  219. VLOG(ERR,"\t- i_ctu_pos_x : 0x%x \n", (reg_val>>8)&0xff);
  220. VLOG(ERR,"\t- i_sao_rdo_valid : 0x%x \n", (reg_val>>16)&0x1);
  221. VLOG(ERR,"\t- i_sao_en_r : 0x%x \n", (reg_val>>20)&0x1);
  222. VLOG(ERR,"\t- i_ctu_fifo_wvalid : 0x%x \n", (reg_val>>24)&0x1);
  223. VLOG(ERR,"\t- cs_sfu_ctu : 0x%x \n", (reg_val>>28)&0x3);
  224. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[5]);
  225. VLOG(ERR,"\t- i_cu_fifo_wvalid : 0x%x \n", (reg_val>>0)&0x1);
  226. VLOG(ERR,"\t- i_rdo_cu_rd_valid : 0x%x \n", (reg_val>>4)&0x1);
  227. VLOG(ERR,"\t- i_cu_size_r : 0x%x \n", (reg_val>>8)&0x3);
  228. VLOG(ERR,"\t- i_cu_idx_r : 0x%x \n", (reg_val>>12)&0xf);
  229. VLOG(ERR,"\t- cs_cu : 0x%x \n", (reg_val>>16)&0x7);
  230. VLOG(ERR,"\t- cs_fifo : 0x%x \n", (reg_val>>20)&0x7);
  231. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[6]);
  232. VLOG(ERR,"\t- w_dbg_tu_fifo_fsm : 0x%x \n", (reg_val>>0)&0xff);
  233. VLOG(ERR,"\t- i_coff_fifo_wvalid : 0x%x \n", (reg_val>>8)&0x1);
  234. VLOG(ERR,"\t- i_tuh_fifo_wvalid : 0x%x \n", (reg_val>>12)&0x1);
  235. VLOG(ERR,"\t- w_dbg_tu_ctrl_fsm : 0x%x \n", (reg_val>>16)&0xf);
  236. VLOG(ERR,"\t- i_rdo_tc_ready : 0x%x \n", (reg_val>>20)&0x1);
  237. VLOG(ERR,"\t- w_dbg_coef_st_in_pic : 0x%x \n", (reg_val>>24)&0x7);
  238. VLOG(ERR,"\t- i_rdo_tu_rd-valid : 0x%x \n", (reg_val>>28)&0x1);
  239. VLOG(ERR, "\n");
  240. VLOG(ERR, "\n");
  241. VLOG(ERR, "\n");
  242. VLOG(ERR, "\n");
  243. }
  244. static void DisplayVceEncDebugDCI2(int core_idx, int vcore_idx, int set_mode, int* debug)
  245. {
  246. int reg_val;
  247. VLOG(ERR,"----------- MODE 4 : DCI2 DEBUG INFO----------\n");
  248. WriteRegVCE(core_idx,vcore_idx, set_mode,4 );
  249. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[3]);
  250. VLOG(ERR,"\t- i_cnt_dci_rd_tuh2 : 0x%x \n", (reg_val>>16)&0xffff);
  251. VLOG(ERR,"\t- i_cnt_dci_wd_tuh2 : 0x%x \n", (reg_val>> 0)&0xffff);
  252. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[4]);
  253. VLOG(ERR,"\t- i_cnt_dci_rd_cu2 : 0x%x \n", (reg_val>>16)&0xffff);
  254. VLOG(ERR,"\t- i_cnt_dci_wd_cu2 : 0x%x \n", (reg_val>> 0)&0xffff);
  255. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[5]);
  256. VLOG(ERR,"\t- i_cnt_dci_rd_ctu2 : 0x%x \n", (reg_val>>16)&0xffff);
  257. VLOG(ERR,"\t- i_cnt_dci_wd_ctu2 : 0x%x \n", (reg_val>> 0)&0xffff);
  258. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[6]);
  259. VLOG(ERR,"\t- i_cnt_dci_rd_coef2 : 0x%x \n", (reg_val>>16)&0xffff);
  260. VLOG(ERR,"\t- i_cnt_dci_wd_coef2 : 0x%x \n", (reg_val>> 0)&0xffff);
  261. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[7]);
  262. VLOG(ERR,"\t- i_dci_full_empty_flag : 0x%x \n", reg_val);
  263. VLOG(ERR, "\n");
  264. VLOG(ERR, "\n");
  265. VLOG(ERR, "\n");
  266. VLOG(ERR, "\n");
  267. }
  268. static void DisplayVceEncDebugDCILast(int core_idx, int vcore_idx, int set_mode, int* debug)
  269. {
  270. int reg_val;
  271. VLOG(ERR,"----------- MODE 5 : DCI LAST DEBUG INFO----------\n");
  272. WriteRegVCE(core_idx,vcore_idx, set_mode,5 );
  273. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[3]);
  274. VLOG(ERR,"\t- i_cnt_dci_last_rdata[143:112] : 0x%x \n", reg_val);
  275. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[4]);
  276. VLOG(ERR,"\t- i_cnt_dci_last_rdata[111: 96] : 0x%x \n", reg_val & 0xffff);
  277. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[5]);
  278. VLOG(ERR,"\t- i_cnt_dci_last_rdata[ 95: 64] : 0x%x \n", reg_val);
  279. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[6]);
  280. VLOG(ERR,"\t- i_cnt_dci_last_rdata[ 63: 32] : 0x%x \n", reg_val);
  281. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[7]);
  282. VLOG(ERR,"\t- i_cnt_dci_last_rdata[ 31: 0] : 0x%x \n", reg_val);
  283. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[8]);
  284. VLOG(ERR,"\t- i_wr_read_point : 0x%x \n", (reg_val >> 16) & 0x7ff );
  285. VLOG(ERR,"\t- i_wr_read_point_limit : 0x%x \n", (reg_val >> 0) & 0x7ff );
  286. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[9]);
  287. VLOG(ERR,"\t- i_sbuf_raddr_store : 0x%x \n", (reg_val >> 0) & 0x3f );
  288. VLOG(ERR,"\t- i_read_point : 0x%x \n", (reg_val >> 8) & 0x1f );
  289. VLOG(ERR,"\t- i_dci_write_addr_b : 0x%x \n", (reg_val >> 16) & 0x3f );
  290. VLOG(ERR,"\t- i_dci_write_addr_c : 0x%x \n", (reg_val >> 24) & 0x1f );
  291. VLOG(ERR, "\n");
  292. VLOG(ERR, "\n");
  293. VLOG(ERR, "\n");
  294. VLOG(ERR, "\n");
  295. }
  296. static void DisplayVceEncDebugBigBufferCnt(int core_idx, int vcore_idx, int set_mode, int* debug)
  297. {
  298. int reg_val;
  299. VLOG(ERR,"----------- MODE 6 : BIG BUFFER CNT DEBUG INFO----------\n");
  300. WriteRegVCE(core_idx,vcore_idx, set_mode,6 );
  301. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[3]);
  302. VLOG(ERR,"\t- i_cnt_bbuf_read_tuh : 0x%x \n", (reg_val >> 16) & 0xffff);
  303. VLOG(ERR,"\t- i_cnt_bbuf_write_tuh : 0x%x \n", (reg_val >> 0) & 0xffff);
  304. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[4]);
  305. VLOG(ERR,"\t- i_cnt_bbuf_read_cu : 0x%x \n", (reg_val >> 16) & 0xffff);
  306. VLOG(ERR,"\t- i_cnt_bbuf_write_cu : 0x%x \n", (reg_val >> 0) & 0xffff);
  307. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[5]);
  308. VLOG(ERR,"\t- i_cnt_bbuf_read_coef : 0x%x \n", (reg_val >> 16) & 0xffff);
  309. VLOG(ERR,"\t- i_cnt_bbuf_write_coef : 0x%x \n", (reg_val >> 0) & 0xffff);
  310. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[6]);
  311. VLOG(ERR,"\t- i_cnt_sbuf_read_tuh : 0x%x \n", (reg_val >> 16) & 0xffff);
  312. VLOG(ERR,"\t- i_cnt_sbuf_write_tuh : 0x%x \n", (reg_val >> 0) & 0xffff);
  313. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[7]);
  314. VLOG(ERR,"\t- i_cnt_sbuf_read_cu : 0x%x \n", (reg_val >> 16) & 0xffff);
  315. VLOG(ERR,"\t- i_cnt_sbuf_write_cu : 0x%x \n", (reg_val >> 0) & 0xffff);
  316. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[8]);
  317. VLOG(ERR,"\t- i_cnt_sbuf_read_ctu : 0x%x \n", (reg_val >> 16) & 0xffff);
  318. VLOG(ERR,"\t- i_cnt_sbuf_write_tcu : 0x%x \n", (reg_val >> 0) & 0xffff);
  319. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[9]);
  320. VLOG(ERR,"\t- i_cnt_sbuf_read_coef : 0x%x \n", (reg_val >> 16) & 0xffff);
  321. VLOG(ERR,"\t- i_cnt_sbuf_write_coef : 0x%x \n", (reg_val >> 0) & 0xffff);
  322. VLOG(ERR, "\n");
  323. VLOG(ERR, "\n");
  324. VLOG(ERR, "\n");
  325. VLOG(ERR, "\n");
  326. }
  327. static void DisplayVceEncDebugBigBufferAddr(int core_idx, int vcore_idx, int set_mode, int* debug)
  328. {
  329. int reg_val;
  330. VLOG(ERR,"----------- MODE 6 : BIG BUFFER ADDR DEBUG INFO----------\n");
  331. WriteRegVCE(core_idx,vcore_idx, set_mode,7 );
  332. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[3]);
  333. VLOG(ERR,"\t- i_cnt_bbuf_raddr_read_tuh : 0x%x \n", (reg_val >> 16) & 0x7ff);
  334. VLOG(ERR,"\t- i_cnt_bbuf_raddr_write_tuh : 0x%x \n", (reg_val >> 0) & 0x7ff);
  335. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[4]);
  336. VLOG(ERR,"\t- i_cnt_bbuf_raddr_read_cu : 0x%x \n", (reg_val >> 16) & 0x1ff);
  337. VLOG(ERR,"\t- i_cnt_bbuf_raddr_write_cu : 0x%x \n", (reg_val >> 0) & 0x1ff);
  338. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[5]);
  339. VLOG(ERR,"\t- i_cnt_bbuf_raddr_read_coef : 0x%x \n", (reg_val >> 16) & 0xfff);
  340. VLOG(ERR,"\t- i_cnt_bbuf_raddr_write_coef : 0x%x \n", (reg_val >> 0) & 0xfff);
  341. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[6]);
  342. VLOG(ERR,"\t- i_cnt_sbuf_raddr_read_tuh : 0x%x \n", (reg_val >> 16) & 0x1f);
  343. VLOG(ERR,"\t- i_cnt_sbuf_raddr_write_tuh : 0x%x \n", (reg_val >> 0) & 0x1f);
  344. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[7]);
  345. VLOG(ERR,"\t- i_cnt_sbuf_raddr_read_cu : 0x%x \n", (reg_val >> 16) & 0x1f);
  346. VLOG(ERR,"\t- i_cnt_sbuf_raddr_write_cu : 0x%x \n", (reg_val >> 0) & 0x1f);
  347. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[8]);
  348. VLOG(ERR,"\t- i_cnt_sbuf_raddr_read_ctu : 0x%x \n", (reg_val >> 16) & 0x1f);
  349. VLOG(ERR,"\t- i_cnt_sbuf_raddr_write_tcu : 0x%x \n", (reg_val >> 0) & 0x1f);
  350. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[9]);
  351. VLOG(ERR,"\t- i_cnt_sbuf_raddr_read_coef : 0x%x \n", (reg_val >> 16) & 0x1f);
  352. VLOG(ERR,"\t- i_cnt_sbuf_raddr_write_coef : 0x%x \n", (reg_val >> 0) & 0x1f);
  353. VLOG(ERR, "\n");
  354. VLOG(ERR, "\n");
  355. VLOG(ERR, "\n");
  356. VLOG(ERR, "\n");
  357. }
  358. static void DisplayVceEncDebugSubWb(int core_idx, int vcore_idx, int set_mode, int* debug)
  359. {
  360. int reg_val;
  361. VLOG(ERR,"----------- MODE 7 : SUB_WB DEBUG INFO----------\n");
  362. WriteRegVCE(core_idx,vcore_idx, set_mode,8 );
  363. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[3]);
  364. VLOG(ERR,"\t- subwb_debug_0 : 0x%x \n", reg_val);
  365. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[4]);
  366. VLOG(ERR,"\t- subwb_debug_1 : 0x%x \n", reg_val);
  367. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[5]);
  368. VLOG(ERR,"\t- subwb_debug_2 : 0x%x \n", reg_val);
  369. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[6]);
  370. VLOG(ERR,"\t- subwb_debug_3 : 0x%x \n", reg_val);
  371. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[7]);
  372. VLOG(ERR,"\t- subwb_debug_4 : 0x%x \n", reg_val);
  373. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[8]);
  374. VLOG(ERR,"\t- int_sync_ypos : 0x%x \n", reg_val);
  375. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[9]);
  376. VLOG(ERR,"\t- pic_run_cnt : 0x%x \n", ((reg_val) >> 0) & 0xffff);
  377. VLOG(ERR,"\t- pic_init_ct : 0x%x \n", ((reg_val) >> 16) & 0xffff);
  378. VLOG(ERR, "\n");
  379. VLOG(ERR, "\n");
  380. VLOG(ERR, "\n");
  381. VLOG(ERR, "\n");
  382. }
  383. static void DisplayVceEncDebugFBC(int core_idx, int vcore_idx, int set_mode, int* debug)
  384. {
  385. int reg_val;
  386. VLOG(ERR,"----------- MODE 8 : FBC DEBUG INFO----------\n");
  387. WriteRegVCE(core_idx,vcore_idx, set_mode,9 );
  388. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[3]);
  389. VLOG(ERR,"\t- ofs_request_count : 0x%x \n", reg_val);
  390. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[4]);
  391. VLOG(ERR,"\t- ofs_bvalid_count : 0x%x \n", reg_val);
  392. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[5]);
  393. VLOG(ERR,"\t- dat_request_count : 0x%x \n", reg_val);
  394. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[6]);
  395. VLOG(ERR,"\t- dat_bvalid_count : 0x%x \n", reg_val);
  396. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[7]);
  397. VLOG(ERR,"\t- fbc_debug : 0x%x \n", ((reg_val) >> 0) & 0x3FFFFFFF);
  398. VLOG(ERR,"\t- fbc_cr_idle_3d : 0x%x \n", ((reg_val) >> 30) & 0x1);
  399. VLOG(ERR,"\t- fbc_cr_busy_3d : 0x%x \n", ((reg_val) >> 31) & 0x1);
  400. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[8]);
  401. VLOG(ERR,"\t- outbuf_debug : 0x%x \n", reg_val);
  402. reg_val = ReadRegVCE(core_idx, vcore_idx, debug[9]);
  403. VLOG(ERR,"\t- fbcif_debug : 0x%x \n", reg_val);
  404. VLOG(ERR, "\n");
  405. VLOG(ERR, "\n");
  406. VLOG(ERR, "\n");
  407. VLOG(ERR, "\n");
  408. }
  409. #define VCORE_DBG_ADDR(__vCoreIdx) 0x8000+(0x1000*__vCoreIdx) + 0x300
  410. #define VCORE_DBG_DATA(__vCoreIdx) 0x8000+(0x1000*__vCoreIdx) + 0x304
  411. #define VCORE_DBG_READY(__vCoreIdx) 0x8000+(0x1000*__vCoreIdx) + 0x308
  412. Uint32 ReadRegVCE(
  413. Uint32 core_idx,
  414. Uint32 vce_core_idx,
  415. Uint32 vce_addr
  416. )
  417. {
  418. int vcpu_reg_addr;
  419. int udata;
  420. int vce_core_base = 0x8000 + 0x1000*vce_core_idx;
  421. SetClockGate(core_idx, 1);
  422. vdi_fio_write_register(core_idx, VCORE_DBG_READY(vce_core_idx), 0);
  423. vcpu_reg_addr = vce_addr >> 2;
  424. vdi_fio_write_register(core_idx, VCORE_DBG_ADDR(vce_core_idx),vcpu_reg_addr + vce_core_base);
  425. if (vdi_fio_read_register(0, VCORE_DBG_READY(vce_core_idx)) == 1)
  426. udata= vdi_fio_read_register(0, VCORE_DBG_DATA(vce_core_idx));
  427. else {
  428. VLOG(ERR, "failed to read VCE register: %d, 0x%04x\n", vce_core_idx, vce_addr);
  429. udata = -2;//-1 can be a valid value
  430. }
  431. SetClockGate(core_idx, 0);
  432. return udata;
  433. }
  434. void WriteRegVCE(
  435. Uint32 core_idx,
  436. Uint32 vce_core_idx,
  437. Uint32 vce_addr,
  438. Uint32 udata
  439. )
  440. {
  441. int vcpu_reg_addr;
  442. SetClockGate(core_idx, 1);
  443. vdi_fio_write_register(core_idx, VCORE_DBG_READY(vce_core_idx),0);
  444. vcpu_reg_addr = vce_addr >> 2;
  445. vdi_fio_write_register(core_idx, VCORE_DBG_DATA(vce_core_idx),udata);
  446. vdi_fio_write_register(core_idx, VCORE_DBG_ADDR(vce_core_idx),(vcpu_reg_addr) & 0x00007FFF);
  447. if (vdi_fio_read_register(0, VCORE_DBG_READY(vce_core_idx)) < 0)
  448. VLOG(ERR, "failed to write VCE register: 0x%04x\n", vce_addr);
  449. SetClockGate(core_idx, 0);
  450. }
  451. void PrintVpuStatus(
  452. Uint32 coreIdx,
  453. Uint32 productId
  454. )
  455. {
  456. SetClockGate(coreIdx, 1);
  457. if (PRODUCT_ID_W_SERIES(productId))
  458. {
  459. int rd, wr;
  460. Uint32 tq, ip, mc, lf;
  461. Uint32 avail_cu, avail_tu, avail_tc, avail_lf, avail_ip;
  462. Uint32 ctu_fsm, nb_fsm, cabac_fsm, cu_info, mvp_fsm, tc_busy, lf_fsm, bs_data, bbusy, fv;
  463. Uint32 reg_val;
  464. Uint32 index;
  465. Uint32 vcpu_reg[31]= {0,};
  466. VLOG(ERR,"-------------------------------------------------------------------------------\n");
  467. VLOG(ERR,"------ VCPU STATUS(DEC) -----\n");
  468. VLOG(ERR,"-------------------------------------------------------------------------------\n");
  469. rd = VpuReadReg(coreIdx, W4_BS_RD_PTR);
  470. wr = VpuReadReg(coreIdx, W4_BS_WR_PTR);
  471. VLOG(ERR,"RD_PTR: 0x%08x WR_PTR: 0x%08x BS_OPT: 0x%08x BS_PARAM: 0x%08x\n",
  472. rd, wr, VpuReadReg(coreIdx, W4_BS_OPTION), VpuReadReg(coreIdx, W4_BS_PARAM));
  473. // --------- VCPU register Dump
  474. VLOG(ERR,"[+] VCPU REG Dump\n");
  475. for (index = 0; index < 25; index++) {
  476. VpuWriteReg (coreIdx, 0x14, (1<<9) | (index & 0xff));
  477. vcpu_reg[index] = VpuReadReg (coreIdx, 0x1c);
  478. if (index < 16) {
  479. VLOG(ERR,"0x%08x\t", vcpu_reg[index]);
  480. if ((index % 4) == 3) VLOG(ERR,"\n");
  481. }
  482. else {
  483. switch (index) {
  484. case 16: VLOG(ERR,"CR0: 0x%08x\t", vcpu_reg[index]); break;
  485. case 17: VLOG(ERR,"CR1: 0x%08x\n", vcpu_reg[index]); break;
  486. case 18: VLOG(ERR,"ML: 0x%08x\t", vcpu_reg[index]); break;
  487. case 19: VLOG(ERR,"MH: 0x%08x\n", vcpu_reg[index]); break;
  488. case 21: VLOG(ERR,"LR: 0x%08x\n", vcpu_reg[index]); break;
  489. case 22: VLOG(ERR,"PC: 0x%08x\n", vcpu_reg[index]);break;
  490. case 23: VLOG(ERR,"SR: 0x%08x\n", vcpu_reg[index]);break;
  491. case 24: VLOG(ERR,"SSP: 0x%08x\n", vcpu_reg[index]);break;
  492. }
  493. }
  494. }
  495. VLOG(ERR,"[-] VCPU REG Dump\n");
  496. // --------- BIT register Dump
  497. VLOG(ERR,"[+] BPU REG Dump\n");
  498. for (index=0;index < 30; index++)
  499. {
  500. int temp;
  501. temp = vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x18));
  502. VLOG(ERR,"BITPC = 0x%08x\n", temp);
  503. if ( temp == 0xffffffff)
  504. return;
  505. }
  506. VLOG(ERR,"BIT START=0x%08x, BIT END=0x%08x\n", vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x11c)),
  507. vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x120)) );
  508. if (productId == PRODUCT_ID_410 )
  509. VLOG(ERR,"BIT COMMAND 0x%x\n", vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x100)));
  510. if (productId == PRODUCT_ID_4102 || productId == PRODUCT_ID_510)
  511. VLOG(ERR,"BIT COMMAND 0x%x\n", vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x1FC)));
  512. //DECODER SDMA INFO
  513. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x120);
  514. while((vdi_fio_read_register(0,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  515. reg_val = vdi_fio_read_register(0,(W4_REG_BASE + 0x8000 + 0x78));
  516. VLOG(ERR,"C_SDMA_LOAD_CMD = 0x%x\n",reg_val);
  517. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x121);
  518. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  519. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  520. VLOG(ERR,"C_SDMA_AURO_MODE = 0x%x\n",reg_val);
  521. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x122);
  522. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  523. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  524. VLOG(ERR,"C_SDMA_BASE_ADDR = 0x%x\n",reg_val);
  525. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x123);
  526. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  527. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  528. VLOG(ERR,"C_SDMA_ENC_ADDR = 0x%x\n",reg_val);
  529. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x124);
  530. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  531. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  532. VLOG(ERR,"C_SDMA_ENDIAN = 0x%x\n",reg_val);
  533. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x125);
  534. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  535. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  536. VLOG(ERR,"C_SDMA_IRQ_CLEAR = 0x%x\n",reg_val);
  537. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x126);
  538. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  539. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  540. VLOG(ERR,"C_SDMA_BUSY = 0x%x\n",reg_val);
  541. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x127);
  542. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  543. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  544. VLOG(ERR,"C_SDMA_LAST_ADDR = 0x%x\n",reg_val);
  545. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x128);
  546. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  547. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  548. VLOG(ERR,"C_SDMA_SC_BASE_ADDR = 0x%x\n",reg_val);
  549. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x129);
  550. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  551. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  552. VLOG(ERR,"C_SDMA_RD_SEL = 0x%x\n",reg_val);
  553. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x130);
  554. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  555. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  556. VLOG(ERR,"C_SDMA_WR_SEL = 0x%x\n",reg_val);
  557. //DECODER SHU INFO
  558. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x140);
  559. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  560. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  561. VLOG(ERR,"C_SHU_INIT = 0x%x\n",reg_val);
  562. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x141);
  563. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  564. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  565. VLOG(ERR,"C_SHU_SEEK_NXT_NAL = 0x%x\n",reg_val);
  566. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x142);
  567. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  568. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  569. VLOG(ERR,"C_SHU_RD_NAL_ADDR = 0x%x\n",reg_val);
  570. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x143);
  571. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  572. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  573. VLOG(ERR,"C_SHU_STATUS = 0x%x\n",reg_val);
  574. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x144);
  575. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  576. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  577. VLOG(ERR,"C_SHU_GBYTE0 = 0x%x\n",reg_val);
  578. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x145);
  579. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  580. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  581. VLOG(ERR,"C_SHU_GBYTE1 = 0x%x\n",reg_val);
  582. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x146);
  583. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  584. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  585. VLOG(ERR,"C_SHU_GBYTE2 = 0x%x\n",reg_val);
  586. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x147);
  587. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  588. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  589. VLOG(ERR,"C_SHU_GBYTE3 = 0x%x\n",reg_val);
  590. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x148);
  591. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  592. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  593. VLOG(ERR,"C_SHU_GBYTE4 = 0x%x\n",reg_val);
  594. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x14C);
  595. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  596. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  597. VLOG(ERR,"C_SHU_SBYTE_LOW = 0x%x\n",reg_val);
  598. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x14D);
  599. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  600. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  601. VLOG(ERR,"C_SHU_SBYTE_HIGH = 0x%x\n",reg_val);
  602. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x14E);
  603. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  604. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  605. VLOG(ERR,"C_SHU_ST_PAT_DIS = 0x%x\n",reg_val);
  606. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x150);
  607. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  608. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  609. VLOG(ERR,"C_SHU_NBUF0 = 0x%x\n",reg_val);
  610. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x151);
  611. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  612. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  613. VLOG(ERR,"C_SHU_NBUF1 = 0x%x\n",reg_val);
  614. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x152);
  615. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  616. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  617. VLOG(ERR,"C_SHU_NBUF2 = 0x%x\n",reg_val);
  618. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x153);
  619. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  620. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  621. VLOG(ERR,"C_SHU_NBUF3 = 0x%x\n",reg_val);
  622. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x15C);
  623. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  624. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  625. VLOG(ERR,"C_SHU_NBUF_RPTR = 0x%x\n",reg_val);
  626. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x15D);
  627. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  628. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  629. VLOG(ERR,"C_SHU_NBUF_WPTR = 0x%x\n",reg_val);
  630. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x15E);
  631. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  632. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  633. VLOG(ERR,"C_SHU_REMAIN_BYTE = 0x%x\n",reg_val);
  634. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x15F);
  635. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  636. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  637. VLOG(ERR,"C_SHU_CONSUME_BYTE= 0x%x\n",reg_val);
  638. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x160);
  639. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  640. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  641. VLOG(ERR,"C_SHU_RD_SEL = 0x%x\n",reg_val);
  642. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x161);
  643. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  644. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  645. VLOG(ERR,"C_SHU_WR_SEL = 0x%x\n",reg_val);
  646. // --------- BIT HEVC Status Dump
  647. ctu_fsm = vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x48));
  648. nb_fsm = vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x4c));
  649. cabac_fsm = vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x50));
  650. cu_info = vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x54));
  651. mvp_fsm = vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x58));
  652. tc_busy = vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x5c));
  653. lf_fsm = vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x60));
  654. bs_data = vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x64));
  655. bbusy = vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x68));
  656. fv = vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x6C));
  657. VLOG(ERR,"[DEBUG-BPUHEVC] CTU_X: %4d, CTU_Y: %4d\n", vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x40)), vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x44)));
  658. VLOG(ERR,"[DEBUG-BPUHEVC] CTU_FSM> Main: 0x%02x, FIFO: 0x%1x, NB: 0x%02x, DBK: 0x%1x\n", ((ctu_fsm >> 24) & 0xff), ((ctu_fsm >> 16) & 0xff), ((ctu_fsm >> 8) & 0xff), (ctu_fsm & 0xff));
  659. VLOG(ERR,"[DEBUG-BPUHEVC] NB_FSM: 0x%02x\n", nb_fsm & 0xff);
  660. VLOG(ERR,"[DEBUG-BPUHEVC] CABAC_FSM> SAO: 0x%02x, CU: 0x%02x, PU: 0x%02x, TU: 0x%02x, EOS: 0x%02x\n", ((cabac_fsm>>25) & 0x3f), ((cabac_fsm>>19) & 0x3f), ((cabac_fsm>>13) & 0x3f), ((cabac_fsm>>6) & 0x7f), (cabac_fsm & 0x3f));
  661. VLOG(ERR,"[DEBUG-BPUHEVC] CU_INFO value = 0x%04x \n\t\t(l2cb: 0x%1x, cux: %1d, cuy; %1d, pred: %1d, pcm: %1d, wr_done: %1d, par_done: %1d, nbw_done: %1d, dec_run: %1d)\n", cu_info,
  662. ((cu_info>> 16) & 0x3), ((cu_info>> 13) & 0x7), ((cu_info>> 10) & 0x7), ((cu_info>> 9) & 0x3), ((cu_info>> 8) & 0x1), ((cu_info>> 6) & 0x3), ((cu_info>> 4) & 0x3), ((cu_info>> 2) & 0x3), (cu_info & 0x3));
  663. VLOG(ERR,"[DEBUG-BPUHEVC] MVP_FSM> 0x%02x\n", mvp_fsm & 0xf);
  664. VLOG(ERR,"[DEBUG-BPUHEVC] TC_BUSY> tc_dec_busy: %1d, tc_fifo_busy: 0x%02x\n", ((tc_busy >> 3) & 0x1), (tc_busy & 0x7));
  665. VLOG(ERR,"[DEBUG-BPUHEVC] LF_FSM> SAO: 0x%1x, LF: 0x%1x\n", ((lf_fsm >> 4) & 0xf), (lf_fsm & 0xf));
  666. VLOG(ERR,"[DEBUG-BPUHEVC] BS_DATA> ExpEnd=%1d, bs_valid: 0x%03x, bs_data: 0x%03x\n", ((bs_data >> 31) & 0x1), ((bs_data >> 16) & 0xfff), (bs_data & 0xfff));
  667. VLOG(ERR,"[DEBUG-BPUHEVC] BUS_BUSY> mib_wreq_done: %1d, mib_busy: %1d, sdma_bus: %1d\n", ((bbusy >> 2) & 0x1), ((bbusy >> 1) & 0x1) , (bbusy & 0x1));
  668. VLOG(ERR,"[DEBUG-BPUHEVC] FIFO_VALID> cu: %1d, tu: %1d, iptu: %1d, lf: %1d, coff: %1d\n\n", ((fv >> 4) & 0x1), ((fv >> 3) & 0x1), ((fv >> 2) & 0x1), ((fv >> 1) & 0x1), (fv & 0x1));
  669. VLOG(ERR,"[-] BPU REG Dump\n");
  670. // --------- VCE register Dump
  671. VLOG(ERR,"[+] VCE REG Dump\n");
  672. tq = ReadRegVCE(coreIdx, 0, 0xd0);
  673. ip = ReadRegVCE(coreIdx, 0, 0xd4);
  674. mc = ReadRegVCE(coreIdx, 0, 0xd8);
  675. lf = ReadRegVCE(coreIdx, 0, 0xdc);
  676. avail_cu = (ReadRegVCE(coreIdx, 0, 0x11C)>>16) - (ReadRegVCE(coreIdx, 0, 0x110)>>16);
  677. avail_tu = (ReadRegVCE(coreIdx, 0, 0x11C)&0xFFFF) - (ReadRegVCE(coreIdx, 0, 0x110)&0xFFFF);
  678. avail_tc = (ReadRegVCE(coreIdx, 0, 0x120)>>16) - (ReadRegVCE(coreIdx, 0, 0x114)>>16);
  679. avail_lf = (ReadRegVCE(coreIdx, 0, 0x120)&0xFFFF) - (ReadRegVCE(coreIdx, 0, 0x114)&0xFFFF);
  680. avail_ip = (ReadRegVCE(coreIdx, 0, 0x124)>>16) - (ReadRegVCE(coreIdx, 0, 0x118)>>16);
  681. VLOG(ERR," TQ IP MC LF GDI_EMPTY ROOM \n");
  682. VLOG(ERR,"------------------------------------------------------------------------------------------------------------\n");
  683. SetClockGate(coreIdx, 1);
  684. VLOG(ERR,"| %d %04d %04d | %d %04d %04d | %d %04d %04d | %d %04d %04d | 0x%08x | CU(%d) TU(%d) TC(%d) LF(%d) IP(%d)\n",
  685. (tq>>22)&0x07, (tq>>11)&0x3ff, tq&0x3ff,
  686. (ip>>22)&0x07, (ip>>11)&0x3ff, ip&0x3ff,
  687. (mc>>22)&0x07, (mc>>11)&0x3ff, mc&0x3ff,
  688. (lf>>22)&0x07, (lf>>11)&0x3ff, lf&0x3ff,
  689. vdi_fio_read_register(coreIdx, 0x88f4), /* GDI empty */
  690. avail_cu, avail_tu, avail_tc, avail_lf, avail_ip);
  691. /* CU/TU Queue count */
  692. reg_val = ReadRegVCE(coreIdx, 0, 0x12C);
  693. VLOG(ERR,"[DCIDEBUG] QUEUE COUNT: CU(%5d) TU(%5d) ", (reg_val>>16)&0xffff, reg_val&0xffff);
  694. reg_val = ReadRegVCE(coreIdx, 0, 0x1A0);
  695. VLOG(ERR,"TC(%5d) IP(%5d) ", (reg_val>>16)&0xffff, reg_val&0xffff);
  696. reg_val = ReadRegVCE(coreIdx, 0, 0x1A4);
  697. VLOG(ERR,"LF(%5d)\n", (reg_val>>16)&0xffff);
  698. VLOG(ERR,"VALID SIGNAL : CU0(%d) CU1(%d) CU2(%d) TU(%d) TC(%d) IP(%5d) LF(%5d)\n"
  699. " DCI_FALSE_RUN(%d) VCE_RESET(%d) CORE_INIT(%d) SET_RUN_CTU(%d) \n",
  700. (reg_val>>6)&1, (reg_val>>5)&1, (reg_val>>4)&1, (reg_val>>3)&1,
  701. (reg_val>>2)&1, (reg_val>>1)&1, (reg_val>>0)&1,
  702. (reg_val>>10)&1, (reg_val>>9)&1, (reg_val>>8)&1, (reg_val>>7)&1);
  703. VLOG(ERR,"State TQ: 0x%08x IP: 0x%08x MC: 0x%08x LF: 0x%08x\n",
  704. ReadRegVCE(coreIdx, 0, 0xd0), ReadRegVCE(coreIdx, 0, 0xd4), ReadRegVCE(coreIdx, 0, 0xd8), ReadRegVCE(coreIdx, 0, 0xdc));
  705. VLOG(ERR,"BWB[1]: RESPONSE_CNT(0x%08x) INFO(0x%08x)\n", ReadRegVCE(coreIdx, 0, 0x194), ReadRegVCE(coreIdx, 0, 0x198));
  706. VLOG(ERR,"BWB[2]: RESPONSE_CNT(0x%08x) INFO(0x%08x)\n", ReadRegVCE(coreIdx, 0, 0x194), ReadRegVCE(coreIdx, 0, 0x198));
  707. VLOG(ERR,"DCI INFO\n");
  708. VLOG(ERR,"READ_CNT_0 : 0x%08x\n", ReadRegVCE(coreIdx, 0, 0x110));
  709. VLOG(ERR,"READ_CNT_1 : 0x%08x\n", ReadRegVCE(coreIdx, 0, 0x114));
  710. VLOG(ERR,"READ_CNT_2 : 0x%08x\n", ReadRegVCE(coreIdx, 0, 0x118));
  711. VLOG(ERR,"WRITE_CNT_0: 0x%08x\n", ReadRegVCE(coreIdx, 0, 0x11c));
  712. VLOG(ERR,"WRITE_CNT_1: 0x%08x\n", ReadRegVCE(coreIdx, 0, 0x120));
  713. VLOG(ERR,"WRITE_CNT_2: 0x%08x\n", ReadRegVCE(coreIdx, 0, 0x124));
  714. reg_val = ReadRegVCE(coreIdx, 0, 0x128);
  715. VLOG(ERR,"LF_DEBUG_PT: 0x%08x\n", reg_val & 0xffffffff);
  716. VLOG(ERR,"cur_main_state %2d, r_lf_pic_deblock_disable %1d, r_lf_pic_sao_disable %1d\n",
  717. (reg_val >> 16) & 0x1f,
  718. (reg_val >> 15) & 0x1,
  719. (reg_val >> 14) & 0x1);
  720. VLOG(ERR,"para_load_done %1d, i_rdma_ack_wait %1d, i_sao_intl_col_done %1d, i_sao_outbuf_full %1d\n",
  721. (reg_val >> 13) & 0x1,
  722. (reg_val >> 12) & 0x1,
  723. (reg_val >> 11) & 0x1,
  724. (reg_val >> 10) & 0x1);
  725. VLOG(ERR,"lf_sub_done %1d, i_wdma_ack_wait %1d, lf_all_sub_done %1d, cur_ycbcr %1d, sub8x8_done %2d\n",
  726. (reg_val >> 9) & 0x1,
  727. (reg_val >> 8) & 0x1,
  728. (reg_val >> 6) & 0x1,
  729. (reg_val >> 4) & 0x1,
  730. reg_val & 0xf);
  731. VLOG(ERR,"[-] VCE REG Dump\n");
  732. VLOG(ERR,"[-] VCE REG Dump\n");
  733. VLOG(ERR,"-------------------------------------------------------------------------------\n");
  734. }
  735. if (productId == PRODUCT_ID_420 || productId == PRODUCT_ID_420L)
  736. {
  737. int rd, wr;
  738. Uint32 reg_val, num;
  739. int vce_enc_debug[12] = {0, };
  740. int set_mode;
  741. int vcore_num, vcore_idx;
  742. Uint32 index;
  743. Uint32 vcpu_reg[31]= {0,};
  744. SetClockGate(coreIdx, 1);
  745. VLOG(ERR,"-------------------------------------------------------------------------------\n");
  746. VLOG(ERR,"------ VCPU STATUS(ENC) -----\n");
  747. VLOG(ERR,"-------------------------------------------------------------------------------\n");
  748. rd = VpuReadReg(coreIdx, W4_BS_RD_PTR);
  749. wr = VpuReadReg(coreIdx, W4_BS_WR_PTR);
  750. VLOG(ERR,"RD_PTR: 0x%08x WR_PTR: 0x%08x BS_OPT: 0x%08x BS_PARAM: 0x%08x\n",
  751. rd, wr, VpuReadReg(coreIdx, W4_BS_OPTION), VpuReadReg(coreIdx, W4_BS_PARAM));
  752. // --------- VCPU register Dump
  753. VLOG(ERR,"[+] VCPU REG Dump\n");
  754. for (index = 0; index < 25; index++) {
  755. VpuWriteReg (coreIdx, W4_VPU_PDBG_IDX_REG, (1<<9) | (index & 0xff));
  756. vcpu_reg[index] = VpuReadReg (coreIdx, W4_VPU_PDBG_RDATA_REG);
  757. if (index < 16) {
  758. VLOG(ERR,"0x%08x\t", vcpu_reg[index]);
  759. if ((index % 4) == 3) VLOG(ERR,"\n");
  760. }
  761. else {
  762. switch (index) {
  763. case 16: VLOG(ERR,"CR0: 0x%08x\t", vcpu_reg[index]); break;
  764. case 17: VLOG(ERR,"CR1: 0x%08x\n", vcpu_reg[index]); break;
  765. case 18: VLOG(ERR,"ML: 0x%08x\t", vcpu_reg[index]); break;
  766. case 19: VLOG(ERR,"MH: 0x%08x\n", vcpu_reg[index]); break;
  767. case 21: VLOG(ERR,"LR: 0x%08x\n", vcpu_reg[index]); break;
  768. case 22: VLOG(ERR,"PC: 0x%08x\n", vcpu_reg[index]);break;
  769. case 23: VLOG(ERR,"SR: 0x%08x\n", vcpu_reg[index]);break;
  770. case 24: VLOG(ERR,"SSP: 0x%08x\n", vcpu_reg[index]);break;
  771. }
  772. }
  773. }
  774. VLOG(ERR,"[-] VCPU REG Dump\n");
  775. VLOG(ERR,"vce run flag = %d\n", VpuReadReg(coreIdx, 0x1E8));
  776. // --------- BIT register Dump
  777. VLOG(ERR,"[+] BPU REG Dump\n");
  778. for (index=0;index < 30; index++)
  779. {
  780. int temp;
  781. temp = vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x18));
  782. VLOG(ERR,"BITPC = 0x%08x\n", temp);
  783. if ( temp == 0xffffffff)
  784. return;
  785. }
  786. // --------- BIT HEVC Status Dump
  787. VLOG(ERR,"==================================\n");
  788. VLOG(ERR,"[-] BPU REG Dump\n");
  789. VLOG(ERR,"==================================\n");
  790. VLOG(ERR,"DBG_FIFO_VALID [%08x]\n",vdi_fio_read_register(coreIdx, (W4_REG_BASE + 0x8000 + 0x6C)));
  791. //SDMA debug information
  792. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20) | (1<<16)| 0x13c);
  793. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  794. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  795. VLOG(ERR,"SDMA_DBG_INFO [%08x]\n", reg_val);
  796. VLOG(ERR,"\t- [ 28] need_more_update : 0x%x \n", (reg_val>>28)&0x1 );
  797. VLOG(ERR,"\t- [27:25] tr_init_fsm : 0x%x \n", (reg_val>>25)&0x7 );
  798. VLOG(ERR,"\t- [24:18] remain_trans_size : 0x%x \n", (reg_val>>18)&0x7F);
  799. VLOG(ERR,"\t- [17:13] wdata_out_cnt : 0x%x \n", (reg_val>>13)&0x1F);
  800. VLOG(ERR,"\t- [12:10] wdma_wd_fsm : 0x%x \n", (reg_val>>10)&0x1F);
  801. VLOG(ERR,"\t- [ 9: 7] wdma_wa_fsm : 0x%x ", (reg_val>> 7)&0x7 );
  802. if (((reg_val>>7) &0x7) == 3)
  803. VLOG(ERR,"-->WDMA_WAIT_ADDR \n");
  804. else
  805. VLOG(ERR,"\n");
  806. VLOG(ERR,"\t- [ 6: 5] sdma_init_fsm : 0x%x \n", (reg_val>> 5)&0x3 );
  807. VLOG(ERR,"\t- [ 4: 1] save_fsm : 0x%x \n", (reg_val>> 1)&0xF );
  808. VLOG(ERR,"\t- [ 0] unalign_written : 0x%x \n", (reg_val>> 0)&0x1 );
  809. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16)| 0x13b);
  810. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  811. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  812. VLOG(ERR,"SDMA_NAL_MEM_INF [%08x]\n", reg_val);
  813. VLOG(ERR,"\t- [ 7: 1] nal_mem_empty_room : 0x%x \n", (reg_val>> 1)&0x3F);
  814. VLOG(ERR,"\t- [ 0] ge_wnbuf_size : 0x%x \n", (reg_val>> 0)&0x1 );
  815. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16) | 0x131);
  816. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  817. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  818. VLOG(ERR,"SDMA_IRQ [%08x]: [1]sdma_irq : 0x%x, [2]enable_sdma_irq : 0x%x\n",reg_val, (reg_val >> 1)&0x1,(reg_val &0x1));
  819. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16) | 0x134);
  820. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  821. VLOG(ERR,"SDMA_BS_BASE_ADDR [%08x]\n",vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78)));
  822. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16) | 0x135);
  823. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  824. VLOG(ERR,"SDMA_NAL_STR_ADDR [%08x]\n",vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78)));
  825. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16) | 0x136);
  826. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  827. VLOG(ERR,"SDMA_IRQ_ADDR [%08x]\n",vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78)));
  828. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16) | 0x137);
  829. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  830. VLOG(ERR,"SDMA_BS_END_ADDR [%08x]\n",vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78)));
  831. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16) | 0x13A);
  832. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  833. VLOG(ERR,"SDMA_CUR_ADDR [%08x]\n",vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78)));
  834. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16) | 0x139);
  835. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  836. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  837. VLOG(ERR,"SDMA_STATUS [%08x]\n",reg_val);
  838. VLOG(ERR,"\t- [2] all_wresp_done : 0x%x \n", (reg_val>> 2)&0x1);
  839. VLOG(ERR,"\t- [1] sdma_init_busy : 0x%x \n", (reg_val>> 1)&0x1 );
  840. VLOG(ERR,"\t- [0] save_busy : 0x%x \n", (reg_val>> 0)&0x1 );
  841. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16) | 0x164);
  842. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  843. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  844. VLOG(ERR,"SHU_DBG [%08x] : shu_unaligned_num (0x%x)\n",reg_val, reg_val);
  845. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16) | 0x169);
  846. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  847. VLOG(ERR,"SHU_NBUF_WPTR [%08x]\n",vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78)));
  848. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16) | 0x16A);
  849. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  850. VLOG(ERR,"SHU_NBUF_RPTR [%08x]\n",vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78)));
  851. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16) | 0x16C);
  852. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  853. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78));
  854. VLOG(ERR,"SHU_NBUF_INFO [%08x]\n",reg_val);
  855. VLOG(ERR,"\t- [5:1] nbuf_remain_byte : 0x%x \n", (reg_val>> 1)&0x1F);
  856. VLOG(ERR,"\t- [ 0] nbuf_wptr_wrap : 0x%x \n", (reg_val>> 0)&0x1 );
  857. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16) | 0x184);
  858. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  859. VLOG(ERR,"CTU_LAST_ENC_POS [%08x]\n",vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78)));
  860. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16) | 0x187);
  861. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  862. VLOG(ERR,"CTU_POS_IN_PIC [%08x]\n",vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78)));
  863. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16) | 0x110);
  864. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  865. VLOG(ERR,"MIB_EXTADDR [%08x]\n",vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78)));
  866. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16) | 0x111);
  867. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  868. VLOG(ERR,"MIB_INTADDR [%08x]\n",vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78)));
  869. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16) | 0x113);
  870. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  871. VLOG(ERR,"MIB_CMD [%08x]\n",vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78)));
  872. vdi_fio_write_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x74),(1<<20)| (1<<16) | 0x114);
  873. while((vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x7c))& 0x1) ==0 );
  874. VLOG(ERR,"MIB_BUSY [%08x]\n",vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x78)));
  875. VLOG(ERR,"DBG_BPU_ENC_NB0 [%08x]\n",vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x40)));
  876. VLOG(ERR,"DBG_BPU_CTU_CTRL0 [%08x]\n",vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x44)));
  877. VLOG(ERR,"DBG_BPU_CAB_FSM0 [%08x]\n",vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x48)));
  878. VLOG(ERR,"DBG_BPU_BIN_GEN0 [%08x]\n",vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x4C)));
  879. VLOG(ERR,"DBG_BPU_CAB_MBAE0 [%08x]\n",vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x50)));
  880. VLOG(ERR,"DBG_BPU_BUS_BUSY [%08x]\n",vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x68)));
  881. VLOG(ERR,"DBG_FIFO_VALID [%08x]\n",vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x6C)));
  882. VLOG(ERR,"DBG_BPU_CTU_CTRL1 [%08x]\n",vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x54)));
  883. VLOG(ERR,"DBG_BPU_CTU_CTRL2 [%08x]\n",vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x58)));
  884. VLOG(ERR,"DBG_BPU_CTU_CTRL3 [%08x]\n",vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x5C)));
  885. for (index=0x80; index<0xA0; index+=4) {
  886. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + index));
  887. num = (index - 0x80)/2;
  888. VLOG(ERR,"DBG_BIT_STACK [%08x] : Stack%02d (0x%04x), Stack%02d(0x%04x) \n",reg_val, num, reg_val>>16, num+1, reg_val & 0xffff);
  889. }
  890. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0xA0));
  891. VLOG(ERR,"DGB_BIT_CORE_INFO [%08x] : pc_ctrl_id (0x%04x), pfu_reg_pc(0x%04x)\n",reg_val,reg_val>>16, reg_val & 0xffff);
  892. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0xA4));
  893. VLOG(ERR,"DGB_BIT_CORE_INFO [%08x] : ACC0 (0x%08x)\n",reg_val, reg_val);
  894. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0xA8));
  895. VLOG(ERR,"DGB_BIT_CORE_INFO [%08x] : ACC1 (0x%08x)\n",reg_val, reg_val);
  896. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0xAC));
  897. VLOG(ERR,"DGB_BIT_CORE_INFO [%08x] : pfu_ibuff_id(0x%04x), pfu_ibuff_op(0x%04x)\n",reg_val,reg_val>>16, reg_val & 0xffff);
  898. for (num=0; num<5; num+=1) {
  899. reg_val = vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0xB0));
  900. VLOG(ERR,"DGB_BIT_CORE_INFO [%08x] : core_pram_rd_en(0x%04x), core_pram_rd_addr(0x%04x)\n",reg_val,reg_val>>16, reg_val & 0xffff);
  901. }
  902. VLOG(ERR,"SAO_LUMA_OFFSET [%08x]\n",vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0xB4)));
  903. VLOG(ERR,"SAO_CB_OFFSET [%08x]\n",vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0xB8)));
  904. VLOG(ERR,"SAO_CR_OFFSET [%08x]\n",vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0xBC)));
  905. VLOG(ERR,"GDI_NO_MORE_REQ [%08x]\n",vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x8f0)));
  906. VLOG(ERR,"GDI_EMPTY_FLAG [%08x]\n",vdi_fio_read_register(coreIdx,(W4_REG_BASE + 0x8000 + 0x8f4)));
  907. if ( productId == PRODUCT_ID_420) {
  908. VLOG(ERR,"WAVE420_CODE VCE DUMP\n");
  909. vce_enc_debug[0] = 0x0bc8;//MODE SEL
  910. vce_enc_debug[1] = 0x0be0;
  911. vce_enc_debug[2] = 0x0bcc;
  912. vce_enc_debug[3] = 0x0be4;
  913. vce_enc_debug[4] = 0x0be8;
  914. vce_enc_debug[5] = 0x0bec;
  915. vce_enc_debug[6] = 0x0bc0;
  916. vce_enc_debug[7] = 0x0bc4;
  917. vce_enc_debug[8] = 0x0bf0;
  918. vce_enc_debug[9] = 0x0bf4;
  919. set_mode = 0x0bc8;
  920. vcore_num = 1;
  921. }
  922. else if (productId == PRODUCT_ID_420L) {
  923. VLOG(ERR,"WAVE420L_CODE VCE DUMP\n");
  924. vce_enc_debug[0] = 0x0bd0;//MODE SEL
  925. vce_enc_debug[1] = 0x0bd4;
  926. vce_enc_debug[2] = 0x0bd8;
  927. vce_enc_debug[3] = 0x0bdc;
  928. vce_enc_debug[4] = 0x0be0;
  929. vce_enc_debug[5] = 0x0be4;
  930. vce_enc_debug[6] = 0x0be8;
  931. vce_enc_debug[7] = 0x0bc4;
  932. vce_enc_debug[8] = 0x0bf0;
  933. vce_enc_debug[9] = 0x0bf4;
  934. set_mode = 0x0bd0;
  935. vcore_num = 1;
  936. }
  937. for (vcore_idx = 0; vcore_idx < vcore_num ; vcore_idx++)
  938. {
  939. VLOG(ERR,"==========================================\n");
  940. VLOG(ERR,"[+] VCE REG Dump VCORE_IDX : %d\n",vcore_idx);
  941. VLOG(ERR,"==========================================\n");
  942. DisplayVceEncDebugCommon (coreIdx, vcore_idx, set_mode, vce_enc_debug[0], vce_enc_debug[1], vce_enc_debug[2]);
  943. DisplayVceEncDebugDCI (coreIdx, vcore_idx, set_mode, vce_enc_debug);
  944. DisplayVceEncDebugRDO (coreIdx, vcore_idx, set_mode, vce_enc_debug);
  945. DisplayVceEncDebugLF (coreIdx, vcore_idx, set_mode, vce_enc_debug);
  946. DisplayVceEncDebugSFU (coreIdx, vcore_idx, set_mode, vce_enc_debug);
  947. DisplayVceEncDebugDCI2 (coreIdx, vcore_idx, set_mode, vce_enc_debug);
  948. DisplayVceEncDebugDCILast (coreIdx, vcore_idx, set_mode, vce_enc_debug);
  949. DisplayVceEncDebugBigBufferCnt (coreIdx, vcore_idx, set_mode, vce_enc_debug);
  950. DisplayVceEncDebugBigBufferAddr (coreIdx, vcore_idx, set_mode, vce_enc_debug);
  951. DisplayVceEncDebugSubWb (coreIdx, vcore_idx, set_mode, vce_enc_debug);
  952. DisplayVceEncDebugFBC (coreIdx, vcore_idx, set_mode, vce_enc_debug);
  953. }
  954. }
  955. if ( productId == PRODUCT_ID_520 )
  956. {
  957. int rd, wr;
  958. SetClockGate(coreIdx, 1);
  959. VLOG(ERR,"-------------------------------------------------------------------------------\n");
  960. VLOG(ERR,"------ VCPU STATUS(ENC) -----\n");
  961. VLOG(ERR,"-------------------------------------------------------------------------------\n");
  962. rd = VpuReadReg(coreIdx, W4_BS_RD_PTR);
  963. wr = VpuReadReg(coreIdx, W4_BS_WR_PTR);
  964. VLOG(ERR,"RD_PTR: 0x%08x WR_PTR: 0x%08x BS_OPT: 0x%08x BS_PARAM: 0x%08x\n",
  965. rd, wr, VpuReadReg(coreIdx, W4_BS_OPTION), VpuReadReg(coreIdx, W4_BS_PARAM));
  966. VLOG(ERR,"=========Need to add debug code here =========\n");
  967. }
  968. else
  969. {
  970. }
  971. SetClockGate(coreIdx, 0);
  972. }
  973. void HandleEncoderError(
  974. EncHandle handle,
  975. Uint32 encPicCnt,
  976. EncOutputInfo* outputInfo
  977. )
  978. {
  979. UNREFERENCED_PARAMETER(handle);
  980. }
  981. void HandleDecoderError(
  982. DecHandle handle,
  983. Uint32 frameIdx,
  984. TestDecConfig* param,
  985. vpu_buffer_t* fbMem,
  986. DecOutputInfo* outputInfo
  987. )
  988. {
  989. UNREFERENCED_PARAMETER(handle);
  990. UNREFERENCED_PARAMETER(outputInfo);
  991. }
  992. void PrintMemoryAccessViolationReason(
  993. Uint32 core_idx,
  994. void *outp
  995. )
  996. {
  997. UNREFERENCED_PARAMETER(core_idx);
  998. UNREFERENCED_PARAMETER(outp);
  999. }
  1000. /**
  1001. * \brief Handle error cases depending on product
  1002. * \return -1 SEQUENCE ERROR
  1003. */
  1004. Int32 HandleDecInitSequenceError(DecHandle handle, Uint32 productId, DecOpenParam* openParam, DecInitialInfo* seqInfo, RetCode apiErrorCode)
  1005. {
  1006. if (apiErrorCode == RETCODE_MEMORY_ACCESS_VIOLATION) {
  1007. PrintMemoryAccessViolationReason(handle->coreIdx, NULL);
  1008. return -1;
  1009. }
  1010. if (PRODUCT_ID_W_SERIES(productId)) {
  1011. if (seqInfo->seqInitErrReason == WAVE4_SPSERR_NOT_FOUND) {
  1012. return -2;
  1013. } else {
  1014. if (seqInfo->seqInitErrReason == WAVE4_SPEC_OVER_PICTURE_WIDTH_SIZE) {
  1015. VLOG(ERR, "Not supported picture width: MAX_SIZE(8192): %d\n", seqInfo->picWidth);
  1016. }
  1017. if (seqInfo->seqInitErrReason == WAVE4_SPEC_OVER_PICTURE_HEIGHT_SIZE) {
  1018. VLOG(ERR, "Not supported picture height: MAX_SIZE(8192): %d\n", seqInfo->picHeight);
  1019. }
  1020. if (seqInfo->seqInitErrReason == WAVE4_SPEC_OVER_CHROMA_FORMAT) {
  1021. VLOG(ERR, "Not supported chroma idc: %d\n", seqInfo->chromaFormatIDC);
  1022. }
  1023. if (seqInfo->seqInitErrReason == WAVE4_SPEC_OVER_BIT_DEPTH) {
  1024. VLOG(INFO, "Not supported Luma or Chroma bitdepth: L(%d), C(%d)\n", seqInfo->lumaBitdepth, seqInfo->chromaBitdepth);
  1025. }
  1026. if (seqInfo->seqInitErrReason == WAVE4_SPEC_OVER_PROFILE) {
  1027. VLOG(INFO, "Not supported profile: %d\n", seqInfo->profile);
  1028. }
  1029. if (seqInfo->seqInitErrReason == WAVE4_SPSERR_NOT_FOUND) {
  1030. VLOG(INFO, "Not found SPS: RD_PTR(0x%08x), WR_PTR(0x%08x)\n", seqInfo->rdPtr, seqInfo->wrPtr);
  1031. }
  1032. return -1;
  1033. }
  1034. }
  1035. else {
  1036. if (openParam->bitstreamMode == BS_MODE_PIC_END && (seqInfo->seqInitErrReason&(1<<31))) {
  1037. VLOG(ERR, "SEQUENCE HEADER NOT FOUND\n");
  1038. return -1;
  1039. }
  1040. else {
  1041. return -1;
  1042. }
  1043. }
  1044. }