vdec.c 76 KB

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  1. #include <linux/kernel.h>
  2. #include <linux/mm.h>
  3. #include <linux/interrupt.h>
  4. #include <linux/ioport.h>
  5. #include <linux/module.h>
  6. #include <linux/mutex.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/dma-mapping.h>
  9. #include <linux/of.h>
  10. #include <linux/pm_runtime.h>
  11. #include <linux/wait.h>
  12. #include <linux/list.h>
  13. #include <linux/clk.h>
  14. #include <linux/delay.h>
  15. #include <linux/uaccess.h>
  16. #include <linux/cdev.h>
  17. #include <linux/slab.h>
  18. #include <linux/of_address.h>
  19. #include <linux/sched.h>
  20. #include <linux/sched/signal.h>
  21. #include <linux/version.h>
  22. #include <linux/kfifo.h>
  23. #include <linux/kthread.h>
  24. #include <linux/reset.h>
  25. #include <asm/io.h>
  26. #include <soc/sifive/sifive_l2_cache.h>
  27. #include "../../../vpuapi/vpuconfig.h"
  28. #include "vpu.h"
  29. //#define ENABLE_DEBUG_MSG
  30. #ifdef ENABLE_DEBUG_MSG
  31. #define DPRINTK(args...) printk(KERN_INFO args);
  32. #else
  33. #define DPRINTK(args...)
  34. #endif
  35. /* definitions to be changed as customer configuration */
  36. /* if you want to have clock gating scheme frame by frame */
  37. /* #define VPU_SUPPORT_CLOCK_CONTROL */
  38. /* if the driver want to use interrupt service from kernel ISR */
  39. #define VPU_SUPPORT_ISR
  40. #ifdef VPU_SUPPORT_ISR
  41. /* if the driver want to disable and enable IRQ whenever interrupt asserted. */
  42. //#define VPU_IRQ_CONTROL
  43. #endif
  44. #define VPU_SUPPORT_CLOCK_CONTROL
  45. /* if clktree is work,try this...*/
  46. #define STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  47. /* if the platform driver knows the name of this driver */
  48. /* VPU_PLATFORM_DEVICE_NAME */
  49. #define VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  50. /* if this driver knows the dedicated video memory address */
  51. //#define VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  52. static void starfive_flush_dcache(unsigned long start, unsigned long len)
  53. {
  54. sifive_l2_flush64_range(start, len);
  55. }
  56. #define VPU_PLATFORM_DEVICE_NAME "vdec"
  57. #define VPU_CLK_NAME "vcodec"
  58. #define VPU_DEV_NAME "vdec"
  59. /* if the platform driver knows this driver */
  60. /* the definition of VPU_REG_BASE_ADDR and VPU_REG_SIZE are not meaningful */
  61. #define VPU_REG_BASE_ADDR 0x118F0000
  62. #define VPU_REG_SIZE (0x4000*MAX_NUM_VPU_CORE)
  63. #ifdef VPU_SUPPORT_ISR
  64. #define VPU_IRQ_NUM (23)
  65. #endif
  66. /* this definition is only for chipsnmedia FPGA board env */
  67. /* so for SOC env of customers can be ignored */
  68. #ifndef VM_RESERVED /*for kernel up to 3.7.0 version*/
  69. #define VM_RESERVED (VM_DONTEXPAND | VM_DONTDUMP)
  70. #endif
  71. struct device *vpu_dev;
  72. typedef struct vpu_drv_context_t {
  73. struct fasync_struct *async_queue;
  74. #ifdef SUPPORT_MULTI_INST_INTR
  75. unsigned long interrupt_reason[MAX_NUM_INSTANCE];
  76. #else
  77. unsigned long interrupt_reason;
  78. #endif
  79. u32 open_count; /*!<< device reference count. Not instance count */
  80. } vpu_drv_context_t;
  81. /* To track the allocated memory buffer */
  82. typedef struct vpudrv_buffer_pool_t {
  83. struct list_head list;
  84. struct vpudrv_buffer_t vb;
  85. struct file *filp;
  86. } vpudrv_buffer_pool_t;
  87. /* To track the instance index and buffer in instance pool */
  88. typedef struct vpudrv_instanace_list_t {
  89. struct list_head list;
  90. unsigned long inst_idx;
  91. unsigned long core_idx;
  92. struct file *filp;
  93. } vpudrv_instanace_list_t;
  94. typedef struct vpudrv_instance_pool_t {
  95. unsigned char codecInstPool[MAX_NUM_INSTANCE][MAX_INST_HANDLE_SIZE];
  96. } vpudrv_instance_pool_t;
  97. #ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  98. typedef struct vpu_clkgen_t {
  99. void __iomem *en_ctrl;
  100. uint32_t rst_mask;
  101. } vpu_clkgen_t;
  102. #endif
  103. struct clk_bulk_data vpu_clks[] = {
  104. { .id = "apb_clk" },
  105. { .id = "axi_clk" },
  106. { .id = "bpu_clk" },
  107. { .id = "vce_clk" },
  108. { .id = "noc_bus" },
  109. };
  110. typedef struct vpu_clk_t {
  111. #ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  112. void __iomem *clkgen;
  113. void __iomem *rst_ctrl;
  114. void __iomem *rst_status;
  115. void __iomem *noc_bus;
  116. uint32_t en_shift;
  117. uint32_t en_mask;
  118. vpu_clkgen_t apb_clk;
  119. vpu_clkgen_t axi_clk;
  120. vpu_clkgen_t bpu_clk;
  121. vpu_clkgen_t vce_clk;
  122. vpu_clkgen_t aximem_128b;
  123. #else
  124. struct clk_bulk_data *clks;
  125. struct reset_control *resets;
  126. int nr_clks;
  127. #endif
  128. struct device *dev;
  129. bool noc_ctrl;
  130. } vpu_clk_t;
  131. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  132. #include "vmm.h"
  133. static video_mm_t s_vmem;
  134. static vpudrv_buffer_t s_video_memory = {0};
  135. #endif /*VPU_SUPPORT_RESERVED_VIDEO_MEMORY*/
  136. static int vpu_hw_reset(void);
  137. static void vpu_clk_disable(vpu_clk_t *clk);
  138. static int vpu_clk_enable(vpu_clk_t *clk);
  139. static vpu_clk_t *vpu_clk_get(struct platform_device *pdev);
  140. static void vpu_clk_put(vpu_clk_t *clk);
  141. static int vpu_pmu_enable(struct device *dev);
  142. static void vpu_pmu_disable(struct device *dev);
  143. /* end customer definition */
  144. static vpudrv_buffer_t s_instance_pool = {0};
  145. static vpudrv_buffer_t s_common_memory = {0};
  146. static vpu_drv_context_t s_vpu_drv_context;
  147. static dev_t s_vpu_devt;
  148. static int s_vpu_major;
  149. static struct cdev s_vpu_cdev;
  150. static struct class *s_vpu_class;
  151. static vpu_clk_t *s_vpu_clk;
  152. static int s_vpu_open_ref_count;
  153. #ifdef VPU_SUPPORT_ISR
  154. static int s_vpu_irq = VPU_IRQ_NUM;
  155. #endif
  156. static vpudrv_buffer_t s_vpu_register = {0};
  157. #ifdef SUPPORT_MULTI_INST_INTR
  158. static int s_interrupt_flag[MAX_NUM_INSTANCE];
  159. static wait_queue_head_t s_interrupt_wait_q[MAX_NUM_INSTANCE];
  160. typedef struct kfifo kfifo_t;
  161. static kfifo_t s_interrupt_pending_q[MAX_NUM_INSTANCE];
  162. static spinlock_t s_kfifo_lock = __SPIN_LOCK_UNLOCKED(s_kfifo_lock);
  163. #else
  164. static int s_interrupt_flag;
  165. static wait_queue_head_t s_interrupt_wait_q;
  166. #endif
  167. static spinlock_t s_vpu_lock = __SPIN_LOCK_UNLOCKED(s_vpu_lock);
  168. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
  169. static DECLARE_MUTEX(s_vpu_sem);
  170. #else
  171. static DEFINE_SEMAPHORE(s_vpu_sem);
  172. #endif
  173. static struct list_head s_vbp_head = LIST_HEAD_INIT(s_vbp_head);
  174. static struct list_head s_inst_list_head = LIST_HEAD_INIT(s_inst_list_head);
  175. static vpu_bit_firmware_info_t s_bit_firmware_info[MAX_NUM_VPU_CORE];
  176. //#ifdef CONFIG_PM
  177. /* implement to power management functions */
  178. #define BIT_BASE 0x0000
  179. #define BIT_CODE_RUN (BIT_BASE + 0x000)
  180. #define BIT_CODE_DOWN (BIT_BASE + 0x004)
  181. #define BIT_INT_CLEAR (BIT_BASE + 0x00C)
  182. #define BIT_INT_STS (BIT_BASE + 0x010)
  183. #define BIT_CODE_RESET (BIT_BASE + 0x014)
  184. #define BIT_INT_REASON (BIT_BASE + 0x174)
  185. #define BIT_BUSY_FLAG (BIT_BASE + 0x160)
  186. #define BIT_RUN_COMMAND (BIT_BASE + 0x164)
  187. #define BIT_RUN_INDEX (BIT_BASE + 0x168)
  188. #define BIT_RUN_COD_STD (BIT_BASE + 0x16C)
  189. /* WAVE5 registers */
  190. #define W5_REG_BASE 0x0000
  191. #define W5_VPU_BUSY_STATUS (W5_REG_BASE + 0x0070)
  192. #define W5_VPU_INT_REASON_CLEAR (W5_REG_BASE + 0x0034)
  193. #define W5_VPU_VINT_CLEAR (W5_REG_BASE + 0x003C)
  194. #define W5_VPU_VPU_INT_STS (W5_REG_BASE + 0x0044)
  195. #define W5_VPU_INT_REASON (W5_REG_BASE + 0x004c)
  196. #define W5_RET_FAIL_REASON (W5_REG_BASE + 0x010C)
  197. #ifdef SUPPORT_MULTI_INST_INTR
  198. #define W5_RET_BS_EMPTY_INST (W5_REG_BASE + 0x01E4)
  199. #define W5_RET_QUEUE_CMD_DONE_INST (W5_REG_BASE + 0x01E8)
  200. #define W5_RET_SEQ_DONE_INSTANCE_INFO (W5_REG_BASE + 0x01FC)
  201. typedef enum {
  202. INT_WAVE5_INIT_VPU = 0,
  203. INT_WAVE5_WAKEUP_VPU = 1,
  204. INT_WAVE5_SLEEP_VPU = 2,
  205. INT_WAVE5_CREATE_INSTANCE = 3,
  206. INT_WAVE5_FLUSH_INSTANCE = 4,
  207. INT_WAVE5_DESTORY_INSTANCE = 5,
  208. INT_WAVE5_INIT_SEQ = 6,
  209. INT_WAVE5_SET_FRAMEBUF = 7,
  210. INT_WAVE5_DEC_PIC = 8,
  211. INT_WAVE5_ENC_PIC = 8,
  212. INT_WAVE5_ENC_SET_PARAM = 9,
  213. #ifdef SUPPORT_SOURCE_RELEASE_INTERRUPT
  214. INT_WAVE5_ENC_SRC_RELEASE = 10,
  215. #endif
  216. INT_WAVE5_ENC_LOW_LATENCY = 13,
  217. INT_WAVE5_DEC_QUERY = 14,
  218. INT_WAVE5_BSBUF_EMPTY = 15,
  219. INT_WAVE5_BSBUF_FULL = 15,
  220. } Wave5InterruptBit;
  221. #endif
  222. /* WAVE5 INIT, WAKEUP */
  223. #define W5_PO_CONF (W5_REG_BASE + 0x0000)
  224. #define W5_VPU_VINT_ENABLE (W5_REG_BASE + 0x0048)
  225. #define W5_VPU_RESET_REQ (W5_REG_BASE + 0x0050)
  226. #define W5_VPU_RESET_STATUS (W5_REG_BASE + 0x0054)
  227. #define W5_VPU_REMAP_CTRL (W5_REG_BASE + 0x0060)
  228. #define W5_VPU_REMAP_VADDR (W5_REG_BASE + 0x0064)
  229. #define W5_VPU_REMAP_PADDR (W5_REG_BASE + 0x0068)
  230. #define W5_VPU_REMAP_CORE_START (W5_REG_BASE + 0x006C)
  231. #define W5_REMAP_CODE_INDEX 0
  232. /* WAVE5 registers */
  233. #define W5_ADDR_CODE_BASE (W5_REG_BASE + 0x0110)
  234. #define W5_CODE_SIZE (W5_REG_BASE + 0x0114)
  235. #define W5_CODE_PARAM (W5_REG_BASE + 0x0118)
  236. #define W5_INIT_VPU_TIME_OUT_CNT (W5_REG_BASE + 0x0130)
  237. #define W5_HW_OPTION (W5_REG_BASE + 0x012C)
  238. #define W5_RET_SUCCESS (W5_REG_BASE + 0x0108)
  239. #define W5_COMMAND (W5_REG_BASE + 0x0100)
  240. #define W5_VPU_HOST_INT_REQ (W5_REG_BASE + 0x0038)
  241. /* Product register */
  242. #define VPU_PRODUCT_CODE_REGISTER (BIT_BASE + 0x1044)
  243. #if defined(VPU_SUPPORT_PLATFORM_DRIVER_REGISTER) && defined(CONFIG_PM)
  244. static u32 s_vpu_reg_store[MAX_NUM_VPU_CORE][64];
  245. #endif
  246. //#endif //CONFIG_PM
  247. #define ReadVpuRegister(addr) *(volatile unsigned int *)(s_vpu_register.virt_addr + s_bit_firmware_info[core].reg_base_offset + addr)
  248. #define WriteVpuRegister(addr, val) *(volatile unsigned int *)(s_vpu_register.virt_addr + s_bit_firmware_info[core].reg_base_offset + addr) = (unsigned int)val
  249. #define WriteVpu(addr, val) *(volatile unsigned int *)(addr) = (unsigned int)val;
  250. #ifdef CONFIG_CPU_FREQ
  251. #include <linux/fs.h>
  252. #include <linux/file.h>
  253. struct freq_ctrl {
  254. struct device *dev;
  255. struct file *governor;
  256. struct file *maxfreq;
  257. struct file *parameters_off;
  258. const char *scaling_governor;
  259. const char *scaling_maxfreq;
  260. const char *scaling_parameters_off;
  261. const char *fixed_freq;
  262. char re_cpu_gov[16];
  263. char re_max_freq[16];
  264. struct mutex mutex_lock;
  265. int count;
  266. };
  267. static struct freq_ctrl *vpu_freq_ctrl;
  268. static int vpu_freq_open(struct freq_ctrl *vpu_freq_ctrl)
  269. {
  270. vpu_freq_ctrl->governor = filp_open(
  271. vpu_freq_ctrl->scaling_governor, O_RDWR, 0);
  272. if (IS_ERR(vpu_freq_ctrl->governor))
  273. goto out;
  274. vpu_freq_ctrl->maxfreq = filp_open(
  275. vpu_freq_ctrl->scaling_maxfreq, O_RDWR, 0);
  276. if (IS_ERR(vpu_freq_ctrl->maxfreq))
  277. goto out;
  278. vpu_freq_ctrl->parameters_off = filp_open(
  279. vpu_freq_ctrl->scaling_parameters_off, O_RDWR, 0);
  280. if (IS_ERR(vpu_freq_ctrl->parameters_off))
  281. goto out;
  282. return 0;
  283. out:
  284. dev_err(vpu_freq_ctrl->dev, "failed open scaling_governor.\n");
  285. return -ENXIO;
  286. }
  287. static int vpu_freq_close(void)
  288. {
  289. if (!vpu_freq_ctrl)
  290. return -ENODEV;
  291. mutex_destroy(&vpu_freq_ctrl->mutex_lock);
  292. if (vpu_freq_ctrl->governor && vpu_freq_ctrl->maxfreq
  293. && vpu_freq_ctrl->parameters_off) {
  294. fput(vpu_freq_ctrl->governor);
  295. fput(vpu_freq_ctrl->maxfreq);
  296. fput(vpu_freq_ctrl->parameters_off);
  297. vpu_freq_ctrl->governor = NULL;
  298. vpu_freq_ctrl->maxfreq = NULL;
  299. vpu_freq_ctrl->parameters_off = NULL;
  300. }
  301. return 0;
  302. }
  303. static int vpu_freq_save_env(void)
  304. {
  305. const char *fixed_freq = vpu_freq_ctrl->fixed_freq;
  306. const char *governor_mode = "performance";
  307. size_t rv;
  308. if (!vpu_freq_ctrl)
  309. return -ENODEV;
  310. mutex_lock(&vpu_freq_ctrl->mutex_lock);
  311. if (vpu_freq_ctrl->count == 0) {
  312. /*save env*/
  313. kernel_read(vpu_freq_ctrl->governor, vpu_freq_ctrl->re_cpu_gov,
  314. sizeof(vpu_freq_ctrl->re_cpu_gov), NULL);
  315. kernel_read(vpu_freq_ctrl->maxfreq, vpu_freq_ctrl->re_max_freq,
  316. sizeof(vpu_freq_ctrl->re_max_freq), NULL);
  317. /*setenv*/
  318. rv = kernel_write(vpu_freq_ctrl->maxfreq, fixed_freq,
  319. strlen(fixed_freq), NULL);
  320. rv = kernel_write(vpu_freq_ctrl->governor, governor_mode,
  321. strlen(governor_mode), NULL);
  322. rv = kernel_write(vpu_freq_ctrl->parameters_off, "1", 1, NULL);
  323. }
  324. vpu_freq_ctrl->count++;
  325. mutex_unlock(&vpu_freq_ctrl->mutex_lock);
  326. return 0;
  327. }
  328. static int vpu_freq_put_env(void)
  329. {
  330. size_t rv;
  331. if (!vpu_freq_ctrl)
  332. return -ENODEV;
  333. mutex_lock(&vpu_freq_ctrl->mutex_lock);
  334. vpu_freq_ctrl->count--;
  335. if (vpu_freq_ctrl->count == 0) {
  336. rv = kernel_write(vpu_freq_ctrl->governor, vpu_freq_ctrl->re_cpu_gov,
  337. strlen(vpu_freq_ctrl->re_cpu_gov), NULL);
  338. rv = kernel_write(vpu_freq_ctrl->maxfreq, vpu_freq_ctrl->re_max_freq,
  339. strlen(vpu_freq_ctrl->re_max_freq), NULL);
  340. rv = kernel_write(vpu_freq_ctrl->parameters_off, "0", 1, NULL);
  341. }
  342. mutex_unlock(&vpu_freq_ctrl->mutex_lock);
  343. return 0;
  344. }
  345. static int vpu_freq_init(struct device *dev)
  346. {
  347. int ret;
  348. const char *of_str;
  349. vpu_freq_ctrl = devm_kzalloc(dev, sizeof(*vpu_freq_ctrl), GFP_KERNEL);
  350. if (!vpu_freq_ctrl)
  351. return -ENOMEM;
  352. vpu_freq_ctrl->scaling_governor = "/sys/devices/system/cpu/cpufreq/policy0/scaling_governor";
  353. vpu_freq_ctrl->scaling_maxfreq = "/sys/devices/system/cpu/cpufreq/policy0/scaling_max_freq";
  354. vpu_freq_ctrl->scaling_parameters_off = "/sys/module/cpufreq/parameters/off";
  355. vpu_freq_ctrl->dev = dev;
  356. ret = vpu_freq_open(vpu_freq_ctrl);
  357. if (ret) {
  358. devm_kfree(dev, vpu_freq_ctrl);
  359. vpu_freq_ctrl = NULL;
  360. return ret;
  361. }
  362. if (!device_property_read_string(dev, "vdec,runtime-cpufreq", &of_str))
  363. vpu_freq_ctrl->fixed_freq = of_str;
  364. else
  365. vpu_freq_ctrl->fixed_freq = "1250000";
  366. vpu_freq_ctrl->count = 0;
  367. mutex_init(&vpu_freq_ctrl->mutex_lock);
  368. dev_dbg(dev, "fixed_freq:%s\n", vpu_freq_ctrl->fixed_freq);
  369. return 0;
  370. }
  371. #endif
  372. static int vpu_alloc_dma_buffer(vpudrv_buffer_t *vb)
  373. {
  374. if (!vb)
  375. return -1;
  376. DPRINTK("[VPUDRV] vpu_alloc_dma_buffer \n");
  377. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  378. vb->phys_addr = (unsigned long)vmem_alloc(&s_vmem, vb->size, 0);
  379. if ((unsigned long)vb->phys_addr == (unsigned long)-1) {
  380. printk(KERN_ERR "[VPUDRV] Physical memory allocation error size=%d\n", vb->size);
  381. return -1;
  382. }
  383. vb->base = (unsigned long)(s_video_memory.base + (vb->phys_addr - s_video_memory.phys_addr));
  384. #else
  385. vb->base = (unsigned long)dma_alloc_coherent(vpu_dev, PAGE_ALIGN(vb->size), (dma_addr_t *) (&vb->phys_addr), GFP_DMA | GFP_KERNEL);
  386. if ((void *)(vb->base) == NULL) {
  387. printk(KERN_ERR "[VPUDRV] Physical memory allocation error size=%d\n", vb->size);
  388. return -1;
  389. }
  390. starfive_flush_dcache(vb->phys_addr,PAGE_ALIGN(vb->size));
  391. #endif
  392. return 0;
  393. }
  394. static void vpu_free_dma_buffer(vpudrv_buffer_t *vb)
  395. {
  396. if (!vb)
  397. return;
  398. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  399. if (vb->base)
  400. vmem_free(&s_vmem, vb->phys_addr, 0);
  401. #else
  402. if (vb->base)
  403. dma_free_coherent(vpu_dev, PAGE_ALIGN(vb->size), (void *)vb->base, vb->phys_addr);
  404. #endif
  405. }
  406. static int vpu_free_instances(struct file *filp)
  407. {
  408. vpudrv_instanace_list_t *vil, *n;
  409. vpudrv_instance_pool_t *vip;
  410. void *vip_base;
  411. int instance_pool_size_per_core;
  412. void *vdi_mutexes_base;
  413. const int PTHREAD_MUTEX_T_DESTROY_VALUE = 0xdead10cc;
  414. DPRINTK("[VPUDRV] vpu_free_instances\n");
  415. instance_pool_size_per_core = (s_instance_pool.size/MAX_NUM_VPU_CORE); /* s_instance_pool.size assigned to the size of all core once call VDI_IOCTL_GET_INSTANCE_POOL by user. */
  416. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  417. {
  418. if (vil->filp == filp) {
  419. vip_base = (void *)(s_instance_pool.base + (instance_pool_size_per_core*vil->core_idx));
  420. DPRINTK("[VPUDRV] vpu_free_instances detect instance crash instIdx=%d, coreIdx=%d, vip_base=%p, instance_pool_size_per_core=%d\n", (int)vil->inst_idx, (int)vil->core_idx, vip_base, (int)instance_pool_size_per_core);
  421. vip = (vpudrv_instance_pool_t *)vip_base;
  422. if (vip) {
  423. memset(&vip->codecInstPool[vil->inst_idx], 0x00, 4); /* only first 4 byte is key point(inUse of CodecInst in vpuapi) to free the corresponding instance. */
  424. #define PTHREAD_MUTEX_T_HANDLE_SIZE 4
  425. vdi_mutexes_base = (vip_base + (instance_pool_size_per_core - PTHREAD_MUTEX_T_HANDLE_SIZE*4));
  426. DPRINTK("[VPUDRV] vpu_free_instances : force to destroy vdi_mutexes_base=%p in userspace \n", vdi_mutexes_base);
  427. if (vdi_mutexes_base) {
  428. int i;
  429. for (i = 0; i < 4; i++) {
  430. memcpy(vdi_mutexes_base, &PTHREAD_MUTEX_T_DESTROY_VALUE, PTHREAD_MUTEX_T_HANDLE_SIZE);
  431. vdi_mutexes_base += PTHREAD_MUTEX_T_HANDLE_SIZE;
  432. }
  433. }
  434. }
  435. s_vpu_open_ref_count--;
  436. list_del(&vil->list);
  437. kfree(vil);
  438. }
  439. }
  440. return 1;
  441. }
  442. static int vpu_free_buffers(struct file *filp)
  443. {
  444. vpudrv_buffer_pool_t *pool, *n;
  445. vpudrv_buffer_t vb;
  446. DPRINTK("[VPUDRV] vpu_free_buffers\n");
  447. list_for_each_entry_safe(pool, n, &s_vbp_head, list)
  448. {
  449. if (pool->filp == filp) {
  450. vb = pool->vb;
  451. if (vb.base) {
  452. vpu_free_dma_buffer(&vb);
  453. list_del(&pool->list);
  454. kfree(pool);
  455. }
  456. }
  457. }
  458. return 0;
  459. }
  460. #ifdef SUPPORT_MULTI_INST_INTR
  461. static inline u32 get_inst_idx(u32 reg_val)
  462. {
  463. u32 inst_idx;
  464. int i;
  465. for (i=0; i < MAX_NUM_INSTANCE; i++)
  466. {
  467. if(((reg_val >> i)&0x01) == 1)
  468. break;
  469. }
  470. inst_idx = i;
  471. return inst_idx;
  472. }
  473. static s32 get_vpu_inst_idx(vpu_drv_context_t *dev, u32 *reason, u32 empty_inst, u32 done_inst, u32 seq_inst)
  474. {
  475. s32 inst_idx;
  476. u32 reg_val;
  477. u32 int_reason;
  478. int_reason = *reason;
  479. DPRINTK("[VPUDRV][+]%s, int_reason=0x%x, empty_inst=0x%x, done_inst=0x%x\n", __func__, int_reason, empty_inst, done_inst);
  480. //printk(KERN_ERR "[VPUDRV][+]%s, int_reason=0x%x, empty_inst=0x%x, done_inst=0x%x\n", __func__, int_reason, empty_inst, done_inst);
  481. if (int_reason & (1 << INT_WAVE5_BSBUF_EMPTY))
  482. {
  483. reg_val = (empty_inst & 0xffff);
  484. inst_idx = get_inst_idx(reg_val);
  485. *reason = (1 << INT_WAVE5_BSBUF_EMPTY);
  486. DPRINTK("[VPUDRV] %s, W5_RET_BS_EMPTY_INST reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  487. goto GET_VPU_INST_IDX_HANDLED;
  488. }
  489. if (int_reason & (1 << INT_WAVE5_INIT_SEQ))
  490. {
  491. reg_val = (seq_inst & 0xffff);
  492. inst_idx = get_inst_idx(reg_val);
  493. *reason = (1 << INT_WAVE5_INIT_SEQ);
  494. DPRINTK("[VPUDRV] %s, RET_SEQ_DONE_INSTANCE_INFO INIT_SEQ reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  495. goto GET_VPU_INST_IDX_HANDLED;
  496. }
  497. if (int_reason & (1 << INT_WAVE5_DEC_PIC))
  498. {
  499. reg_val = (done_inst & 0xffff);
  500. inst_idx = get_inst_idx(reg_val);
  501. *reason = (1 << INT_WAVE5_DEC_PIC);
  502. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST DEC_PIC reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  503. if (int_reason & (1 << INT_WAVE5_ENC_LOW_LATENCY))
  504. {
  505. u32 ll_inst_idx;
  506. reg_val = (done_inst >> 16);
  507. ll_inst_idx = get_inst_idx(reg_val);
  508. if (ll_inst_idx == inst_idx)
  509. *reason = ((1 << INT_WAVE5_DEC_PIC) | (1 << INT_WAVE5_ENC_LOW_LATENCY));
  510. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST DEC_PIC and ENC_LOW_LATENCY reg_val=0x%x, inst_idx=%d, ll_inst_idx=%d\n", __func__, reg_val, inst_idx, ll_inst_idx);
  511. }
  512. goto GET_VPU_INST_IDX_HANDLED;
  513. }
  514. if (int_reason & (1 << INT_WAVE5_ENC_SET_PARAM))
  515. {
  516. reg_val = (seq_inst & 0xffff);
  517. inst_idx = get_inst_idx(reg_val);
  518. *reason = (1 << INT_WAVE5_ENC_SET_PARAM);
  519. DPRINTK("[VPUDRV] %s, RET_SEQ_DONE_INSTANCE_INFO ENC_SET_PARAM reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  520. goto GET_VPU_INST_IDX_HANDLED;
  521. }
  522. #ifdef SUPPORT_SOURCE_RELEASE_INTERRUPT
  523. if (int_reason & (1 << INT_WAVE5_ENC_SRC_RELEASE))
  524. {
  525. reg_val = (done_inst & 0xffff);
  526. inst_idx = get_inst_idx(reg_val);
  527. *reason = (1 << INT_WAVE5_ENC_SRC_RELEASE);
  528. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST ENC_SET_PARAM reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  529. goto GET_VPU_INST_IDX_HANDLED;
  530. }
  531. #endif
  532. if (int_reason & (1 << INT_WAVE5_ENC_LOW_LATENCY))
  533. {
  534. reg_val = (done_inst >> 16);
  535. inst_idx = get_inst_idx(reg_val);
  536. *reason = (1 << INT_WAVE5_ENC_LOW_LATENCY);
  537. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST ENC_LOW_LATENCY reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  538. goto GET_VPU_INST_IDX_HANDLED;
  539. }
  540. inst_idx = -1;
  541. *reason = 0;
  542. DPRINTK("[VPUDRV] %s, UNKNOWN INTERRUPT REASON: %08x\n", __func__, int_reason);
  543. GET_VPU_INST_IDX_HANDLED:
  544. DPRINTK("[VPUDRV][-]%s, inst_idx=%d. *reason=0x%x\n", __func__, inst_idx, *reason);
  545. return inst_idx;
  546. }
  547. #endif
  548. static irqreturn_t vpu_irq_handler(int irq, void *dev_id)
  549. {
  550. vpu_drv_context_t *dev = (vpu_drv_context_t *)dev_id;
  551. /* this can be removed. it also work in VPU_WaitInterrupt of API function */
  552. int core;
  553. int product_code;
  554. #ifdef SUPPORT_MULTI_INST_INTR
  555. u32 intr_reason;
  556. s32 intr_inst_index;
  557. #endif
  558. DPRINTK("[VPUDRV][+]%s\n", __func__);
  559. #ifdef VPU_IRQ_CONTROL
  560. disable_irq_nosync(s_vpu_irq);
  561. #endif
  562. #ifdef SUPPORT_MULTI_INST_INTR
  563. intr_inst_index = 0;
  564. intr_reason = 0;
  565. #endif
  566. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  567. if (s_bit_firmware_info[core].size == 0) {/* it means that we didn't get an information the current core from API layer. No core activated.*/
  568. printk(KERN_ERR "[VPUDRV] : s_bit_firmware_info[core].size is zero\n");
  569. continue;
  570. }
  571. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  572. if (PRODUCT_CODE_W_SERIES(product_code)) {
  573. if (ReadVpuRegister(W5_VPU_VPU_INT_STS)) {
  574. #ifdef SUPPORT_MULTI_INST_INTR
  575. u32 empty_inst;
  576. u32 done_inst;
  577. u32 seq_inst;
  578. u32 i, reason, reason_clr;
  579. reason = ReadVpuRegister(W5_VPU_INT_REASON);
  580. empty_inst = ReadVpuRegister(W5_RET_BS_EMPTY_INST);
  581. done_inst = ReadVpuRegister(W5_RET_QUEUE_CMD_DONE_INST);
  582. seq_inst = ReadVpuRegister(W5_RET_SEQ_DONE_INSTANCE_INFO);
  583. reason_clr = reason;
  584. DPRINTK("[VPUDRV] vpu_irq_handler reason=0x%x, empty_inst=0x%x, done_inst=0x%x, seq_inst=0x%x \n", reason, empty_inst, done_inst, seq_inst);
  585. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  586. if (0 == empty_inst && 0 == done_inst && 0 == seq_inst) break;
  587. intr_reason = reason;
  588. intr_inst_index = get_vpu_inst_idx(dev, &intr_reason, empty_inst, done_inst, seq_inst);
  589. DPRINTK("[VPUDRV] > instance_index: %d, intr_reason: %08x empty_inst: %08x done_inst: %08x seq_inst: %08x\n", intr_inst_index, intr_reason, empty_inst, done_inst, seq_inst);
  590. if (intr_inst_index >= 0 && intr_inst_index < MAX_NUM_INSTANCE) {
  591. if (intr_reason == (1 << INT_WAVE5_BSBUF_EMPTY)) {
  592. empty_inst = empty_inst & ~(1 << intr_inst_index);
  593. WriteVpuRegister(W5_RET_BS_EMPTY_INST, empty_inst);
  594. if (0 == empty_inst) {
  595. reason &= ~(1<<INT_WAVE5_BSBUF_EMPTY);
  596. }
  597. DPRINTK("[VPUDRV] %s, W5_RET_BS_EMPTY_INST Clear empty_inst=0x%x, intr_inst_index=%d\n", __func__, empty_inst, intr_inst_index);
  598. }
  599. if (intr_reason == (1 << INT_WAVE5_DEC_PIC))
  600. {
  601. done_inst = done_inst & ~(1 << intr_inst_index);
  602. WriteVpuRegister(W5_RET_QUEUE_CMD_DONE_INST, done_inst);
  603. if (0 == done_inst) {
  604. reason &= ~(1<<INT_WAVE5_DEC_PIC);
  605. }
  606. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  607. }
  608. if ((intr_reason == (1 << INT_WAVE5_INIT_SEQ)) || (intr_reason == (1 << INT_WAVE5_ENC_SET_PARAM)))
  609. {
  610. seq_inst = seq_inst & ~(1 << intr_inst_index);
  611. WriteVpuRegister(W5_RET_SEQ_DONE_INSTANCE_INFO, seq_inst);
  612. if (0 == seq_inst) {
  613. reason &= ~(1<<INT_WAVE5_INIT_SEQ | 1<<INT_WAVE5_ENC_SET_PARAM);
  614. }
  615. DPRINTK("[VPUDRV] %s, W5_RET_SEQ_DONE_INSTANCE_INFO Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  616. }
  617. if ((intr_reason == (1 << INT_WAVE5_ENC_LOW_LATENCY)))
  618. {
  619. done_inst = (done_inst >> 16);
  620. done_inst = done_inst & ~(1 << intr_inst_index);
  621. done_inst = (done_inst << 16);
  622. WriteVpuRegister(W5_RET_QUEUE_CMD_DONE_INST, done_inst);
  623. if (0 == done_inst) {
  624. reason &= ~(1 << INT_WAVE5_ENC_LOW_LATENCY);
  625. }
  626. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST INT_WAVE5_ENC_LOW_LATENCY Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  627. }
  628. if (!kfifo_is_full(&s_interrupt_pending_q[intr_inst_index])) {
  629. if (intr_reason == ((1 << INT_WAVE5_ENC_PIC) | (1 << INT_WAVE5_ENC_LOW_LATENCY))) {
  630. u32 ll_intr_reason = (1 << INT_WAVE5_ENC_PIC);
  631. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &ll_intr_reason, sizeof(u32), &s_kfifo_lock);
  632. }
  633. else
  634. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason, sizeof(u32), &s_kfifo_lock);
  635. }
  636. else {
  637. printk(KERN_ERR "[VPUDRV] : kfifo_is_full kfifo_count=%d \n", kfifo_len(&s_interrupt_pending_q[intr_inst_index]));
  638. }
  639. }
  640. else {
  641. printk(KERN_ERR "[VPUDRV] : intr_inst_index is wrong intr_inst_index=%d \n", intr_inst_index);
  642. }
  643. }
  644. if (0 != reason)
  645. printk(KERN_ERR "INTERRUPT REASON REMAINED: %08x\n", reason);
  646. WriteVpuRegister(W5_VPU_INT_REASON_CLEAR, reason_clr);
  647. #else
  648. dev->interrupt_reason = ReadVpuRegister(W5_VPU_INT_REASON);
  649. WriteVpuRegister(W5_VPU_INT_REASON_CLEAR, dev->interrupt_reason);
  650. #endif
  651. WriteVpuRegister(W5_VPU_VINT_CLEAR, 0x1);
  652. }
  653. }
  654. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  655. if (ReadVpuRegister(BIT_INT_STS)) {
  656. #ifdef SUPPORT_MULTI_INST_INTR
  657. intr_reason = ReadVpuRegister(BIT_INT_REASON);
  658. intr_inst_index = 0; // in case of coda seriese. treats intr_inst_index is already 0
  659. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason, sizeof(u32), &s_kfifo_lock);
  660. #else
  661. dev->interrupt_reason = ReadVpuRegister(BIT_INT_REASON);
  662. #endif
  663. WriteVpuRegister(BIT_INT_CLEAR, 0x1);
  664. }
  665. }
  666. else {
  667. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  668. continue;
  669. }
  670. #ifdef SUPPORT_MULTI_INST_INTR
  671. DPRINTK("[VPUDRV] product: 0x%08x intr_reason: 0x%08x\n\n", product_code, intr_reason);
  672. #else
  673. DPRINTK("[VPUDRV] product: 0x%08x intr_reason: 0x%08x\n", product_code, dev->interrupt_reason);
  674. #endif
  675. }
  676. if (dev->async_queue)
  677. kill_fasync(&dev->async_queue, SIGIO, POLL_IN); /* notify the interrupt to user space */
  678. #ifdef SUPPORT_MULTI_INST_INTR
  679. if (intr_inst_index >= 0 && intr_inst_index < MAX_NUM_INSTANCE) {
  680. s_interrupt_flag[intr_inst_index]= 1;
  681. wake_up_interruptible(&s_interrupt_wait_q[intr_inst_index]);
  682. }
  683. #else
  684. s_interrupt_flag = 1;
  685. wake_up_interruptible(&s_interrupt_wait_q);
  686. #endif
  687. DPRINTK("[VPUDRV][-]%s\n", __func__);
  688. return IRQ_HANDLED;
  689. }
  690. static int vpu_open(struct inode *inode, struct file *filp)
  691. {
  692. DPRINTK("[VPUDRV][+] %s\n", __func__);
  693. vpu_clk_enable(s_vpu_clk);
  694. reset_control_deassert(s_vpu_clk->resets);
  695. spin_lock(&s_vpu_lock);
  696. s_vpu_drv_context.open_count++;
  697. filp->private_data = (void *)(&s_vpu_drv_context);
  698. spin_unlock(&s_vpu_lock);
  699. DPRINTK("[VPUDRV][-] %s\n", __func__);
  700. return 0;
  701. }
  702. /*static int vpu_ioctl(struct inode *inode, struct file *filp, u_int cmd, u_long arg) // for kernel 2.6.9 of C&M*/
  703. static long vpu_ioctl(struct file *filp, u_int cmd, u_long arg)
  704. {
  705. int ret = 0;
  706. struct vpu_drv_context_t *dev = (struct vpu_drv_context_t *)filp->private_data;
  707. switch (cmd) {
  708. case VDI_IOCTL_GET_PHYSICAL_MEMORY:
  709. {
  710. vpudrv_buffer_pool_t *vbp = NULL;
  711. void *user_address = NULL;
  712. struct task_struct *my_struct = NULL;
  713. struct mm_struct *mm = NULL;
  714. unsigned long address = 0;
  715. pgd_t *pgd = NULL;
  716. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  717. vbp = kzalloc(sizeof(*vbp), GFP_KERNEL);
  718. if (!vbp) {
  719. up(&s_vpu_sem);
  720. return -ENOMEM;
  721. }
  722. ret = copy_from_user(&(vbp->vb), (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  723. if (ret) {
  724. kfree(vbp);
  725. up(&s_vpu_sem);
  726. return -EFAULT;
  727. }
  728. user_address = (void *)vbp->vb.virt_addr;
  729. my_struct = get_current();
  730. mm = my_struct->mm;
  731. address = (unsigned long)user_address;
  732. pgd = pgd_offset(mm, address);
  733. if (!pgd_none(*pgd) && !pgd_bad(*pgd)) {
  734. p4d_t *p4d = p4d_offset(pgd, address);
  735. pud_t *pud = pud_offset(p4d, address);
  736. if (!pud_none(*pud) && !pud_bad(*pud)) {
  737. pmd_t *pmd = pmd_offset(pud, address);
  738. if (!pmd_none(*pmd) && !pmd_bad(*pmd)) {
  739. pte_t *pte = pte_offset_map(pmd, address);
  740. if (!pte_none(*pte)) {
  741. struct page *pg = pte_page(*pte);
  742. unsigned long phys = page_to_phys(pg);
  743. unsigned long virt = (unsigned long)phys_to_virt(phys);
  744. printk("attach phy address = %lx, virt = %lx\r\n", phys, virt);
  745. vbp->vb.phys_addr = phys;
  746. vbp->vb.base = virt;
  747. }
  748. pte_unmap(pte);
  749. }
  750. }
  751. }
  752. ret = copy_to_user((void __user *)arg, &(vbp->vb), sizeof(vpudrv_buffer_t));
  753. if (ret) {
  754. kfree(vbp);
  755. ret = -EFAULT;
  756. up(&s_vpu_sem);
  757. break;
  758. }
  759. vbp->filp = filp;
  760. spin_lock(&s_vpu_lock);
  761. list_add(&vbp->list, &s_vbp_head);
  762. spin_unlock(&s_vpu_lock);
  763. up(&s_vpu_sem);
  764. }
  765. }
  766. break;
  767. case VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY:
  768. {
  769. vpudrv_buffer_pool_t *vbp;
  770. DPRINTK("[VPUDRV][+]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  771. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  772. vbp = kzalloc(sizeof(*vbp), GFP_KERNEL);
  773. if (!vbp) {
  774. up(&s_vpu_sem);
  775. return -ENOMEM;
  776. }
  777. ret = copy_from_user(&(vbp->vb), (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  778. if (ret) {
  779. kfree(vbp);
  780. up(&s_vpu_sem);
  781. return -EFAULT;
  782. }
  783. ret = vpu_alloc_dma_buffer(&(vbp->vb));
  784. if (ret == -1) {
  785. ret = -ENOMEM;
  786. kfree(vbp);
  787. up(&s_vpu_sem);
  788. break;
  789. }
  790. ret = copy_to_user((void __user *)arg, &(vbp->vb), sizeof(vpudrv_buffer_t));
  791. if (ret) {
  792. kfree(vbp);
  793. ret = -EFAULT;
  794. up(&s_vpu_sem);
  795. break;
  796. }
  797. vbp->filp = filp;
  798. spin_lock(&s_vpu_lock);
  799. list_add(&vbp->list, &s_vbp_head);
  800. spin_unlock(&s_vpu_lock);
  801. up(&s_vpu_sem);
  802. }
  803. DPRINTK("[VPUDRV][-]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  804. }
  805. break;
  806. case VDI_IOCTL_FREE_PHYSICALMEMORY:
  807. {
  808. vpudrv_buffer_pool_t *vbp, *n;
  809. vpudrv_buffer_t vb;
  810. DPRINTK("[VPUDRV][+]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  811. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  812. ret = copy_from_user(&vb, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  813. if (ret) {
  814. up(&s_vpu_sem);
  815. return -EACCES;
  816. }
  817. if (vb.base)
  818. vpu_free_dma_buffer(&vb);
  819. spin_lock(&s_vpu_lock);
  820. list_for_each_entry_safe(vbp, n, &s_vbp_head, list)
  821. {
  822. if (vbp->vb.base == vb.base) {
  823. list_del(&vbp->list);
  824. kfree(vbp);
  825. break;
  826. }
  827. }
  828. spin_unlock(&s_vpu_lock);
  829. up(&s_vpu_sem);
  830. }
  831. DPRINTK("[VPUDRV][-]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  832. }
  833. break;
  834. case VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO:
  835. {
  836. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  837. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO\n");
  838. if (s_video_memory.base != 0) {
  839. ret = copy_to_user((void __user *)arg, &s_video_memory, sizeof(vpudrv_buffer_t));
  840. if (ret != 0)
  841. ret = -EFAULT;
  842. } else {
  843. ret = -EFAULT;
  844. }
  845. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO\n");
  846. #endif
  847. }
  848. break;
  849. case VDI_IOCTL_WAIT_INTERRUPT:
  850. {
  851. vpudrv_intr_info_t info;
  852. #ifdef SUPPORT_MULTI_INST_INTR
  853. u32 intr_inst_index;
  854. u32 intr_reason_in_q;
  855. u32 interrupt_flag_in_q;
  856. #endif
  857. DPRINTK("[VPUDRV][+]VDI_IOCTL_WAIT_INTERRUPT\n");
  858. ret = copy_from_user(&info, (vpudrv_intr_info_t *)arg, sizeof(vpudrv_intr_info_t));
  859. if (ret != 0)
  860. {
  861. return -EFAULT;
  862. }
  863. #ifdef SUPPORT_MULTI_INST_INTR
  864. intr_inst_index = info.intr_inst_index;
  865. intr_reason_in_q = 0;
  866. interrupt_flag_in_q = kfifo_out_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason_in_q, sizeof(u32), &s_kfifo_lock);
  867. if (interrupt_flag_in_q > 0)
  868. {
  869. dev->interrupt_reason[intr_inst_index] = intr_reason_in_q;
  870. DPRINTK("[VPUDRV] Interrupt Remain : intr_inst_index=%d, intr_reason_in_q=0x%x, interrupt_flag_in_q=%d\n", intr_inst_index, intr_reason_in_q, interrupt_flag_in_q);
  871. goto INTERRUPT_REMAIN_IN_QUEUE;
  872. }
  873. #endif
  874. #ifdef SUPPORT_MULTI_INST_INTR
  875. #ifdef SUPPORT_TIMEOUT_RESOLUTION
  876. kt = ktime_set(0, info.timeout*1000*1000);
  877. ret = wait_event_interruptible_hrtimeout(s_interrupt_wait_q[intr_inst_index], s_interrupt_flag[intr_inst_index] != 0, kt);
  878. #else
  879. ret = wait_event_interruptible_timeout(s_interrupt_wait_q[intr_inst_index], s_interrupt_flag[intr_inst_index] != 0, msecs_to_jiffies(info.timeout));
  880. #endif
  881. #else
  882. ret = wait_event_interruptible_timeout(s_interrupt_wait_q, s_interrupt_flag != 0, msecs_to_jiffies(info.timeout));
  883. #endif
  884. #ifdef SUPPORT_TIMEOUT_RESOLUTION
  885. if (ret == -ETIME) {
  886. //DPRINTK("[VPUDRV][-]VDI_IOCTL_WAIT_INTERRUPT timeout = %d \n", info.timeout);
  887. break;
  888. }
  889. #endif
  890. if (!ret) {
  891. ret = -ETIME;
  892. break;
  893. }
  894. if (signal_pending(current)) {
  895. ret = -ERESTARTSYS;
  896. break;
  897. }
  898. #ifdef SUPPORT_MULTI_INST_INTR
  899. intr_reason_in_q = 0;
  900. interrupt_flag_in_q = kfifo_out_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason_in_q, sizeof(u32), &s_kfifo_lock);
  901. if (interrupt_flag_in_q > 0) {
  902. dev->interrupt_reason[intr_inst_index] = intr_reason_in_q;
  903. }
  904. else {
  905. dev->interrupt_reason[intr_inst_index] = 0;
  906. }
  907. #endif
  908. #ifdef SUPPORT_MULTI_INST_INTR
  909. DPRINTK("[VPUDRV] inst_index(%d), s_interrupt_flag(%d), reason(0x%08lx)\n", intr_inst_index, s_interrupt_flag[intr_inst_index], dev->interrupt_reason[intr_inst_index]);
  910. #else
  911. DPRINTK("[VPUDRV] s_interrupt_flag(%d), reason(0x%08lx)\n", s_interrupt_flag, dev->interrupt_reason);
  912. #endif
  913. #ifdef SUPPORT_MULTI_INST_INTR
  914. INTERRUPT_REMAIN_IN_QUEUE:
  915. info.intr_reason = dev->interrupt_reason[intr_inst_index];
  916. s_interrupt_flag[intr_inst_index] = 0;
  917. dev->interrupt_reason[intr_inst_index] = 0;
  918. #else
  919. info.intr_reason = dev->interrupt_reason;
  920. s_interrupt_flag = 0;
  921. dev->interrupt_reason = 0;
  922. #endif
  923. #ifdef VPU_IRQ_CONTROL
  924. enable_irq(s_vpu_irq);
  925. #endif
  926. ret = copy_to_user((void __user *)arg, &info, sizeof(vpudrv_intr_info_t));
  927. DPRINTK("[VPUDRV][-]VDI_IOCTL_WAIT_INTERRUPT\n");
  928. if (ret != 0)
  929. {
  930. return -EFAULT;
  931. }
  932. }
  933. break;
  934. case VDI_IOCTL_SET_CLOCK_GATE:
  935. {
  936. u32 clkgate;
  937. DPRINTK("[VPUDRV][+]VDI_IOCTL_SET_CLOCK_GATE\n");
  938. if (get_user(clkgate, (u32 __user *) arg))
  939. return -EFAULT;
  940. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  941. if (clkgate)
  942. vpu_clk_enable(s_vpu_clk);
  943. else
  944. vpu_clk_disable(s_vpu_clk);
  945. #endif
  946. DPRINTK("[VPUDRV][-]VDI_IOCTL_SET_CLOCK_GATE\n");
  947. }
  948. break;
  949. case VDI_IOCTL_GET_INSTANCE_POOL:
  950. {
  951. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_INSTANCE_POOL\n");
  952. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  953. if (s_instance_pool.base != 0) {
  954. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(vpudrv_buffer_t));
  955. if (ret != 0)
  956. ret = -EFAULT;
  957. } else {
  958. ret = copy_from_user(&s_instance_pool, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  959. if (ret == 0) {
  960. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  961. s_instance_pool.size = PAGE_ALIGN(s_instance_pool.size);
  962. s_instance_pool.base = (unsigned long)vmalloc(s_instance_pool.size);
  963. s_instance_pool.phys_addr = s_instance_pool.base;
  964. if (s_instance_pool.base != 0)
  965. #else
  966. if (vpu_alloc_dma_buffer(&s_instance_pool) != -1)
  967. #endif
  968. {
  969. memset((void *)s_instance_pool.base, 0x0, s_instance_pool.size); /*clearing memory*/
  970. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(vpudrv_buffer_t));
  971. if (ret == 0) {
  972. /* success to get memory for instance pool */
  973. up(&s_vpu_sem);
  974. break;
  975. }
  976. }
  977. }
  978. ret = -EFAULT;
  979. }
  980. up(&s_vpu_sem);
  981. }
  982. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_INSTANCE_POOL\n");
  983. }
  984. break;
  985. case VDI_IOCTL_GET_COMMON_MEMORY:
  986. {
  987. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_COMMON_MEMORY\n");
  988. if (s_common_memory.base != 0) {
  989. ret = copy_to_user((void __user *)arg, &s_common_memory, sizeof(vpudrv_buffer_t));
  990. if (ret != 0)
  991. ret = -EFAULT;
  992. } else {
  993. ret = copy_from_user(&s_common_memory, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  994. if (ret == 0) {
  995. if (vpu_alloc_dma_buffer(&s_common_memory) != -1) {
  996. ret = copy_to_user((void __user *)arg, &s_common_memory, sizeof(vpudrv_buffer_t));
  997. if (ret == 0) {
  998. /* success to get memory for common memory */
  999. break;
  1000. }
  1001. }
  1002. }
  1003. ret = -EFAULT;
  1004. }
  1005. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_COMMON_MEMORY\n");
  1006. }
  1007. break;
  1008. case VDI_IOCTL_OPEN_INSTANCE:
  1009. {
  1010. vpudrv_inst_info_t inst_info;
  1011. vpudrv_instanace_list_t *vil, *n;
  1012. vil = kzalloc(sizeof(*vil), GFP_KERNEL);
  1013. if (!vil)
  1014. return -ENOMEM;
  1015. if (copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t)))
  1016. return -EFAULT;
  1017. vil->inst_idx = inst_info.inst_idx;
  1018. vil->core_idx = inst_info.core_idx;
  1019. vil->filp = filp;
  1020. spin_lock(&s_vpu_lock);
  1021. list_add(&vil->list, &s_inst_list_head);
  1022. inst_info.inst_open_count = 0; /* counting the current open instance number */
  1023. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  1024. {
  1025. if (vil->core_idx == inst_info.core_idx)
  1026. inst_info.inst_open_count++;
  1027. }
  1028. #ifdef SUPPORT_MULTI_INST_INTR
  1029. kfifo_reset(&s_interrupt_pending_q[inst_info.inst_idx]);
  1030. #endif
  1031. spin_unlock(&s_vpu_lock);
  1032. s_vpu_open_ref_count++; /* flag just for that vpu is in opened or closed */
  1033. if (copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t))) {
  1034. kfree(vil);
  1035. return -EFAULT;
  1036. }
  1037. DPRINTK("[VPUDRV] VDI_IOCTL_OPEN_INSTANCE core_idx=%d, inst_idx=%d, s_vpu_open_ref_count=%d, inst_open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, s_vpu_open_ref_count, inst_info.inst_open_count);
  1038. }
  1039. break;
  1040. case VDI_IOCTL_CLOSE_INSTANCE:
  1041. {
  1042. vpudrv_inst_info_t inst_info;
  1043. vpudrv_instanace_list_t *vil, *n;
  1044. u32 found = 0;
  1045. DPRINTK("[VPUDRV][+]VDI_IOCTL_CLOSE_INSTANCE\n");
  1046. if (copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t)))
  1047. return -EFAULT;
  1048. spin_lock(&s_vpu_lock);
  1049. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  1050. {
  1051. if (vil->inst_idx == inst_info.inst_idx && vil->core_idx == inst_info.core_idx) {
  1052. list_del(&vil->list);
  1053. kfree(vil);
  1054. found = 1;
  1055. break;
  1056. }
  1057. }
  1058. if (0 == found) {
  1059. spin_unlock(&s_vpu_lock);
  1060. return -EINVAL;
  1061. }
  1062. inst_info.inst_open_count = 0; /* counting the current open instance number */
  1063. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  1064. {
  1065. if (vil->core_idx == inst_info.core_idx)
  1066. inst_info.inst_open_count++;
  1067. }
  1068. #ifdef SUPPORT_MULTI_INST_INTR
  1069. kfifo_reset(&s_interrupt_pending_q[inst_info.inst_idx]);
  1070. #endif
  1071. spin_unlock(&s_vpu_lock);
  1072. s_vpu_open_ref_count--; /* flag just for that vpu is in opened or closed */
  1073. if (copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t)))
  1074. return -EFAULT;
  1075. DPRINTK("[VPUDRV] VDI_IOCTL_CLOSE_INSTANCE core_idx=%d, inst_idx=%d, s_vpu_open_ref_count=%d, inst_open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, s_vpu_open_ref_count, inst_info.inst_open_count);
  1076. }
  1077. break;
  1078. case VDI_IOCTL_GET_INSTANCE_NUM:
  1079. {
  1080. vpudrv_inst_info_t inst_info;
  1081. vpudrv_instanace_list_t *vil, *n;
  1082. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_INSTANCE_NUM\n");
  1083. ret = copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t));
  1084. if (ret != 0)
  1085. break;
  1086. spin_lock(&s_vpu_lock);
  1087. inst_info.inst_open_count = 0;
  1088. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  1089. {
  1090. if (vil->core_idx == inst_info.core_idx)
  1091. inst_info.inst_open_count++;
  1092. }
  1093. spin_unlock(&s_vpu_lock);
  1094. ret = copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t));
  1095. DPRINTK("[VPUDRV] VDI_IOCTL_GET_INSTANCE_NUM core_idx=%d, inst_idx=%d, open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, inst_info.inst_open_count);
  1096. }
  1097. break;
  1098. case VDI_IOCTL_RESET:
  1099. {
  1100. vpu_hw_reset();
  1101. }
  1102. break;
  1103. case VDI_IOCTL_GET_REGISTER_INFO:
  1104. {
  1105. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_REGISTER_INFO\n");
  1106. ret = copy_to_user((void __user *)arg, &s_vpu_register, sizeof(vpudrv_buffer_t));
  1107. if (ret != 0)
  1108. ret = -EFAULT;
  1109. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_REGISTER_INFO s_vpu_register.phys_addr==0x%lx, s_vpu_register.virt_addr=0x%lx, s_vpu_register.size=%d\n", s_vpu_register.phys_addr , s_vpu_register.virt_addr, s_vpu_register.size);
  1110. }
  1111. break;
  1112. case VDI_IOCTL_FLUSH_DCACHE:
  1113. {
  1114. vpudrv_flush_cache_t cache_info;
  1115. ret = copy_from_user(&cache_info, (vpudrv_flush_cache_t *)arg, sizeof(vpudrv_flush_cache_t));
  1116. if (ret != 0)
  1117. ret = -EFAULT;
  1118. if(cache_info.flag)
  1119. starfive_flush_dcache(cache_info.start,cache_info.size);
  1120. }
  1121. break;
  1122. case VDI_IOCTL_CPUFREQ_SAVEENV:
  1123. {
  1124. #ifdef CONFIG_CPU_FREQ
  1125. vpu_freq_save_env();
  1126. #endif
  1127. }
  1128. break;
  1129. case VDI_IOCTL_CPUFREQ_PUTENV:
  1130. {
  1131. #ifdef CONFIG_CPU_FREQ
  1132. vpu_freq_put_env();
  1133. #endif
  1134. }
  1135. break;
  1136. default:
  1137. {
  1138. printk(KERN_ERR "[VPUDRV] No such IOCTL, cmd is %d\n", cmd);
  1139. }
  1140. break;
  1141. }
  1142. return ret;
  1143. }
  1144. static ssize_t vpu_read(struct file *filp, char __user *buf, size_t len, loff_t *ppos)
  1145. {
  1146. return -1;
  1147. }
  1148. static ssize_t vpu_write(struct file *filp, const char __user *buf, size_t len, loff_t *ppos)
  1149. {
  1150. /* DPRINTK("[VPUDRV] vpu_write len=%d\n", (int)len); */
  1151. if (!buf) {
  1152. printk(KERN_ERR "[VPUDRV] vpu_write buf = NULL error \n");
  1153. return -EFAULT;
  1154. }
  1155. if (len == sizeof(vpu_bit_firmware_info_t)) {
  1156. vpu_bit_firmware_info_t *bit_firmware_info;
  1157. bit_firmware_info = kmalloc(sizeof(vpu_bit_firmware_info_t), GFP_KERNEL);
  1158. if (!bit_firmware_info) {
  1159. printk(KERN_ERR "[VPUDRV] vpu_write bit_firmware_info allocation error \n");
  1160. return -EFAULT;
  1161. }
  1162. if (copy_from_user(bit_firmware_info, buf, len)) {
  1163. printk(KERN_ERR "[VPUDRV] vpu_write copy_from_user error for bit_firmware_info\n");
  1164. return -EFAULT;
  1165. }
  1166. if (bit_firmware_info->size == sizeof(vpu_bit_firmware_info_t)) {
  1167. DPRINTK("[VPUDRV] vpu_write set bit_firmware_info coreIdx=0x%x, reg_base_offset=0x%x size=0x%x, bit_code[0]=0x%x\n",
  1168. bit_firmware_info->core_idx, (int)bit_firmware_info->reg_base_offset, bit_firmware_info->size, bit_firmware_info->bit_code[0]);
  1169. if (bit_firmware_info->core_idx > MAX_NUM_VPU_CORE) {
  1170. printk(KERN_ERR "[VPUDRV] vpu_write coreIdx[%d] is exceeded than MAX_NUM_VPU_CORE[%d]\n", bit_firmware_info->core_idx, MAX_NUM_VPU_CORE);
  1171. return -ENODEV;
  1172. }
  1173. memcpy((void *)&s_bit_firmware_info[bit_firmware_info->core_idx], bit_firmware_info, sizeof(vpu_bit_firmware_info_t));
  1174. kfree(bit_firmware_info);
  1175. return len;
  1176. }
  1177. kfree(bit_firmware_info);
  1178. }
  1179. return -1;
  1180. }
  1181. static int vpu_release(struct inode *inode, struct file *filp)
  1182. {
  1183. int ret = 0;
  1184. u32 open_count;
  1185. #ifdef SUPPORT_MULTI_INST_INTR
  1186. int i;
  1187. #endif
  1188. DPRINTK("[VPUDRV] vpu_release\n");
  1189. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  1190. /* found and free the not handled buffer by user applications */
  1191. vpu_free_buffers(filp);
  1192. /* found and free the not closed instance by user applications */
  1193. vpu_free_instances(filp);
  1194. spin_lock(&s_vpu_lock);
  1195. s_vpu_drv_context.open_count--;
  1196. open_count = s_vpu_drv_context.open_count;
  1197. spin_unlock(&s_vpu_lock);
  1198. if (open_count == 0) {
  1199. #ifdef SUPPORT_MULTI_INST_INTR
  1200. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1201. kfifo_reset(&s_interrupt_pending_q[i]);
  1202. }
  1203. #endif
  1204. if (s_instance_pool.base) {
  1205. DPRINTK("[VPUDRV] free instance pool\n");
  1206. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1207. vfree((const void *)s_instance_pool.base);
  1208. #else
  1209. vpu_free_dma_buffer(&s_instance_pool);
  1210. #endif
  1211. s_instance_pool.base = 0;
  1212. }
  1213. }
  1214. }
  1215. up(&s_vpu_sem);
  1216. reset_control_assert(s_vpu_clk->resets);
  1217. vpu_clk_disable(s_vpu_clk);
  1218. return 0;
  1219. }
  1220. static int vpu_fasync(int fd, struct file *filp, int mode)
  1221. {
  1222. struct vpu_drv_context_t *dev = (struct vpu_drv_context_t *)filp->private_data;
  1223. return fasync_helper(fd, filp, mode, &dev->async_queue);
  1224. }
  1225. static int vpu_map_to_register(struct file *fp, struct vm_area_struct *vm)
  1226. {
  1227. unsigned long pfn;
  1228. vm->vm_flags |= VM_IO | VM_RESERVED;
  1229. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  1230. pfn = s_vpu_register.phys_addr >> PAGE_SHIFT;
  1231. return remap_pfn_range(vm, vm->vm_start, pfn, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1232. }
  1233. static int vpu_map_to_physical_memory(struct file *fp, struct vm_area_struct *vm)
  1234. {
  1235. vm->vm_flags |= VM_IO | VM_RESERVED;
  1236. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  1237. return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1238. }
  1239. static int vpu_map_to_instance_pool_memory(struct file *fp, struct vm_area_struct *vm)
  1240. {
  1241. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1242. int ret;
  1243. long length = vm->vm_end - vm->vm_start;
  1244. unsigned long start = vm->vm_start;
  1245. char *vmalloc_area_ptr = (char *)s_instance_pool.base;
  1246. unsigned long pfn;
  1247. vm->vm_flags |= VM_RESERVED;
  1248. /* loop over all pages, map it page individually */
  1249. while (length > 0)
  1250. {
  1251. pfn = vmalloc_to_pfn(vmalloc_area_ptr);
  1252. if ((ret = remap_pfn_range(vm, start, pfn, PAGE_SIZE, PAGE_SHARED)) < 0) {
  1253. return ret;
  1254. }
  1255. start += PAGE_SIZE;
  1256. vmalloc_area_ptr += PAGE_SIZE;
  1257. length -= PAGE_SIZE;
  1258. }
  1259. return 0;
  1260. #else
  1261. vm->vm_flags |= VM_RESERVED;
  1262. return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1263. #endif
  1264. }
  1265. /*!
  1266. * @brief memory map interface for vpu file operation
  1267. * @return 0 on success or negative error code on error
  1268. */
  1269. static int vpu_mmap(struct file *fp, struct vm_area_struct *vm)
  1270. {
  1271. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1272. if (vm->vm_pgoff == 0)
  1273. return vpu_map_to_instance_pool_memory(fp, vm);
  1274. if (vm->vm_pgoff == (s_vpu_register.phys_addr>>PAGE_SHIFT))
  1275. return vpu_map_to_register(fp, vm);
  1276. return vpu_map_to_physical_memory(fp, vm);
  1277. #else
  1278. if (vm->vm_pgoff) {
  1279. if (vm->vm_pgoff == (s_instance_pool.phys_addr>>PAGE_SHIFT))
  1280. return vpu_map_to_instance_pool_memory(fp, vm);
  1281. return vpu_map_to_physical_memory(fp, vm);
  1282. } else {
  1283. return vpu_map_to_register(fp, vm);
  1284. }
  1285. #endif
  1286. }
  1287. struct file_operations vpu_fops = {
  1288. .owner = THIS_MODULE,
  1289. .open = vpu_open,
  1290. .read = vpu_read,
  1291. .write = vpu_write,
  1292. /*.ioctl = vpu_ioctl, // for kernel 2.6.9 of C&M*/
  1293. .unlocked_ioctl = vpu_ioctl,
  1294. .release = vpu_release,
  1295. .fasync = vpu_fasync,
  1296. .mmap = vpu_mmap,
  1297. };
  1298. static int vpu_probe(struct platform_device *pdev)
  1299. {
  1300. int err = 0;
  1301. struct resource *res = NULL;
  1302. struct device *devices;
  1303. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1304. struct resource res_cma;
  1305. struct device_node *node;
  1306. #endif
  1307. DPRINTK("[VPUDRV] vpu_probe\n");
  1308. if(pdev){
  1309. vpu_dev = &pdev->dev;
  1310. vpu_dev->coherent_dma_mask = 0xffffffff;;
  1311. dev_info(vpu_dev,"device init.\n");
  1312. }
  1313. if (pdev)
  1314. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1315. if (res) {/* if platform driver is implemented */
  1316. s_vpu_register.phys_addr = res->start;
  1317. s_vpu_register.virt_addr = (unsigned long)ioremap_nocache(res->start, res->end - res->start);
  1318. s_vpu_register.size = res->end - res->start;
  1319. DPRINTK("[VPUDRV] : vpu base address get from platform driver physical base addr==0x%lx, virtual base=0x%lx\n", s_vpu_register.phys_addr , s_vpu_register.virt_addr);
  1320. } else {
  1321. s_vpu_register.phys_addr = VPU_REG_BASE_ADDR;
  1322. s_vpu_register.virt_addr = (unsigned long)ioremap_nocache(s_vpu_register.phys_addr, VPU_REG_SIZE);
  1323. s_vpu_register.size = VPU_REG_SIZE;
  1324. DPRINTK("[VPUDRV] : vpu base address get from defined value physical base addr==0x%lx, virtual base=0x%lx\n", s_vpu_register.phys_addr, s_vpu_register.virt_addr);
  1325. }
  1326. /* get the major number of the character device */
  1327. if ((alloc_chrdev_region(&s_vpu_devt, 0, 1, VPU_DEV_NAME)) < 0) {
  1328. err = -EBUSY;
  1329. printk(KERN_ERR "could not allocate major number\n");
  1330. goto ERROR_PROVE_DEVICE;
  1331. }
  1332. printk(KERN_INFO "SUCCESS alloc_chrdev_region\n");
  1333. s_vpu_major = MAJOR(s_vpu_devt);
  1334. /* initialize the device structure and register the device with the kernel */
  1335. cdev_init(&s_vpu_cdev, &vpu_fops);
  1336. if ((cdev_add(&s_vpu_cdev, s_vpu_devt, 1)) < 0) {
  1337. err = -EBUSY;
  1338. printk(KERN_ERR "could not allocate chrdev\n");
  1339. goto ERROR_PROVE_DEVICE;
  1340. }
  1341. s_vpu_class = class_create(THIS_MODULE, VPU_DEV_NAME);
  1342. if (IS_ERR(s_vpu_class)) {
  1343. dev_err(vpu_dev, "class creat error.\n");
  1344. goto ERROR_CRART_CLASS;
  1345. }
  1346. devices = device_create(s_vpu_class, 0, MKDEV(s_vpu_major, 0),
  1347. NULL, VPU_DEV_NAME);
  1348. if (IS_ERR(devices)) {
  1349. dev_err(vpu_dev, "device creat error.\n");
  1350. goto ERROR_CREAT_DEVICE;
  1351. }
  1352. if (pdev)
  1353. s_vpu_clk = vpu_clk_get(pdev);
  1354. else
  1355. s_vpu_clk = vpu_clk_get(NULL);
  1356. if (!s_vpu_clk)
  1357. printk(KERN_ERR "[VPUDRV] : not support clock controller.\n");
  1358. else
  1359. DPRINTK("[VPUDRV] : get clock controller s_vpu_clk=%p\n", s_vpu_clk);
  1360. #ifdef CONFIG_CPU_FREQ
  1361. vpu_freq_init(&pdev->dev);
  1362. #endif
  1363. vpu_pmu_enable(s_vpu_clk->dev);
  1364. #ifdef VPU_SUPPORT_ISR
  1365. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1366. if (pdev)
  1367. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1368. if (res) {/* if platform driver is implemented */
  1369. s_vpu_irq = res->start;
  1370. DPRINTK("[VPUDRV] : vpu irq number get from platform driver irq=0x%x\n", s_vpu_irq);
  1371. } else {
  1372. DPRINTK("[VPUDRV] : vpu irq number get from defined value irq=0x%x\n", s_vpu_irq);
  1373. }
  1374. #else
  1375. DPRINTK("[VPUDRV] : vpu irq number get from defined value irq=0x%x\n", s_vpu_irq);
  1376. #endif
  1377. err = request_irq(s_vpu_irq, vpu_irq_handler, 0, pdev->name, (void *)(&s_vpu_drv_context));
  1378. if (err) {
  1379. printk(KERN_ERR "[VPUDRV] : fail to register interrupt handler\n");
  1380. goto ERROR_PROVE_DEVICE;
  1381. }
  1382. #endif
  1383. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1384. node = of_parse_phandle(vpu_dev->of_node, "memory-region", 0);
  1385. if(node){
  1386. dev_info(vpu_dev, "Get mem form memory-region\n");
  1387. of_address_to_resource(node, 0, &res_cma);
  1388. s_video_memory.size = resource_size(&res_cma);
  1389. s_video_memory.phys_addr = res_cma.start;
  1390. }else{
  1391. dev_info(vpu_dev, "Get mem form memory-region fiiled.please check the dts file.\n");
  1392. return 0;
  1393. }
  1394. s_video_memory.base = (unsigned long)ioremap_nocache(DRAM_MEM2SYS(s_video_memory.phys_addr), PAGE_ALIGN(s_video_memory.size));
  1395. if (!s_video_memory.base) {
  1396. printk(KERN_ERR "[VPUDRV] : fail to remap video memory physical phys_addr=0x%lx, base=0x%lx, size=%d\n", s_video_memory.phys_addr, s_video_memory.base, (int)s_video_memory.size);
  1397. goto ERROR_PROVE_DEVICE;
  1398. }
  1399. if (vmem_init(&s_vmem, s_video_memory.phys_addr, s_video_memory.size) < 0) {
  1400. printk(KERN_ERR "[VPUDRV] : fail to init vmem system\n");
  1401. goto ERROR_PROVE_DEVICE;
  1402. }
  1403. DPRINTK("[VPUDRV] success to probe vpu device with reserved video memory phys_addr=0x%lx, base=0x%lx, size=%d\n", s_video_memory.phys_addr, s_video_memory.base,s_video_memory.size);
  1404. #else
  1405. DPRINTK("[VPUDRV] success to probe vpu device with non reserved video memory\n");
  1406. #endif
  1407. return 0;
  1408. ERROR_CREAT_DEVICE:
  1409. class_destroy(s_vpu_class);
  1410. ERROR_CRART_CLASS:
  1411. cdev_del(&s_vpu_cdev);
  1412. ERROR_PROVE_DEVICE:
  1413. if (s_vpu_major)
  1414. unregister_chrdev_region(s_vpu_major, 1);
  1415. if (s_vpu_register.virt_addr)
  1416. iounmap((void *)s_vpu_register.virt_addr);
  1417. return err;
  1418. }
  1419. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1420. static int vpu_remove(struct platform_device *pdev)
  1421. {
  1422. DPRINTK("[VPUDRV] vpu_remove\n");
  1423. if (s_instance_pool.base) {
  1424. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1425. vfree((const void *)s_instance_pool.base);
  1426. #else
  1427. vpu_free_dma_buffer(&s_instance_pool);
  1428. #endif
  1429. s_instance_pool.base = 0;
  1430. }
  1431. if (s_common_memory.base) {
  1432. vpu_free_dma_buffer(&s_common_memory);
  1433. s_common_memory.base = 0;
  1434. }
  1435. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1436. if (s_video_memory.base) {
  1437. iounmap((void *)s_video_memory.base);
  1438. s_video_memory.base = 0;
  1439. vmem_exit(&s_vmem);
  1440. }
  1441. #endif
  1442. if (s_vpu_major > 0) {
  1443. device_destroy(s_vpu_class, MKDEV(s_vpu_major, 0));
  1444. class_destroy(s_vpu_class);
  1445. cdev_del(&s_vpu_cdev);
  1446. unregister_chrdev_region(s_vpu_devt, 1);
  1447. s_vpu_major = 0;
  1448. }
  1449. #ifdef VPU_SUPPORT_ISR
  1450. if (s_vpu_irq)
  1451. free_irq(s_vpu_irq, &s_vpu_drv_context);
  1452. #endif
  1453. if (s_vpu_register.virt_addr)
  1454. iounmap((void *)s_vpu_register.virt_addr);
  1455. vpu_clk_put(s_vpu_clk);
  1456. vpu_pmu_disable(s_vpu_clk->dev);
  1457. return 0;
  1458. }
  1459. #endif /*VPU_SUPPORT_PLATFORM_DRIVER_REGISTER*/
  1460. #if defined(VPU_SUPPORT_PLATFORM_DRIVER_REGISTER) && defined(CONFIG_PM)
  1461. #define W5_MAX_CODE_BUF_SIZE (512*1024)
  1462. #define W5_CMD_INIT_VPU (0x0001)
  1463. #define W5_CMD_SLEEP_VPU (0x0004)
  1464. #define W5_CMD_WAKEUP_VPU (0x0002)
  1465. static void Wave5BitIssueCommand(int core, u32 cmd)
  1466. {
  1467. WriteVpuRegister(W5_VPU_BUSY_STATUS, 1);
  1468. WriteVpuRegister(W5_COMMAND, cmd);
  1469. WriteVpuRegister(W5_VPU_HOST_INT_REQ, 1);
  1470. return;
  1471. }
  1472. static int vpu_suspend(struct platform_device *pdev, pm_message_t state)
  1473. {
  1474. int i;
  1475. int core;
  1476. unsigned long timeout = jiffies + HZ; /* vpu wait timeout to 1sec */
  1477. int product_code;
  1478. DPRINTK("[VPUDRV] vpu_suspend\n");
  1479. vpu_clk_enable(s_vpu_clk);
  1480. if (s_vpu_open_ref_count > 0) {
  1481. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  1482. if (s_bit_firmware_info[core].size == 0)
  1483. continue;
  1484. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  1485. if (PRODUCT_CODE_W_SERIES(product_code)) {
  1486. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1487. if (time_after(jiffies, timeout)) {
  1488. DPRINTK("SLEEP_VPU BUSY timeout");
  1489. goto DONE_SUSPEND;
  1490. }
  1491. }
  1492. Wave5BitIssueCommand(core, W5_CMD_SLEEP_VPU);
  1493. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1494. if (time_after(jiffies, timeout)) {
  1495. DPRINTK("SLEEP_VPU BUSY timeout");
  1496. goto DONE_SUSPEND;
  1497. }
  1498. }
  1499. if (ReadVpuRegister(W5_RET_SUCCESS) == 0) {
  1500. DPRINTK("SLEEP_VPU failed [0x%x]", ReadVpuRegister(W5_RET_FAIL_REASON));
  1501. goto DONE_SUSPEND;
  1502. }
  1503. }
  1504. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  1505. while (ReadVpuRegister(BIT_BUSY_FLAG)) {
  1506. if (time_after(jiffies, timeout))
  1507. goto DONE_SUSPEND;
  1508. }
  1509. for (i = 0; i < 64; i++)
  1510. s_vpu_reg_store[core][i] = ReadVpuRegister(BIT_BASE+(0x100+(i * 4)));
  1511. }
  1512. else {
  1513. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  1514. goto DONE_SUSPEND;
  1515. }
  1516. }
  1517. }
  1518. vpu_clk_disable(s_vpu_clk);
  1519. return 0;
  1520. DONE_SUSPEND:
  1521. vpu_clk_disable(s_vpu_clk);
  1522. return -EAGAIN;
  1523. }
  1524. static int vpu_resume(struct platform_device *pdev)
  1525. {
  1526. int i;
  1527. int core;
  1528. u32 val;
  1529. unsigned long timeout = jiffies + HZ; /* vpu wait timeout to 1sec */
  1530. int product_code;
  1531. unsigned long code_base;
  1532. u32 code_size;
  1533. u32 remap_size;
  1534. int regVal;
  1535. u32 hwOption = 0;
  1536. DPRINTK("[VPUDRV] vpu_resume\n");
  1537. vpu_clk_enable(s_vpu_clk);
  1538. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  1539. if (s_bit_firmware_info[core].size == 0) {
  1540. continue;
  1541. }
  1542. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  1543. if (PRODUCT_CODE_W_SERIES(product_code)) {
  1544. code_base = s_common_memory.phys_addr;
  1545. /* ALIGN TO 4KB */
  1546. code_size = (W5_MAX_CODE_BUF_SIZE&~0xfff);
  1547. if (code_size < s_bit_firmware_info[core].size*2) {
  1548. goto DONE_WAKEUP;
  1549. }
  1550. regVal = 0;
  1551. WriteVpuRegister(W5_PO_CONF, regVal);
  1552. /* Reset All blocks */
  1553. regVal = 0x7ffffff;
  1554. WriteVpuRegister(W5_VPU_RESET_REQ, regVal); /*Reset All blocks*/
  1555. /* Waiting reset done */
  1556. while (ReadVpuRegister(W5_VPU_RESET_STATUS)) {
  1557. if (time_after(jiffies, timeout))
  1558. goto DONE_WAKEUP;
  1559. }
  1560. WriteVpuRegister(W5_VPU_RESET_REQ, 0);
  1561. /* remap page size */
  1562. remap_size = (code_size >> 12) & 0x1ff;
  1563. regVal = 0x80000000 | (W5_REMAP_CODE_INDEX<<12) | (0 << 16) | (1<<11) | remap_size;
  1564. WriteVpuRegister(W5_VPU_REMAP_CTRL, regVal);
  1565. WriteVpuRegister(W5_VPU_REMAP_VADDR,0x00000000); /* DO NOT CHANGE! */
  1566. WriteVpuRegister(W5_VPU_REMAP_PADDR,code_base);
  1567. WriteVpuRegister(W5_ADDR_CODE_BASE, code_base);
  1568. WriteVpuRegister(W5_CODE_SIZE, code_size);
  1569. WriteVpuRegister(W5_CODE_PARAM, 0);
  1570. WriteVpuRegister(W5_INIT_VPU_TIME_OUT_CNT, timeout);
  1571. WriteVpuRegister(W5_HW_OPTION, hwOption);
  1572. /* Interrupt */
  1573. if (product_code == WAVE521_CODE || product_code == WAVE521C_CODE ) {
  1574. regVal = (1<<INT_WAVE5_ENC_SET_PARAM);
  1575. regVal |= (1<<INT_WAVE5_ENC_PIC);
  1576. regVal |= (1<<INT_WAVE5_INIT_SEQ);
  1577. regVal |= (1<<INT_WAVE5_DEC_PIC);
  1578. regVal |= (1<<INT_WAVE5_BSBUF_EMPTY);
  1579. }
  1580. else {
  1581. // decoder
  1582. regVal = (1<<INT_WAVE5_INIT_SEQ);
  1583. regVal |= (1<<INT_WAVE5_DEC_PIC);
  1584. regVal |= (1<<INT_WAVE5_BSBUF_EMPTY);
  1585. }
  1586. WriteVpuRegister(W5_VPU_VINT_ENABLE, regVal);
  1587. Wave5BitIssueCommand(core, W5_CMD_INIT_VPU);
  1588. WriteVpuRegister(W5_VPU_REMAP_CORE_START, 1);
  1589. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1590. if (time_after(jiffies, timeout))
  1591. goto DONE_WAKEUP;
  1592. }
  1593. if (ReadVpuRegister(W5_RET_SUCCESS) == 0) {
  1594. DPRINTK("WAKEUP_VPU failed [0x%x]", ReadVpuRegister(W5_RET_FAIL_REASON));
  1595. goto DONE_WAKEUP;
  1596. }
  1597. }
  1598. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  1599. WriteVpuRegister(BIT_CODE_RUN, 0);
  1600. /*---- LOAD BOOT CODE*/
  1601. for (i = 0; i < 512; i++) {
  1602. val = s_bit_firmware_info[core].bit_code[i];
  1603. WriteVpuRegister(BIT_CODE_DOWN, ((i << 16) | val));
  1604. }
  1605. for (i = 0 ; i < 64 ; i++)
  1606. WriteVpuRegister(BIT_BASE+(0x100+(i * 4)), s_vpu_reg_store[core][i]);
  1607. WriteVpuRegister(BIT_BUSY_FLAG, 1);
  1608. WriteVpuRegister(BIT_CODE_RESET, 1);
  1609. WriteVpuRegister(BIT_CODE_RUN, 1);
  1610. while (ReadVpuRegister(BIT_BUSY_FLAG)) {
  1611. if (time_after(jiffies, timeout))
  1612. goto DONE_WAKEUP;
  1613. }
  1614. }
  1615. else {
  1616. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  1617. goto DONE_WAKEUP;
  1618. }
  1619. }
  1620. if (s_vpu_open_ref_count == 0)
  1621. vpu_clk_disable(s_vpu_clk);
  1622. DONE_WAKEUP:
  1623. if (s_vpu_open_ref_count > 0)
  1624. vpu_clk_enable(s_vpu_clk);
  1625. return 0;
  1626. }
  1627. #else
  1628. #define vpu_suspend NULL
  1629. #define vpu_resume NULL
  1630. #endif /* !CONFIG_PM */
  1631. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1632. static const struct of_device_id cm_vpu_match[] = {
  1633. {
  1634. .compatible = "c&m,cm511-vpu",
  1635. },
  1636. {
  1637. .compatible = "starfive,vdec",
  1638. },
  1639. {
  1640. /* end of table */
  1641. },
  1642. };
  1643. MODULE_DEVICE_TABLE(of, cm_vpu_match);
  1644. static struct platform_driver vpu_driver = {
  1645. .driver = {
  1646. .name = VPU_PLATFORM_DEVICE_NAME,
  1647. .of_match_table = cm_vpu_match,
  1648. },
  1649. .probe = vpu_probe,
  1650. .remove = vpu_remove,
  1651. .suspend = vpu_suspend,
  1652. .resume = vpu_resume,
  1653. };
  1654. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1655. static int __init vpu_init(void)
  1656. {
  1657. int res;
  1658. #ifdef SUPPORT_MULTI_INST_INTR
  1659. int i;
  1660. #endif
  1661. DPRINTK("[VPUDRV] begin vpu_init\n");
  1662. #ifdef SUPPORT_MULTI_INST_INTR
  1663. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1664. init_waitqueue_head(&s_interrupt_wait_q[i]);
  1665. }
  1666. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1667. #define MAX_INTERRUPT_QUEUE (16*MAX_NUM_INSTANCE)
  1668. res = kfifo_alloc(&s_interrupt_pending_q[i], MAX_INTERRUPT_QUEUE*sizeof(u32), GFP_KERNEL);
  1669. if (res) {
  1670. DPRINTK("[VPUDRV] kfifo_alloc failed 0x%x\n", res);
  1671. }
  1672. }
  1673. #else
  1674. init_waitqueue_head(&s_interrupt_wait_q);
  1675. #endif
  1676. s_common_memory.base = 0;
  1677. s_instance_pool.base = 0;
  1678. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1679. res = platform_driver_register(&vpu_driver);
  1680. #else
  1681. res = vpu_probe(NULL);
  1682. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1683. DPRINTK("[VPUDRV] end vpu_init result=0x%x\n", res);
  1684. return res;
  1685. }
  1686. static void __exit vpu_exit(void)
  1687. {
  1688. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1689. DPRINTK("[VPUDRV] vpu_exit\n");
  1690. platform_driver_unregister(&vpu_driver);
  1691. #else /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1692. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1693. #else
  1694. vpu_clk_disable(s_vpu_clk);
  1695. #endif
  1696. vpu_clk_put(s_vpu_clk);
  1697. if (s_instance_pool.base) {
  1698. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1699. vfree((const void *)s_instance_pool.base);
  1700. #else
  1701. vpu_free_dma_buffer(&s_instance_pool);
  1702. #endif
  1703. s_instance_pool.base = 0;
  1704. }
  1705. if (s_common_memory.base) {
  1706. vpu_free_dma_buffer(&s_common_memory);
  1707. s_common_memory.base = 0;
  1708. }
  1709. #ifdef CONFIG_CPU_FREQ
  1710. vpu_freq_close();
  1711. #endif
  1712. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1713. if (s_video_memory.base) {
  1714. iounmap((void *)s_video_memory.base);
  1715. s_video_memory.base = 0;
  1716. vmem_exit(&s_vmem);
  1717. }
  1718. #endif
  1719. if (s_vpu_major > 0) {
  1720. device_destroy(s_vpu_class, MKDEV(s_vpu_major, 0));
  1721. class_destroy(s_vpu_class);
  1722. cdev_del(&s_vpu_cdev);
  1723. unregister_chrdev_region(s_vpu_devt, 1);
  1724. s_vpu_major = 0;
  1725. }
  1726. #ifdef VPU_SUPPORT_ISR
  1727. if (s_vpu_irq)
  1728. free_irq(s_vpu_irq, &s_vpu_drv_context);
  1729. #endif
  1730. #ifdef SUPPORT_MULTI_INST_INTR
  1731. {
  1732. int i;
  1733. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1734. kfifo_free(&s_interrupt_pending_q[i]);
  1735. }
  1736. }
  1737. #endif
  1738. if (s_vpu_register.virt_addr) {
  1739. iounmap((void *)s_vpu_register.virt_addr);
  1740. s_vpu_register.virt_addr = 0x00;
  1741. }
  1742. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1743. return;
  1744. }
  1745. MODULE_AUTHOR("A customer using C&M VPU, Inc.");
  1746. MODULE_DESCRIPTION("VPU linux driver");
  1747. MODULE_LICENSE("GPL");
  1748. module_init(vpu_init);
  1749. module_exit(vpu_exit);
  1750. static int vpu_pmu_enable(struct device *dev)
  1751. {
  1752. int ret;
  1753. pm_runtime_enable(dev);
  1754. ret = pm_runtime_get_sync(dev);
  1755. if (ret < 0)
  1756. dev_err(dev, "failed to get pm runtime: %d\n", ret);
  1757. return ret;
  1758. }
  1759. static void vpu_pmu_disable(struct device *dev)
  1760. {
  1761. pm_runtime_put_sync(dev);
  1762. pm_runtime_disable(dev);
  1763. }
  1764. /* clk&reset for starfive jh7110*/
  1765. #ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  1766. #define CLK_ENABLE_DATA 1
  1767. #define CLK_DISABLE_DATA 0
  1768. #define CLK_EN_SHIFT 31
  1769. #define CLK_EN_MASK 0x80000000U
  1770. #define SAIF_BD_APBS_BASE 0x13020000
  1771. #define WAVE511_CLK_AXI_CTRL 0x118U
  1772. #define WAVE511_CLK_BPU_CTRL 0x11cU
  1773. #define WAVE511_CLK_VCE_CTRL 0x120U
  1774. #define WAVE511_CLK_APB_CTRL 0x124U
  1775. #define WAVE511_CLK_NOCBUS_CTRL 0x130U
  1776. #define RSTGEN_SOFTWARE_RESET_ASSERT1 0x2FCU
  1777. #define RSTGEN_SOFTWARE_RESET_STATUS1 0x30CU
  1778. #define RSTN_AXI_MASK (0x1 << 15)
  1779. #define RSTN_BPU_MASK (0x1 << 16)
  1780. #define RSTN_VCE_MASK (0x1 << 17)
  1781. #define RSTN_APB_MASK (0x1 << 18)
  1782. #define RSTN_128B_AXIMEM_MASK (0x1 << 21)
  1783. static uint32_t saif_get_reg(const volatile void __iomem *addr,
  1784. uint32_t shift, uint32_t mask)
  1785. {
  1786. u32 tmp;
  1787. tmp = readl(addr);
  1788. tmp = (tmp & mask) >> shift;
  1789. return tmp;
  1790. }
  1791. static void saif_set_reg(volatile void __iomem *addr, uint32_t data,
  1792. uint32_t shift, uint32_t mask)
  1793. {
  1794. uint32_t tmp;
  1795. tmp = readl(addr);
  1796. tmp &= ~mask;
  1797. tmp |= (data << shift) & mask;
  1798. writel(tmp, addr);
  1799. }
  1800. static void saif_assert_rst(volatile void __iomem *addr,
  1801. const volatile void __iomem *addr_status, uint32_t mask)
  1802. {
  1803. uint32_t tmp;
  1804. tmp = readl(addr);
  1805. tmp |= mask;
  1806. writel(tmp, addr);
  1807. do {
  1808. tmp = readl(addr_status);
  1809. } while ((tmp & mask) != 0);
  1810. }
  1811. static void saif_clear_rst(volatile void __iomem *addr,
  1812. const volatile void __iomem *addr_status, uint32_t mask)
  1813. {
  1814. uint32_t tmp;
  1815. tmp = readl(addr);
  1816. tmp &= ~mask;
  1817. writel(tmp, addr);
  1818. do {
  1819. tmp = readl(addr_status);
  1820. } while ((tmp & mask) != mask);
  1821. }
  1822. static void vpu_noc_vdec_bus_control(vpu_clk_t *clk, bool enable)
  1823. {
  1824. if (enable)
  1825. saif_set_reg(clk->noc_bus, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1826. else
  1827. saif_set_reg(clk->noc_bus, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1828. }
  1829. static void vpu_clk_control(vpu_clk_t *clk, bool enable)
  1830. {
  1831. if (enable) {
  1832. /*enable*/
  1833. saif_set_reg(clk->apb_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1834. saif_set_reg(clk->axi_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1835. saif_set_reg(clk->bpu_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1836. saif_set_reg(clk->vce_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1837. /*clr-reset*/
  1838. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1839. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1840. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1841. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1842. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->aximem_128b.rst_mask);
  1843. } else {
  1844. /*assert-reset*/
  1845. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1846. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1847. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1848. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1849. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->aximem_128b.rst_mask);
  1850. /*disable*/
  1851. saif_set_reg(clk->apb_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1852. saif_set_reg(clk->axi_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1853. saif_set_reg(clk->bpu_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1854. saif_set_reg(clk->vce_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1855. }
  1856. }
  1857. static void vpu_clk_reset(vpu_clk_t *clk)
  1858. {
  1859. /*assert-reset*/
  1860. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1861. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1862. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1863. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1864. /*clr-reset*/
  1865. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1866. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1867. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1868. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1869. }
  1870. int vpu_hw_reset(void)
  1871. {
  1872. if (!s_vpu_clk)
  1873. return -1;
  1874. vpu_clk_reset(s_vpu_clk);
  1875. DPRINTK("[VPUDRV] reset vpu hardware. \n");
  1876. return 0;
  1877. }
  1878. static int vpu_of_clk_get(struct platform_device *pdev, vpu_clk_t *vpu_clk)
  1879. {
  1880. if (!pdev)
  1881. return -ENXIO;
  1882. vpu_clk->clkgen = ioremap(SAIF_BD_APBS_BASE, 0x400);
  1883. if (IS_ERR(vpu_clk->clkgen)) {
  1884. dev_err(&pdev->dev, "ioremap clkgen failed.\n");
  1885. return PTR_ERR(vpu_clk->clkgen);
  1886. }
  1887. /* clkgen define */
  1888. vpu_clk->axi_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_AXI_CTRL;
  1889. vpu_clk->bpu_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_BPU_CTRL;
  1890. vpu_clk->vce_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_VCE_CTRL;
  1891. vpu_clk->apb_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_APB_CTRL;
  1892. vpu_clk->noc_bus = vpu_clk->clkgen + WAVE511_CLK_NOCBUS_CTRL;
  1893. vpu_clk->en_mask = CLK_EN_MASK;
  1894. vpu_clk->en_shift = CLK_EN_SHIFT;
  1895. /* rstgen define */
  1896. vpu_clk->rst_ctrl = vpu_clk->clkgen + RSTGEN_SOFTWARE_RESET_ASSERT1;
  1897. vpu_clk->rst_status = vpu_clk->clkgen + RSTGEN_SOFTWARE_RESET_STATUS1;
  1898. vpu_clk->axi_clk.rst_mask = RSTN_AXI_MASK;
  1899. vpu_clk->bpu_clk.rst_mask = RSTN_BPU_MASK;
  1900. vpu_clk->vce_clk.rst_mask = RSTN_VCE_MASK;
  1901. vpu_clk->apb_clk.rst_mask = RSTN_APB_MASK;
  1902. vpu_clk->aximem_128b.rst_mask = RSTN_128B_AXIMEM_MASK;
  1903. if (device_property_read_bool(&pdev->dev, "starfive,vdec_noc_ctrl"))
  1904. vpu_clk->noc_ctrl = true;
  1905. return 0;
  1906. }
  1907. static vpu_clk_t *vpu_clk_get(struct platform_device *pdev)
  1908. {
  1909. vpu_clk_t *vpu_clk;
  1910. vpu_clk = devm_kzalloc(&pdev->dev, sizeof(*vpu_clk), GFP_KERNEL);
  1911. if (!vpu_clk)
  1912. return NULL;
  1913. if (vpu_of_clk_get(pdev, vpu_clk))
  1914. goto err_get_clk;
  1915. return vpu_clk;
  1916. err_get_clk:
  1917. devm_kfree(&pdev->dev, vpu_clk);
  1918. return NULL;
  1919. }
  1920. static void vpu_clk_put(vpu_clk_t *clk)
  1921. {
  1922. if (clk->clkgen) {
  1923. iounmap(clk->clkgen);
  1924. clk->clkgen = NULL;
  1925. }
  1926. }
  1927. static int vpu_clk_enable(vpu_clk_t *clk)
  1928. {
  1929. if (clk == NULL || IS_ERR(clk))
  1930. return -1;
  1931. vpu_pmu_enable(clk->dev);
  1932. vpu_clk_control(clk, true);
  1933. if (clk->noc_ctrl == true)
  1934. vpu_noc_vdec_bus_control(clk, true);
  1935. DPRINTK("[VPUDRV] vpu_clk_enable\n");
  1936. return 0;
  1937. }
  1938. static void vpu_clk_disable(vpu_clk_t *clk)
  1939. {
  1940. if (clk == NULL || IS_ERR(clk))
  1941. return;
  1942. vpu_clk_control(clk, false);
  1943. vpu_pmu_disable(clk->dev);
  1944. if (clk->noc_ctrl == true)
  1945. vpu_noc_vdec_bus_control(clk, false);
  1946. DPRINTK("[VPUDRV] vpu_clk_disable\n");
  1947. }
  1948. #else /*STARFIVE_VPU_SUPPORT_CLOCK_CONTROL*/
  1949. int vpu_hw_reset(void)
  1950. {
  1951. DPRINTK("[VPUDRV] reset vpu hardware. \n");
  1952. /* sram do not need reset */
  1953. return reset_control_reset(s_vpu_clk->resets);
  1954. }
  1955. static int vpu_of_clk_get(struct platform_device *pdev, vpu_clk_t *vpu_clk)
  1956. {
  1957. struct device *dev = &pdev->dev;
  1958. int ret;
  1959. vpu_clk->dev = dev;
  1960. vpu_clk->clks = vpu_clks;
  1961. vpu_clk->nr_clks = ARRAY_SIZE(vpu_clks);
  1962. vpu_clk->resets = devm_reset_control_array_get_shared(dev);
  1963. if (IS_ERR(vpu_clk->resets)) {
  1964. ret = PTR_ERR(vpu_clk->resets);
  1965. dev_err(dev, "faied to get vpu reset controls\n");
  1966. }
  1967. ret = devm_clk_bulk_get(dev, vpu_clk->nr_clks, vpu_clk->clks);
  1968. if (ret)
  1969. dev_err(dev, "faied to get vpu clk controls\n");
  1970. if (device_property_read_bool(dev, "starfive,vdec_noc_ctrl"))
  1971. vpu_clk->noc_ctrl = true;
  1972. return 0;
  1973. }
  1974. static vpu_clk_t *vpu_clk_get(struct platform_device *pdev)
  1975. {
  1976. vpu_clk_t *vpu_clk;
  1977. if (!pdev)
  1978. return NULL;
  1979. vpu_clk = devm_kzalloc(&pdev->dev, sizeof(*vpu_clk), GFP_KERNEL);
  1980. if (!vpu_clk)
  1981. return NULL;
  1982. if (vpu_of_clk_get(pdev, vpu_clk))
  1983. goto err_of_clk_get;
  1984. return vpu_clk;
  1985. err_of_clk_get:
  1986. devm_kfree(&pdev->dev, vpu_clk);
  1987. return NULL;
  1988. }
  1989. static void vpu_clk_put(vpu_clk_t *clk)
  1990. {
  1991. clk_bulk_put(clk->nr_clks, clk->clks);
  1992. }
  1993. static int vpu_clk_enable(vpu_clk_t *clk)
  1994. {
  1995. int ret;
  1996. ret = clk_bulk_prepare_enable(clk->nr_clks, clk->clks);
  1997. if (ret)
  1998. dev_err(clk->dev, "enable clk error.\n");
  1999. DPRINTK("[VPUDRV] vpu_clk_enable\n");
  2000. return ret;
  2001. }
  2002. static void vpu_clk_disable(vpu_clk_t *clk)
  2003. {
  2004. clk_bulk_disable_unprepare(clk->nr_clks, clk->clks);
  2005. }
  2006. #endif