vpuconfig.h 7.3 KB

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  1. //SPDX-License-Identifier: LGPL-2.1 OR BSD-3-Clause
  2. /*
  3. * Copyright (c) 2019, Chips&Media
  4. * All rights reserved.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. *
  9. * 1. Redistributions of source code must retain the above copyright notice, this
  10. * list of conditions and the following disclaimer.
  11. * 2. Redistributions in binary form must reproduce the above copyright notice,
  12. * this list of conditions and the following disclaimer in the documentation
  13. * and/or other materials provided with the distribution.
  14. *
  15. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  16. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  17. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
  19. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  21. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  22. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  23. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  24. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25. */
  26. #ifndef _VPU_CONFIG_H_
  27. #define _VPU_CONFIG_H_
  28. #include "../config.h"
  29. #define ENC_STREAM_BUF_COUNT 5
  30. #define ENC_STREAM_BUF_SIZE 0xF00000
  31. #define BODA950_CODE 0x9500
  32. #define CODA960_CODE 0x9600
  33. #define CODA980_CODE 0x9800
  34. #define WAVE512_CODE 0x5120
  35. #define WAVE515_CODE 0x5150
  36. #define WAVE517_CODE 0x5170
  37. #define WAVE511_CODE 0x5110
  38. #define WAVE521_CODE 0x5210
  39. #define WAVE521C_CODE 0x521c
  40. #define WAVE521C_DUAL_CODE 0x521d // wave521 dual core
  41. #define PRODUCT_CODE_W_SERIES(x) (x == WAVE512_CODE || x == WAVE515_CODE || x == WAVE517_CODE || x == WAVE511_CODE || x == WAVE521_CODE || x == WAVE521C_CODE || x == WAVE521C_DUAL_CODE)
  42. #define PRODUCT_CODE_NOT_W_SERIES(x) (x == BODA950_CODE || x == CODA960_CODE || x == CODA980_CODE)
  43. #define WAVE5_MAX_CODE_BUF_SIZE (1024*1024)
  44. #define WAVE521ENC_WORKBUF_SIZE (128*1024) //HEVC 128K, AVC 40K
  45. #define WAVE512DEC_WORKBUF_SIZE (2*1024*1024)
  46. #define WAVE515DEC_WORKBUF_SIZE (2*1024*1024)
  47. #define WAVE521DEC_WORKBUF_SIZE (1784*1024)
  48. #define MAX_INST_HANDLE_SIZE 48 /* DO NOT CHANGE THIS VALUE */
  49. #define MAX_NUM_INSTANCE 4
  50. #define MAX_NUM_VPU_CORE 1
  51. #define MAX_NUM_VCORE 1
  52. #define MAX_ENC_AVC_PIC_WIDTH 4096
  53. #define MAX_ENC_AVC_PIC_HEIGHT 2304
  54. #define MAX_ENC_PIC_WIDTH 4096
  55. #define MAX_ENC_PIC_HEIGHT 2304
  56. #define MIN_ENC_PIC_WIDTH 96
  57. #define MIN_ENC_PIC_HEIGHT 16
  58. // for WAVE420
  59. #define W4_MIN_ENC_PIC_WIDTH 256
  60. #define W4_MIN_ENC_PIC_HEIGHT 128
  61. #define W4_MAX_ENC_PIC_WIDTH 8192
  62. #define W4_MAX_ENC_PIC_HEIGHT 8192
  63. #define MAX_DEC_PIC_WIDTH 4096
  64. #define MAX_DEC_PIC_HEIGHT 2304
  65. #define MAX_CTU_NUM 0x4000 // CTU num for max resolution = 8192x8192/(64x64)
  66. #define MAX_SUB_CTU_NUM (MAX_CTU_NUM*4)
  67. #define MAX_MB_NUM 0x40000 // MB num for max resolution = 8192x8192/(16x16)
  68. // Application specific configuration
  69. #define VPU_ENC_TIMEOUT 60000
  70. #define VPU_DEC_TIMEOUT 60000
  71. #define VPU_BUSY_CHECK_TIMEOUT 10000
  72. // codec specific configuration
  73. #define VPU_REORDER_ENABLE 1 // it can be set to 1 to handle reordering DPB in host side.
  74. #define CBCR_INTERLEAVE 1 //[default 1 for BW checking with CnMViedo Conformance] 0 (chroma separate mode), 1 (chroma interleave mode) // if the type of tiledmap uses the kind of MB_RASTER_MAP. must set to enable CBCR_INTERLEAVE
  75. #define VPU_ENABLE_BWB 1
  76. #define HOST_ENDIAN VDI_128BIT_LITTLE_ENDIAN
  77. #define VPU_FRAME_ENDIAN HOST_ENDIAN
  78. #define VPU_STREAM_ENDIAN HOST_ENDIAN
  79. #define VPU_USER_DATA_ENDIAN HOST_ENDIAN
  80. #define VPU_SOURCE_ENDIAN HOST_ENDIAN
  81. #define DRAM_BUS_WIDTH 16
  82. // for WAVE Encoder
  83. #define USE_SRC_PRP_AXI 0
  84. #define USE_SRC_PRI_AXI 1
  85. #define DEFAULT_SRC_AXI USE_SRC_PRP_AXI
  86. /************************************************************************/
  87. /* VPU COMMON MEMORY */
  88. /************************************************************************/
  89. #define VLC_BUF_NUM (3)
  90. #define COMMAND_QUEUE_DEPTH (4)
  91. #ifdef SUPPORT_LOOK_AHEAD_RC
  92. #define MAX_SRC_BUFFER_NUM 13
  93. #define ENC_SRC_BUF_NUM (MAX_SRC_BUFFER_NUM+COMMAND_QUEUE_DEPTH) //!< case of GOPsize = 8 (IBBBBBBBP), max src buffer num = 13
  94. #else
  95. #define ENC_SRC_BUF_NUM 20 // [FIX ME]
  96. #endif
  97. #define ONE_TASKBUF_SIZE_FOR_W5DEC_CQ (8*1024*1024) /* upto 8Kx4K, need 8Mbyte per task*/
  98. #define ONE_TASKBUF_SIZE_FOR_W5ENC_CQ (8*1024*1024) /* upto 8Kx8K, need 8Mbyte per task.*/
  99. #define ONE_TASKBUF_SIZE_FOR_W511DEC_CQ (8*1024*1024) /* upto 8Kx8K, need 8Mbyte per task.*/
  100. /* FW will return one TASKBUF size base on MaxCPB (according to the SPEC), but this size will be quite big depend on profile/level.*/
  101. /* ex) main10, 8kx8k = 180Mbytes will be returned */
  102. /* Thus, if host can set size limitation for one TASKBUF size. (but, small size limitation can cause processing error) */
  103. #define ONE_TASKBUF_MAX_SIZE_LIMIT_DEC (8*1024*1024)
  104. #define ONE_TASKBUF_MAX_SIZE_LIMIT_ENC (20*1024*1024)
  105. #define ONE_TASKBUF_SIZE_FOR_CQ 0
  106. #define SIZE_COMMON (2*1024*1024)
  107. //=====4. VPU REPORT MEMORY ======================//
  108. #define SIZE_REPORT_BUF (0x10000)
  109. #define STREAM_END_SIZE 0
  110. #define STREAM_END_SET_FLAG 0
  111. #define STREAM_END_CLEAR_FLAG -1
  112. #define EXPLICIT_END_SET_FLAG -2
  113. #define UPDATE_NEW_BS_BUF 0
  114. #define USE_BIT_INTERNAL_BUF 1
  115. #define USE_IP_INTERNAL_BUF 1
  116. #define USE_DBKY_INTERNAL_BUF 1
  117. #define USE_DBKC_INTERNAL_BUF 1
  118. #define USE_OVL_INTERNAL_BUF 1
  119. #define USE_BTP_INTERNAL_BUF 1
  120. #define USE_ME_INTERNAL_BUF 1
  121. /* WAVE410 only */
  122. #define USE_BPU_INTERNAL_BUF 1
  123. #define USE_VCE_IP_INTERNAL_BUF 1
  124. #define USE_VCE_LF_ROW_INTERNAL_BUF 1
  125. /* WAVE420 only */
  126. #define USE_IMD_INTERNAL_BUF 1
  127. #define USE_RDO_INTERNAL_BUF 1
  128. #define USE_LF_INTERNAL_BUF 1
  129. #define WAVE5_UPPER_PROC_AXI_ID 0x0
  130. #define WAVE5_PROC_AXI_ID 0x0
  131. #define WAVE5_PRP_AXI_ID 0x0
  132. #define WAVE5_FBD_Y_AXI_ID 0x0
  133. #define WAVE5_FBC_Y_AXI_ID 0x0
  134. #define WAVE5_FBD_C_AXI_ID 0x0
  135. #define WAVE5_FBC_C_AXI_ID 0x0
  136. #define WAVE5_SEC_AXI_ID 0x0
  137. #define WAVE5_PRI_AXI_ID 0x0
  138. #endif /* _VPU_CONFIG_H_ */