coda9_regdefine.h 30 KB

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  1. //SPDX-License-Identifier: LGPL-2.1 OR BSD-3-Clause
  2. /*
  3. * Copyright (c) 2019, Chips&Media
  4. * All rights reserved.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. *
  9. * 1. Redistributions of source code must retain the above copyright notice, this
  10. * list of conditions and the following disclaimer.
  11. * 2. Redistributions in binary form must reproduce the above copyright notice,
  12. * this list of conditions and the following disclaimer in the documentation
  13. * and/or other materials provided with the distribution.
  14. *
  15. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  16. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  17. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
  19. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  21. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  22. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  23. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  24. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25. */
  26. #include "../../config.h"
  27. #ifndef REGDEFINE_H_INCLUDED
  28. #define REGDEFINE_H_INCLUDED
  29. //------------------------------------------------------------------------------
  30. // REGISTER BASE
  31. //------------------------------------------------------------------------------
  32. #define BIT_BASE 0x0000
  33. #define GDMA_BASE 0x1000
  34. #define MBC_BASE 0x0400
  35. #define ME_BASE 0x0600
  36. #define MC_BASE 0x0C00
  37. #define DMAC_BASE 0x2000
  38. #define BW_BASE 0x03000000
  39. //------------------------------------------------------------------------------
  40. // HARDWARE REGISTER
  41. //------------------------------------------------------------------------------
  42. // SW Reset command
  43. #define VPU_SW_RESET_BPU_CORE 0x008
  44. #define VPU_SW_RESET_BPU_BUS 0x010
  45. #define VPU_SW_RESET_VCE_CORE 0x020
  46. #define VPU_SW_RESET_VCE_BUS 0x040
  47. #define VPU_SW_RESET_GDI_CORE 0x080
  48. #define VPU_SW_RESET_GDI_BUS 0x100
  49. #define BIT_CODE_RUN (BIT_BASE + 0x000)
  50. #define BIT_CODE_DOWN (BIT_BASE + 0x004)
  51. #define BIT_INT_REQ (BIT_BASE + 0x008)
  52. #define BIT_INT_CLEAR (BIT_BASE + 0x00C)
  53. #define BIT_INT_STS (BIT_BASE + 0x010)
  54. #define BIT_CODE_RESET (BIT_BASE + 0x014)
  55. #define BIT_CUR_PC (BIT_BASE + 0x018)
  56. #define BIT_SW_RESET (BIT_BASE + 0x024)
  57. #define BIT_SW_RESET_STATUS (BIT_BASE + 0x034)
  58. //------------------------------------------------------------------------------
  59. // GLOBAL REGISTER
  60. //------------------------------------------------------------------------------
  61. #define BIT_CODE_BUF_ADDR (BIT_BASE + 0x100)
  62. #define BIT_WORK_BUF_ADDR (BIT_BASE + 0x104)
  63. #define BIT_PARA_BUF_ADDR (BIT_BASE + 0x108)
  64. #define BIT_BIT_STREAM_CTRL (BIT_BASE + 0x10C)
  65. #define BIT_FRAME_MEM_CTRL (BIT_BASE + 0x110)
  66. #define BIT_BIT_STREAM_PARAM (BIT_BASE + 0x114)
  67. #define BIT_TEMP_BUF_ADDR (BIT_BASE + 0x118)
  68. #define BIT_RD_PTR (BIT_BASE + 0x120)
  69. #define BIT_WR_PTR (BIT_BASE + 0x124)
  70. #define BIT_ROLLBACK_STATUS (BIT_BASE + 0x128) // internal used in f/w.
  71. #define BIT_AXI_SRAM_USE (BIT_BASE + 0x140)
  72. #define BIT_BYTE_POS_FRAME_START (BIT_BASE + 0x144)
  73. #define BIT_BYTE_POS_FRAME_END (BIT_BASE + 0x148)
  74. #define BIT_FRAME_CYCLE (BIT_BASE + 0x14C)
  75. #define BIT_FRM_DIS_FLG (BIT_BASE + 0x150)
  76. #define BIT_BUSY_FLAG (BIT_BASE + 0x160)
  77. #define BIT_RUN_COMMAND (BIT_BASE + 0x164)
  78. #define BIT_RUN_INDEX (BIT_BASE + 0x168)
  79. #define BIT_RUN_COD_STD (BIT_BASE + 0x16C)
  80. #define BIT_INT_ENABLE (BIT_BASE + 0x170)
  81. #define BIT_INT_REASON (BIT_BASE + 0x174)
  82. #define BIT_RUN_AUX_STD (BIT_BASE + 0x178)
  83. // MSG REGISTER ADDRESS changed
  84. #define BIT_MSG_0 (BIT_BASE + 0x130)
  85. #define BIT_MSG_1 (BIT_BASE + 0x134)
  86. #define BIT_MSG_2 (BIT_BASE + 0x138)
  87. #define BIT_MSG_3 (BIT_BASE + 0x13C)
  88. #define MBC_BUSY (MBC_BASE + 0x040)
  89. #define MC_BUSY (MC_BASE + 0x004)
  90. //------------------------------------------------------------------------------
  91. // [ENC SEQ INIT] COMMAND
  92. //------------------------------------------------------------------------------
  93. #define CMD_ENC_SEQ_BB_START (BIT_BASE + 0x180)
  94. #define CMD_ENC_SEQ_BB_SIZE (BIT_BASE + 0x184)
  95. #define CMD_ENC_SEQ_OPTION (BIT_BASE + 0x188) // HecEnable,ConstIntraQp, FMO, QPREP, AUD, SLICE, MB BIT
  96. #define CMD_ENC_SEQ_COD_STD (BIT_BASE + 0x18C)
  97. #define CMD_ENC_SEQ_SRC_SIZE (BIT_BASE + 0x190)
  98. #define CMD_ENC_SEQ_SRC_F_RATE (BIT_BASE + 0x194)
  99. #define CMD_ENC_SEQ_MP4_PARA (BIT_BASE + 0x198)
  100. #define CMD_ENC_SEQ_263_PARA (BIT_BASE + 0x19C)
  101. #define CMD_ENC_SEQ_264_PARA (BIT_BASE + 0x1A0)
  102. #define CMD_ENC_SEQ_SLICE_MODE (BIT_BASE + 0x1A4)
  103. #define CMD_ENC_SEQ_GOP_NUM (BIT_BASE + 0x1A8)
  104. #define CMD_ENC_SEQ_RC_PARA (BIT_BASE + 0x1AC)
  105. #define CMD_ENC_SEQ_RC_BUF_SIZE (BIT_BASE + 0x1B0)
  106. #define CMD_ENC_SEQ_INTRA_REFRESH (BIT_BASE + 0x1B4)
  107. #define CMD_ENC_SEQ_INTRA_QP (BIT_BASE + 0x1C4)
  108. #define CMD_ENC_SEQ_RC_QP_MAX (BIT_BASE + 0x1C8)
  109. #define CMD_ENC_SEQ_RC_GAMMA (BIT_BASE + 0x1CC)
  110. #define CMD_ENC_SEQ_RC_INTERVAL_MODE (BIT_BASE + 0x1D0) // mbInterval[32:2], rcIntervalMode[1:0]
  111. #define CMD_ENC_SEQ_INTRA_WEIGHT (BIT_BASE + 0x1D4)
  112. #define CMD_ENC_SEQ_ME_OPTION (BIT_BASE + 0x1D8)
  113. #define CMD_ENC_SEQ_RC_PARA2 (BIT_BASE + 0x1DC)
  114. #define CMD_ENC_SEQ_QP_RANGE_SET (BIT_BASE + 0x1E0)
  115. #define CMD_ENC_SEQ_RC_MAX_INTRA_SIZE (BIT_BASE + 0x1F0)
  116. #define CMD_ENC_SEQ_FIRST_MBA (BIT_BASE + 0x1E4)
  117. #define CMD_ENC_SEQ_HEIGHT_IN_MAP_UNITS (BIT_BASE + 0x1E8)
  118. #define CMD_ENC_SEQ_OVERLAP_CLIP_SIZE (BIT_BASE + 0x1EC)
  119. //------------------------------------------------------------------------------
  120. // [ENC SEQ END] COMMAND
  121. //------------------------------------------------------------------------------
  122. #define RET_ENC_SEQ_END_SUCCESS (BIT_BASE + 0x1C0)
  123. //------------------------------------------------------------------------------
  124. // [ENC PIC RUN] COMMAND
  125. //------------------------------------------------------------------------------
  126. #define CMD_ENC_PIC_SRC_INDEX (BIT_BASE + 0x180)
  127. #define CMD_ENC_PIC_SRC_STRIDE (BIT_BASE + 0x184)
  128. #define CMD_ENC_PIC_SRC_ADDR_Y (BIT_BASE + 0x1A8)
  129. #define CMD_ENC_PIC_SRC_ADDR_CB (BIT_BASE + 0x1AC)
  130. #define CMD_ENC_PIC_SRC_ADDR_CR (BIT_BASE + 0x1B0)
  131. #define CMD_ENC_PIC_SRC_BOTTOM_Y (BIT_BASE + 0x1E8) //coda980 only
  132. #define CMD_ENC_PIC_SRC_BOTTOM_CB (BIT_BASE + 0x1EC) //coda980 only
  133. #define CMD_ENC_PIC_SRC_BOTTOM_CR (BIT_BASE + 0x1F0) //coda980 only
  134. #define CMD_ENC_PIC_QS (BIT_BASE + 0x18C)
  135. #define CMD_ENC_PIC_ROT_MODE (BIT_BASE + 0x190)
  136. #define CMD_ENC_PIC_OPTION (BIT_BASE + 0x194)
  137. #define CMD_ENC_PIC_BB_START (BIT_BASE + 0x198)
  138. #define CMD_ENC_PIC_BB_SIZE (BIT_BASE + 0x19C)
  139. #define CMD_ENC_PIC_PARA_BASE_ADDR (BIT_BASE + 0x1A0)
  140. #define CMD_ENC_PIC_SUB_FRAME_SYNC (BIT_BASE + 0x1A4)
  141. #define RET_ENC_PIC_FRAME_NUM (BIT_BASE + 0x1C0)
  142. #define RET_ENC_PIC_TYPE (BIT_BASE + 0x1C4)
  143. #define RET_ENC_PIC_FRAME_IDX (BIT_BASE + 0x1C8)
  144. #define RET_ENC_PIC_SLICE_NUM (BIT_BASE + 0x1CC)
  145. #define RET_ENC_PIC_FLAG (BIT_BASE + 0x1D0)
  146. #define RET_ENC_PIC_SUCCESS (BIT_BASE + 0x1D8)
  147. //------------------------------------------------------------------------------
  148. // [ENC ROI INIT] COMMAND
  149. //------------------------------------------------------------------------------
  150. #define CMD_ENC_ROI_INFO (BIT_BASE + 0x180) // [7:1]: RoiPicAvgQp, [0]: RoiEn
  151. #define CMD_ENC_ROI_QP_MAP_ADDR (BIT_BASE + 0x184) // [31:0] ROI Qp map address
  152. #define RET_ENC_ROI_SUCCESS (BIT_BASE + 0x1D8)
  153. //------------------------------------------------------------------------------
  154. // [ENC SET FRAME BUF] COMMAND
  155. //------------------------------------------------------------------------------
  156. #define CMD_SET_FRAME_SUBSAMP_A (BIT_BASE + 0x188) //coda960 only
  157. #define CMD_SET_FRAME_SUBSAMP_B (BIT_BASE + 0x18C) //coda960 only
  158. #define CMD_SET_FRAME_SUBSAMP_A_MVC (BIT_BASE + 0x1B0) //coda960 only
  159. #define CMD_SET_FRAME_SUBSAMP_B_MVC (BIT_BASE + 0x1B4) //coda960 only
  160. #define CMD_SET_FRAME_DP_BUF_BASE (BIT_BASE + 0x1B0)
  161. #define CMD_SET_FRAME_DP_BUF_SIZE (BIT_BASE + 0x1B4)
  162. //------------------------------------------------------------------------------
  163. // [ENC HEADER] COMMAND
  164. //------------------------------------------------------------------------------
  165. #define CMD_ENC_HEADER_CODE (BIT_BASE + 0x180)
  166. #define CMD_ENC_HEADER_BB_START (BIT_BASE + 0x184)
  167. #define CMD_ENC_HEADER_BB_SIZE (BIT_BASE + 0x188)
  168. #define CMD_ENC_HEADER_FRAME_CROP_H (BIT_BASE + 0x18C)
  169. #define CMD_ENC_HEADER_FRAME_CROP_V (BIT_BASE + 0x190)
  170. #define CMD_ENC_HEADER_CABAC_MODE (BIT_BASE + 0x194) // CODA980
  171. #define CMD_ENC_HEADER_CABAC_INIT_IDC (BIT_BASE + 0x198) // CODA980
  172. #define CMD_ENC_HEADER_TRANSFORM_8X8 (BIT_BASE + 0x19C) // CODA980
  173. #define CMD_ENC_HEADER_CHROMA_FORMAT (BIT_BASE + 0x1A0) // CODA980
  174. #define CMD_ENC_HEADER_FIELD_FLAG (BIT_BASE + 0x1A4)
  175. #define CMD_ENC_HEADER_PROFILE (BIT_BASE + 0x1A8) // CODA980
  176. #define RET_ENC_HEADER_SUCCESS (BIT_BASE + 0x1C0)
  177. //------------------------------------------------------------------------------
  178. // [ENC_PARA_SET] COMMAND
  179. //------------------------------------------------------------------------------
  180. #define CMD_ENC_PARA_SET_TYPE (BIT_BASE + 0x180)
  181. #define RET_ENC_PARA_SET_SIZE (BIT_BASE + 0x1c0)
  182. #define RET_ENC_PARA_SET_SUCCESS (BIT_BASE + 0x1C4)
  183. //------------------------------------------------------------------------------
  184. // [ENC PARA CHANGE] COMMAND :
  185. //------------------------------------------------------------------------------
  186. #define CMD_ENC_PARAM_CHANGE_ENABLE (BIT_BASE + 0x180) // FrameRateEn[3], BitRateEn[2], IntraQpEn[1], GopEn[0]
  187. #define CMD_ENC_PARAM_CHANGE_GOP_NUM (BIT_BASE + 0x184)
  188. #define CMD_ENC_PARAM_CHANGE_INTRA_QP (BIT_BASE + 0x188)
  189. #define CMD_ENC_PARAM_CHANGE_BITRATE (BIT_BASE + 0x18C)
  190. #define CMD_ENC_PARAM_CHANGE_F_RATE (BIT_BASE + 0x190)
  191. #define CMD_ENC_PARAM_CHANGE_INTRA_REFRESH (BIT_BASE + 0x194) // update param
  192. #define CMD_ENC_PARAM_CHANGE_SLICE_MODE (BIT_BASE + 0x198) // update param
  193. #define CMD_ENC_PARAM_CHANGE_HEC_MODE (BIT_BASE + 0x19C) // update param
  194. #define CMD_ENC_PARAM_CHANGE_CABAC_MODE (BIT_BASE + 0x1A0) // entropyCodingMode==2
  195. #define CMD_ENC_PARAM_CHANGE_PPS_ID (BIT_BASE + 0x1B4) // entropyCodingMode==2
  196. #define RET_ENC_SEQ_PARA_CHANGE_SUCCESS (BIT_BASE + 0x1C0)
  197. //------------------------------------------------------------------------------
  198. // [DEC SEQ INIT] COMMAND
  199. //------------------------------------------------------------------------------
  200. #define CMD_DEC_SEQ_BB_START (BIT_BASE + 0x180)
  201. #define CMD_DEC_SEQ_BB_SIZE (BIT_BASE + 0x184)
  202. #define CMD_DEC_SEQ_OPTION (BIT_BASE + 0x188)
  203. #define CMD_DEC_SEQ_MP4_ASP_CLASS (BIT_BASE + 0x19C)
  204. #define CMD_DEC_SEQ_VC1_STREAM_FMT (BIT_BASE + 0x19C)
  205. #define CMD_DEC_SEQ_X264_MV_EN (BIT_BASE + 0x19C)
  206. #define CMD_DEC_SEQ_SPP_CHUNK_SIZE (BIT_BASE + 0x1A0)
  207. // For MPEG2 only
  208. #define CMD_DEC_SEQ_USER_DATA_OPTION (BIT_BASE + 0x194)
  209. #define CMD_DEC_SEQ_USER_DATA_BASE_ADDR (BIT_BASE + 0x1AC)
  210. #define CMD_DEC_SEQ_USER_DATA_BUF_SIZE (BIT_BASE + 0x1B0)
  211. #define CMD_DEC_SEQ_INIT_ESCAPE (BIT_BASE + 0x114)
  212. #define RET_DEC_SEQ_BIT_RATE (BIT_BASE + 0x1B4)
  213. #define RET_DEC_SEQ_EXT_INFO (BIT_BASE + 0x1B8)
  214. #define RET_DEC_SEQ_SUCCESS (BIT_BASE + 0x1C0)
  215. #define RET_DEC_SEQ_SRC_SIZE (BIT_BASE + 0x1C4)
  216. #define RET_DEC_SEQ_ASPECT (BIT_BASE + 0x1C8)
  217. #define RET_DEC_SEQ_FRAME_NEED (BIT_BASE + 0x1CC)
  218. #define RET_DEC_SEQ_FRAME_DELAY (BIT_BASE + 0x1D0)
  219. #define RET_DEC_SEQ_INFO (BIT_BASE + 0x1D4)
  220. #define RET_DEC_SEQ_VP8_SCALE_INFO (BIT_BASE + 0x1D4)
  221. #define RET_DEC_SEQ_CROP_LEFT_RIGHT (BIT_BASE + 0x1D8)
  222. #define RET_DEC_SEQ_CROP_TOP_BOTTOM (BIT_BASE + 0x1DC)
  223. #define RET_DEC_SEQ_SEQ_ERR_REASON (BIT_BASE + 0x1E0)
  224. #define RET_DEC_SEQ_FRATE_NR (BIT_BASE + 0x1E4)
  225. #define RET_DEC_SEQ_FRATE_DR (BIT_BASE + 0x1E8)
  226. #define RET_DEC_SEQ_HEADER_REPORT (BIT_BASE + 0x1EC)
  227. #define RET_DEC_SEQ_VUI_INFO (BIT_BASE + 0x18C)
  228. #define RET_DEC_SEQ_VUI_PIC_STRUCT (BIT_BASE + 0x1A8)
  229. #define RET_DEC_SEQ_MP2_BAR_LEFT_RIGHT (BIT_BASE + 0x180)
  230. #define RET_DEC_SEQ_MP2_BAR_TOP_BOTTOM (BIT_BASE + 0x184)
  231. #define RET_DEC_PIC_MP2_OFFSET1 (BIT_BASE + 0x19C) // for MP2
  232. #define RET_DEC_PIC_MP2_OFFSET2 (BIT_BASE + 0x1A0) // for MP2
  233. #define RET_DEC_PIC_MP2_OFFSET3 (BIT_BASE + 0x1A4) // for MP2
  234. #define RET_DEC_PIC_MP2_OFFSET_NUM (BIT_BASE + 0x1A8) // for MP2
  235. //------------------------------------------------------------------------------
  236. // [DEC SEQ END] COMMAND
  237. //------------------------------------------------------------------------------
  238. #define RET_DEC_SEQ_END_SUCCESS (BIT_BASE + 0x1C0)
  239. //------------------------------------------------------------------------------
  240. // [DEC PIC RUN] COMMAND
  241. //----------------------------------------------------
  242. #define CMD_DEC_PIC_ROT_MODE (BIT_BASE + 0x180)
  243. #define CMD_DEC_PIC_ROT_INDEX (BIT_BASE + 0x184)
  244. #define CMD_DEC_PIC_ROT_ADDR_Y (BIT_BASE + 0x188)
  245. #define CMD_DEC_PIC_ROT_ADDR_CB (BIT_BASE + 0x18C)
  246. #define CMD_DEC_PIC_ROT_ADDR_CR (BIT_BASE + 0x190)
  247. #define CMD_DEC_PIC_ROT_STRIDE (BIT_BASE + 0x1B8)
  248. #define CMD_DEC_PIC_ROT_BOTTOM_Y (BIT_BASE + 0x1E8) // coda980 only
  249. #define CMD_DEC_PIC_ROT_BOTTOM_CB (BIT_BASE + 0x1EC) // coda980 only
  250. #define CMD_DEC_PIC_ROT_BOTTOM_CR (BIT_BASE + 0x1F0) // coda980 only
  251. #define CMD_DEC_PIC_OPTION (BIT_BASE + 0x194)
  252. #define CMD_DEC_PIC_USER_DATA_BASE_ADDR (BIT_BASE + 0x1AC)
  253. #define CMD_DEC_PIC_USER_DATA_BUF_SIZE (BIT_BASE + 0x1B0)
  254. #define CMD_DEC_PIC_NUM_ROWS (BIT_BASE + 0x1B4)
  255. #define CMD_DEC_PIC_THO_PIC_PARA (BIT_BASE + 0x198)
  256. #define CMD_DEC_PIC_THO_QMAT_ADDR (BIT_BASE + 0x1A0)
  257. #define CMD_DEC_PIC_THO_MB_PARA_ADDR (BIT_BASE + 0x1A4)
  258. #define RET_DEC_PIC_VUI_PIC_STRUCT (BIT_BASE + 0x1A8)
  259. #define RET_DEC_PIC_AVC_FPA_SEI0 (BIT_BASE + 0x19C)
  260. #define RET_DEC_PIC_AVC_FPA_SEI1 (BIT_BASE + 0x1A0)
  261. #define RET_DEC_PIC_AVC_FPA_SEI2 (BIT_BASE + 0x1A4)
  262. #define RET_DEC_NUM_MB_ROWS (BIT_BASE + 0x1B4) // it will be update
  263. #define RET_DEC_PIC_AVC_SEI_RP_INFO (BIT_BASE + 0x1B4)
  264. #define RET_DEC_PIC_HRD_INFO (BIT_BASE + 0x1B8)
  265. #define RET_DEC_PIC_SIZE (BIT_BASE + 0x1BC)
  266. #define RET_DEC_PIC_FRAME_NUM (BIT_BASE + 0x1C0)
  267. #define RET_DEC_PIC_FRAME_IDX (BIT_BASE + 0x1C4)
  268. #define RET_DEC_PIC_DISPLAY_IDX (BIT_BASE + 0x1C4)
  269. #define RET_DEC_PIC_ERR_MB (BIT_BASE + 0x1C8)
  270. #define RET_DEC_PIC_TYPE (BIT_BASE + 0x1CC)
  271. #define RET_DEC_PIC_POST (BIT_BASE + 0x1D0) // for VC1
  272. #define RET_DEC_PIC_MVC_REPORT (BIT_BASE + 0x1D0) // for MVC
  273. #define RET_DEC_PIC_OPTION (BIT_BASE + 0x1D4)
  274. #define RET_DEC_PIC_SUCCESS (BIT_BASE + 0x1D8)
  275. #define RET_DEC_PIC_CUR_IDX (BIT_BASE + 0x1DC)
  276. #define RET_DEC_PIC_DECODED_IDX (BIT_BASE + 0x1DC)
  277. #define RET_DEC_PIC_CROP_LEFT_RIGHT (BIT_BASE + 0x1E0) // for AVC, MPEG-2
  278. #define RET_DEC_PIC_CROP_TOP_BOTTOM (BIT_BASE + 0x1E4) // for AVC, MPEG-2
  279. #define RET_DEC_PIC_MODULO_TIME_BASE (BIT_BASE + 0x1E0) // for MP4
  280. #define RET_DEC_PIC_VOP_TIME_INCREMENT (BIT_BASE + 0x1E4) // for MP4
  281. #define RET_DEC_PIC_RV_TR (BIT_BASE + 0x1E8)
  282. #define RET_DEC_PIC_VP8_PIC_REPORT (BIT_BASE + 0x1E8)
  283. #define RET_DEC_PIC_ATSC_USER_DATA_INFO (BIT_BASE + 0x1E8) // H.264, MEPEG2
  284. #define RET_DEC_PIC_VUI_INFO (BIT_BASE + 0x1EC)
  285. #define RET_DEC_PIC_RV_TR_BFRAME (BIT_BASE + 0x1EC)
  286. #define RET_DEC_PIC_ASPECT (BIT_BASE + 0x1F0)
  287. #define RET_DEC_PIC_VP8_SCALE_INFO (BIT_BASE + 0x1F0)
  288. #define RET_DEC_PIC_FRATE_NR (BIT_BASE + 0x1F4)
  289. #define RET_DEC_PIC_FRATE_DR (BIT_BASE + 0x1F8)
  290. #define RET_DEC_PIC_POC_TOP (BIT_BASE + 0x1AC)
  291. #define RET_DEC_PIC_POC_BOT (BIT_BASE + 0x1B0)
  292. #define RET_DEC_PIC_POC (BIT_BASE + 0x1B0)
  293. //------------------------------------------------------------------------------
  294. // [DEC SET FRAME BUF] COMMAND
  295. //------------------------------------------------------------------------------
  296. #define CMD_SET_FRAME_BUF_NUM (BIT_BASE + 0x180)
  297. #define CMD_SET_FRAME_BUF_STRIDE (BIT_BASE + 0x184)
  298. #define CMD_SET_FRAME_SLICE_BB_START (BIT_BASE + 0x188)
  299. #define CMD_SET_FRAME_SLICE_BB_SIZE (BIT_BASE + 0x18C)
  300. #define CMD_SET_FRAME_AXI_BIT_ADDR (BIT_BASE + 0x190)
  301. #define CMD_SET_FRAME_AXI_IPACDC_ADDR (BIT_BASE + 0x194)
  302. #define CMD_SET_FRAME_AXI_DBKY_ADDR (BIT_BASE + 0x198)
  303. #define CMD_SET_FRAME_AXI_DBKC_ADDR (BIT_BASE + 0x19C)
  304. #define CMD_SET_FRAME_AXI_OVL_ADDR (BIT_BASE + 0x1A0)
  305. #define CMD_SET_FRAME_AXI_BTP_ADDR (BIT_BASE + 0x1A4)
  306. #define CMD_SET_FRAME_CACHE_SIZE (BIT_BASE + 0x1A8)
  307. #define CMD_SET_FRAME_CACHE_CONFIG (BIT_BASE + 0x1AC)
  308. #define CMD_SET_FRAME_MB_BUF_BASE (BIT_BASE + 0x1B0)
  309. #define CMD_SET_FRAME_MAX_DEC_SIZE (BIT_BASE + 0x1B8)
  310. #define CMD_SET_FRAME_DELAY (BIT_BASE + 0x1BC)
  311. #define RET_SET_FRAME_SUCCESS (BIT_BASE + 0x1C0)
  312. //------------------------------------------------------------------------------
  313. // [DEC_PARA_SET] COMMAND
  314. //------------------------------------------------------------------------------
  315. #define CMD_DEC_PARA_SET_TYPE (BIT_BASE + 0x180)
  316. #define CMD_DEC_PARA_SET_SIZE (BIT_BASE + 0x184)
  317. #define RET_DEC_PARA_SET_SUCCESS (BIT_BASE + 0x1C0)
  318. //------------------------------------------------------------------------------
  319. // [DEC_BUF_FLUSH] COMMAND
  320. //------------------------------------------------------------------------------
  321. #define RET_DEC_BUF_FLUSH_SUCCESS (BIT_BASE + 0x1C0)
  322. //------------------------------------------------------------------------------
  323. // [SLEEP/WAKE] COMMAND
  324. //------------------------------------------------------------------------------
  325. #define RET_SLEEP_WAKE_SUCCESS (BIT_BASE + 0x1C0)
  326. //------------------------------------------------------------------------------
  327. // [SET PIC INFO] COMMAND
  328. //------------------------------------------------------------------------------
  329. #define GDI_PRI_RD_PRIO_L (GDMA_BASE + 0x000)
  330. #define GDI_PRI_RD_PRIO_H (GDMA_BASE + 0x004)
  331. #define GDI_PRI_WR_PRIO_L (GDMA_BASE + 0x008)
  332. #define GDI_PRI_WR_PRIO_H (GDMA_BASE + 0x00c)
  333. #define GDI_PRI_RD_LOCK_CNT (GDMA_BASE + 0x010)
  334. #define GDI_PRI_WR_LOCK_CNT (GDMA_BASE + 0x014)
  335. #define GDI_SEC_RD_PRIO_L (GDMA_BASE + 0x018)
  336. #define GDI_SEC_RD_PRIO_H (GDMA_BASE + 0x01c)
  337. #define GDI_SEC_WR_PRIO_L (GDMA_BASE + 0x020)
  338. #define GDI_SEC_WR_PRIO_H (GDMA_BASE + 0x024)
  339. #define GDI_SEC_RD_LOCK_CNT (GDMA_BASE + 0x028)
  340. #define GDI_SEC_WR_LOCK_CNT (GDMA_BASE + 0x02c)
  341. #define GDI_SEC_CLIENT_EN (GDMA_BASE + 0x030)
  342. #define GDI_CONTROL (GDMA_BASE + 0x034)
  343. #define GDI_PIC_INIT_HOST (GDMA_BASE + 0x038)
  344. #define GDI_HW_VERINFO (GDMA_BASE + 0x050)
  345. #define GDI_PINFO_REQ (GDMA_BASE + 0x060)
  346. #define GDI_PINFO_ACK (GDMA_BASE + 0x064)
  347. #define GDI_PINFO_ADDR (GDMA_BASE + 0x068)
  348. #define GDI_PINFO_DATA (GDMA_BASE + 0x06c)
  349. #define GDI_BWB_ENABLE (GDMA_BASE + 0x070)
  350. #define GDI_BWB_SIZE (GDMA_BASE + 0x074)
  351. #define GDI_BWB_STD_STRUCT (GDMA_BASE + 0x078)
  352. #define GDI_BWB_STATUS (GDMA_BASE + 0x07c)
  353. #define GDI_STATUS (GDMA_BASE + 0x080)
  354. #define GDI_DEBUG_0 (GDMA_BASE + 0x084)
  355. #define GDI_DEBUG_1 (GDMA_BASE + 0x088)
  356. #define GDI_DEBUG_2 (GDMA_BASE + 0x08c)
  357. #define GDI_DEBUG_3 (GDMA_BASE + 0x090)
  358. #define GDI_DEBUG_PROBE_ADDR (GDMA_BASE + 0x094)
  359. #define GDI_DEBUG_PROBE_DATA (GDMA_BASE + 0x098)
  360. // write protect
  361. #define GDI_WPROT_ERR_CLR (GDMA_BASE + 0x0A0)
  362. #define GDI_WPROT_ERR_RSN (GDMA_BASE + 0x0A4)
  363. #define GDI_WPROT_ERR_ADR (GDMA_BASE + 0x0A8)
  364. #define GDI_WPROT_RGN_EN (GDMA_BASE + 0x0AC)
  365. #define GDI_WPROT_RGN0_STA (GDMA_BASE + 0x0B0)
  366. #define GDI_WPROT_RGN0_END (GDMA_BASE + 0x0B4)
  367. #define GDI_WPROT_RGN1_STA (GDMA_BASE + 0x0B8)
  368. #define GDI_WPROT_RGN1_END (GDMA_BASE + 0x0BC)
  369. #define GDI_WPROT_RGN2_STA (GDMA_BASE + 0x0C0)
  370. #define GDI_WPROT_RGN2_END (GDMA_BASE + 0x0C4)
  371. #define GDI_WPROT_RGN3_STA (GDMA_BASE + 0x0C8)
  372. #define GDI_WPROT_RGN3_END (GDMA_BASE + 0x0CC)
  373. #define GDI_WPROT_RGN4_STA (GDMA_BASE + 0x0D0)
  374. #define GDI_WPROT_RGN4_END (GDMA_BASE + 0x0D4)
  375. #define GDI_WPROT_RGN5_STA (GDMA_BASE + 0x0D8)
  376. #define GDI_WPROT_RGN5_END (GDMA_BASE + 0x0DC)
  377. #define GDI_WPROT_REGIONS 6
  378. #define GDI_BUS_CTRL (GDMA_BASE + 0x0F0)
  379. #define GDI_BUS_STATUS (GDMA_BASE + 0x0F4)
  380. #define GDI_SIZE_ERR_FLAG (GDMA_BASE + 0x0e0)
  381. #define GDI_ADR_RQ_SIZE_ERR_PRI0 (GDMA_BASE + 0x100)
  382. #define GDI_ADR_RQ_SIZE_ERR_PRI1 (GDMA_BASE + 0x104)
  383. #define GDI_ADR_RQ_SIZE_ERR_PRI1 (GDMA_BASE + 0x104)
  384. #define GDI_ADR_RQ_SIZE_ERR_PRI2 (GDMA_BASE + 0x108)
  385. #define GDI_ADR_WQ_SIZE_ERR_PRI0 (GDMA_BASE + 0x10c)
  386. #define GDI_ADR_WQ_SIZE_ERR_PRI1 (GDMA_BASE + 0x110)
  387. #define GDI_ADR_WQ_SIZE_ERR_PRI2 (GDMA_BASE + 0x114)
  388. #define GDI_ADR_RQ_SIZE_ERR_SEC0 (GDMA_BASE + 0x118)
  389. #define GDI_ADR_RQ_SIZE_ERR_SEC1 (GDMA_BASE + 0x11c)
  390. #define GDI_ADR_RQ_SIZE_ERR_SEC2 (GDMA_BASE + 0x120)
  391. #define GDI_ADR_WQ_SIZE_ERR_SEC0 (GDMA_BASE + 0x124)
  392. #define GDI_ADR_WQ_SIZE_ERR_SEC1 (GDMA_BASE + 0x128)
  393. #define GDI_ADR_WQ_SIZE_ERR_SEC2 (GDMA_BASE + 0x12c)
  394. #define GDI_INFO_CONTROL (GDMA_BASE + 0x400)
  395. #define GDI_INFO_PIC_SIZE (GDMA_BASE + 0x404)
  396. // GDI 2.0 register
  397. #define GDI_INFO_BASE_Y_TOP (GDMA_BASE + 0x408)
  398. #define GDI_INFO_BASE_CB_TOP (GDMA_BASE + 0x40C)
  399. #define GDI_INFO_BASE_CR_TOP (GDMA_BASE + 0x410)
  400. #define GDI_INFO_BASE_Y_BOT (GDMA_BASE + 0x414)
  401. #define GDI_INFO_BASE_CB_BOT (GDMA_BASE + 0x418)
  402. #define GDI_INFO_BASE_CR_BOT (GDMA_BASE + 0x41C)
  403. #define GDI_XY2AXI_LUM_BIT00 (GDMA_BASE + 0x800)
  404. #define GDI_XY2AXI_LUM_BIT1F (GDMA_BASE + 0x87C)
  405. #define GDI_XY2AXI_CHR_BIT00 (GDMA_BASE + 0x880)
  406. #define GDI_XY2AXI_CHR_BIT1F (GDMA_BASE + 0x8FC)
  407. #define GDI_XY2AXI_CONFIG (GDMA_BASE + 0x900)
  408. //GDI 1.0 register
  409. #define GDI_INFO_BASE_Y (GDMA_BASE + 0x408)
  410. #define GDI_INFO_BASE_CB (GDMA_BASE + 0x40C)
  411. #define GDI_INFO_BASE_CR (GDMA_BASE + 0x410)
  412. #define GDI_XY2_CAS_0 (GDMA_BASE + 0x800)
  413. #define GDI_XY2_CAS_F (GDMA_BASE + 0x83C)
  414. #define GDI_XY2_BA_0 (GDMA_BASE + 0x840)
  415. #define GDI_XY2_BA_1 (GDMA_BASE + 0x844)
  416. #define GDI_XY2_BA_2 (GDMA_BASE + 0x848)
  417. #define GDI_XY2_BA_3 (GDMA_BASE + 0x84C)
  418. #define GDI_XY2_RAS_0 (GDMA_BASE + 0x850)
  419. #define GDI_XY2_RAS_F (GDMA_BASE + 0x88C)
  420. #define GDI_XY2_RBC_CONFIG (GDMA_BASE + 0x890)
  421. #define GDI_RBC2_AXI_0 (GDMA_BASE + 0x8A0)
  422. #define GDI_RBC2_AXI_1F (GDMA_BASE + 0x91C)
  423. #define GDI_TILEDBUF_BASE (GDMA_BASE + 0x920)
  424. //------------------------------------------------------------------------------
  425. // Product, Reconfiguration Information
  426. //------------------------------------------------------------------------------
  427. #define DBG_CONFIG_REPORT_0 (GDMA_BASE + 0x040) //product name and version
  428. #define DBG_CONFIG_REPORT_1 (GDMA_BASE + 0x044) //interface configuration, hardware definition
  429. #define DBG_CONFIG_REPORT_2 (GDMA_BASE + 0x048) //standard definition
  430. #define DBG_CONFIG_REPORT_3 (GDMA_BASE + 0x04C) //standard detail definition
  431. #define DBG_CONFIG_REPORT_4 (GDMA_BASE + 0x050) //definition in cnm_define
  432. #define DBG_CONFIG_REPORT_5 (GDMA_BASE + 0x054)
  433. #define DBG_CONFIG_REPORT_6 (GDMA_BASE + 0x058)
  434. #define DBG_CONFIG_REPORT_7 (GDMA_BASE + 0x05C)
  435. //------------------------------------------------------------------------------
  436. // MEMORY COPY MODULE REGISTER
  437. //------------------------------------------------------------------------------
  438. #define ADDR_DMAC_PIC_RUN (DMAC_BASE+0x000)
  439. #define ADDR_DMAC_PIC_STATUS (DMAC_BASE+0x004)
  440. #define ADDR_DMAC_PIC_OP_MODE (DMAC_BASE+0x008)
  441. #define ADDR_DMAC_ID (DMAC_BASE+0x00c) //the result muse be 0x4d435059
  442. #define ADDR_DMAC_SRC_BASE_Y (DMAC_BASE+0x010)
  443. #define ADDR_DMAC_SRC_BASE_CB (DMAC_BASE+0x014)
  444. #define ADDR_DMAC_SRC_BASE_CR (DMAC_BASE+0x018)
  445. #define ADDR_DMAC_SRC_STRIDE (DMAC_BASE+0x01c)
  446. #define ADDR_DMAC_DST_BASE_Y (DMAC_BASE+0x020)
  447. #define ADDR_DMAC_DST_BASE_CB (DMAC_BASE+0x024)
  448. #define ADDR_DMAC_DST_BASE_CR (DMAC_BASE+0x028)
  449. #define ADDR_DMAC_DST_STRIDE (DMAC_BASE+0x02c)
  450. #define ADDR_DMAC_SRC_MB_POS_X (DMAC_BASE+0x030)
  451. #define ADDR_DMAC_SRC_MB_POS_Y (DMAC_BASE+0x034)
  452. #define ADDR_DMAC_SRC_MB_BLK_X (DMAC_BASE+0x038)
  453. #define ADDR_DMAC_SRC_MB_BLK_Y (DMAC_BASE+0x03c)
  454. #define ADDR_DMAC_DST_MB_POS_X (DMAC_BASE+0x040)
  455. #define ADDR_DMAC_DST_MB_POS_Y (DMAC_BASE+0x044)
  456. #define ADDR_DMAC_DST_MB_BLK_X (DMAC_BASE+0x048)
  457. #define ADDR_DMAC_DST_MB_BLK_Y (DMAC_BASE+0x04c)
  458. #define ADDR_DMAC_SET_COLOR_Y (DMAC_BASE+0x050)
  459. #define ADDR_DMAC_SET_COLOR_CB (DMAC_BASE+0x054)
  460. #define ADDR_DMAC_SET_COLOR_CR (DMAC_BASE+0x058)
  461. #define ADDR_DMAC_SUB_SAMPLE_X (DMAC_BASE+0x060)
  462. #define ADDR_DMAC_SUB_SAMPLE_Y (DMAC_BASE+0x064)
  463. //------------------------------------------------------------------------------
  464. // DMAC
  465. //------------------------------------------------------------------------------
  466. #define DMAC_DMAC_RUN (DMAC_BASE + 0x00)
  467. #define DMAC_SOFT_RESET (DMAC_BASE + 0x04)
  468. #define DMAC_DMAC_MODE (DMAC_BASE + 0x08)
  469. #define DMAC_DESC_ADDR (DMAC_BASE + 0x0c)
  470. #define DMAC_DESC0 (DMAC_BASE + 0x10)
  471. #define DMAC_DESC1 (DMAC_BASE + 0x14)
  472. #define DMAC_DESC2 (DMAC_BASE + 0x18)
  473. #define DMAC_DESC3 (DMAC_BASE + 0x1c)
  474. #define DMAC_DESC4 (DMAC_BASE + 0x20)
  475. #define DMAC_DESC5 (DMAC_BASE + 0x24)
  476. #define DMAC_DESC6 (DMAC_BASE + 0x28)
  477. #define DMAC_DESC7 (DMAC_BASE + 0x2c)
  478. //------------------------------------------------------------------------------
  479. //------------------------------------------------------------------------------
  480. // [FIRMWARE VERSION] COMMAND
  481. // [32:16] project number =>
  482. // [16:0] version => xxxx.xxxx.xxxxxxxx
  483. //------------------------------------------------------------------------------
  484. #define RET_FW_VER_NUM (BIT_BASE + 0x1c0)
  485. #define RET_FW_CODE_REV (BIT_BASE + 0x1c4)
  486. #endif