coda9.c 105 KB

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  1. //SPDX-License-Identifier: LGPL-2.1 OR BSD-3-Clause
  2. /*
  3. * Copyright (c) 2019, Chips&Media
  4. * All rights reserved.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. *
  9. * 1. Redistributions of source code must retain the above copyright notice, this
  10. * list of conditions and the following disclaimer.
  11. * 2. Redistributions in binary form must reproduce the above copyright notice,
  12. * this list of conditions and the following disclaimer in the documentation
  13. * and/or other materials provided with the distribution.
  14. *
  15. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  16. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  17. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
  19. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  21. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  22. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  23. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  24. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25. */
  26. #include "coda9_vpuconfig.h"
  27. #include "product.h"
  28. #include "coda9_regdefine.h"
  29. #include "misc/debug.h"
  30. static void LoadBitCode(Uint32 coreIdx, PhysicalAddress codeBase, const Uint16 *codeWord, int codeSize)
  31. {
  32. int i;
  33. BYTE code[8];
  34. for (i=0; i<codeSize; i+=4) {
  35. // 2byte little endian variable to 1byte big endian buffer
  36. code[0] = (BYTE)(codeWord[i+0]>>8);
  37. code[1] = (BYTE)codeWord[i+0];
  38. code[2] = (BYTE)(codeWord[i+1]>>8);
  39. code[3] = (BYTE)codeWord[i+1];
  40. code[4] = (BYTE)(codeWord[i+2]>>8);
  41. code[5] = (BYTE)codeWord[i+2];
  42. code[6] = (BYTE)(codeWord[i+3]>>8);
  43. code[7] = (BYTE)codeWord[i+3];
  44. VpuWriteMem(coreIdx, codeBase+i*2, (BYTE *)code, 8, VDI_BIG_ENDIAN);
  45. }
  46. vdi_set_bit_firmware_to_pm(coreIdx, codeWord);
  47. }
  48. static RetCode BitLoadFirmware(Uint32 coreIdx, PhysicalAddress codeBase, const Uint16 *codeWord, int codeSize)
  49. {
  50. int i;
  51. Uint32 data;
  52. LoadBitCode(coreIdx, codeBase, codeWord, codeSize);
  53. VpuWriteReg(coreIdx, BIT_INT_ENABLE, 0);
  54. VpuWriteReg(coreIdx, BIT_CODE_RUN, 0);
  55. for (i=0; i<2048; ++i) {
  56. data = codeWord[i];
  57. VpuWriteReg(coreIdx, BIT_CODE_DOWN, (i << 16) | data);
  58. }
  59. return RETCODE_SUCCESS;
  60. }
  61. static void SetEncFrameMemInfo(CodecInst* pCodecInst)
  62. {
  63. Uint32 val;
  64. EncInfo* pEncInfo = &pCodecInst->CodecInfo->encInfo;
  65. switch (pCodecInst->productId) {
  66. case PRODUCT_ID_960:
  67. val = 0;
  68. if (pEncInfo->mapType) {
  69. if (pEncInfo->mapType == TILED_FRAME_MB_RASTER_MAP || pEncInfo->mapType == TILED_FIELD_MB_RASTER_MAP)
  70. val |= (pEncInfo->linear2TiledEnable<<11)|(0x03<<9)|(FORMAT_420<<6);
  71. else
  72. val |= (pEncInfo->linear2TiledEnable<<11)|(0x02<<9)|(FORMAT_420<<6);
  73. }
  74. val |= ((pEncInfo->openParam.cbcrInterleave)<<2); // Interleave bit position is modified
  75. #if defined(SUPPORT_NV21) || defined(SUPPORT_ENC_NV21)
  76. val |= (pEncInfo->openParam.cbcrInterleave&pEncInfo->openParam.nv21) << 3;
  77. #endif
  78. val |= (pEncInfo->openParam.bwbEnable<<12);
  79. val |= pEncInfo->openParam.frameEndian;
  80. VpuWriteReg(pCodecInst->coreIdx, BIT_FRAME_MEM_CTRL, val);
  81. break;
  82. }
  83. return;
  84. }
  85. void Coda9BitIssueCommand(Uint32 coreIdx, CodecInst *inst, int cmd)
  86. {
  87. int instIdx = 0;
  88. int cdcMode = 0;
  89. int auxMode = 0;
  90. if (inst != NULL) // command is specific to instance
  91. {
  92. instIdx = inst->instIndex;
  93. cdcMode = inst->codecMode;
  94. auxMode = inst->codecModeAux;
  95. }
  96. if (inst) {
  97. if (inst->codecMode < AVC_ENC) {
  98. VpuWriteReg(coreIdx, BIT_WORK_BUF_ADDR, inst->CodecInfo->decInfo.vbWork.phys_addr);
  99. }
  100. else {
  101. VpuWriteReg(coreIdx, BIT_WORK_BUF_ADDR, inst->CodecInfo->encInfo.vbWork.phys_addr);
  102. }
  103. }
  104. VpuWriteReg(coreIdx, BIT_BUSY_FLAG, 1);
  105. VpuWriteReg(coreIdx, BIT_RUN_INDEX, instIdx);
  106. VpuWriteReg(coreIdx, BIT_RUN_COD_STD, cdcMode);
  107. VpuWriteReg(coreIdx, BIT_RUN_AUX_STD, auxMode);
  108. if (inst && inst->loggingEnable)
  109. vdi_log(coreIdx, cmd, 1);
  110. VpuWriteReg(coreIdx, BIT_RUN_COMMAND, cmd);
  111. }
  112. static void SetupCoda9Properties(Uint32 coreIdx, Uint32 productId)
  113. {
  114. VpuAttr* pAttr = &g_VpuCoreAttributes[coreIdx];
  115. Int32 val;
  116. char* pstr;
  117. /* Setup Attributes */
  118. pAttr = &g_VpuCoreAttributes[coreIdx];
  119. // Hardware version information
  120. val = VpuReadReg(coreIdx, VPU_PRODUCT_CODE_REGISTER);
  121. if ((val&0xff00) == 0x3200) val = 0x3200;
  122. val = VpuReadReg(coreIdx, DBG_CONFIG_REPORT_0);
  123. pstr = (char*)&val;
  124. pAttr->productName[0] = pstr[3];
  125. pAttr->productName[1] = pstr[2];
  126. pAttr->productName[2] = pstr[1];
  127. pAttr->productName[3] = pstr[0];
  128. pAttr->productName[4] = 0;
  129. pAttr->supportDecoders = (1<<STD_AVC) |
  130. (1<<STD_VC1) |
  131. (1<<STD_MPEG2) |
  132. (1<<STD_MPEG4) |
  133. (1<<STD_H263) |
  134. (1<<STD_AVS) |
  135. (1<<STD_DIV3) |
  136. (1<<STD_RV) |
  137. (1<<STD_THO) |
  138. (1<<STD_VP8);
  139. /* Encoder */
  140. pAttr->supportEncoders = (1<<STD_AVC) | (1<<STD_MPEG4) | (1<<STD_H263);
  141. /* WTL */
  142. if (productId == PRODUCT_ID_960 || productId == PRODUCT_ID_980) {
  143. pAttr->supportWTL = 1;
  144. }
  145. /* Tiled2Linear */
  146. pAttr->supportTiled2Linear = 1;
  147. /* Maptypes */
  148. pAttr->supportMapTypes = (1<<LINEAR_FRAME_MAP) |
  149. (1<<TILED_FRAME_V_MAP) |
  150. (1<<TILED_FRAME_H_MAP) |
  151. (1<<TILED_FIELD_V_MAP) |
  152. (1<<TILED_MIXED_V_MAP) |
  153. (1<<TILED_FRAME_MB_RASTER_MAP) |
  154. (1<<TILED_FIELD_MB_RASTER_MAP);
  155. if (productId == PRODUCT_ID_980) {
  156. pAttr->supportMapTypes |= (1<<TILED_FRAME_NO_BANK_MAP) |
  157. (1<<TILED_FIELD_NO_BANK_MAP);
  158. }
  159. /* Linear2Tiled */
  160. if (productId == PRODUCT_ID_960 || productId == PRODUCT_ID_980) {
  161. pAttr->supportLinear2Tiled = 1;
  162. }
  163. /* Framebuffer Cache */
  164. if (productId == PRODUCT_ID_960)
  165. pAttr->framebufferCacheType = FramebufCacheMaverickI;
  166. else if (productId == PRODUCT_ID_980)
  167. pAttr->framebufferCacheType = FramebufCacheMaverickII;
  168. else
  169. pAttr->framebufferCacheType = FramebufCacheNone;
  170. /* AXI 128bit Bus */
  171. pAttr->support128bitBus = FALSE;
  172. pAttr->supportEndianMask = (1<<VDI_LITTLE_ENDIAN) | (1<<VDI_BIG_ENDIAN) | (1<<VDI_32BIT_LITTLE_ENDIAN) | (1<<VDI_32BIT_BIG_ENDIAN);
  173. pAttr->supportBitstreamMode = (1<<BS_MODE_INTERRUPT) | (1<<BS_MODE_PIC_END);
  174. pAttr->bitstreamBufferMargin = VPU_GBU_SIZE;
  175. pAttr->numberOfMemProtectRgns = 6;
  176. }
  177. Uint32 Coda9VpuGetProductId(Uint32 coreIdx)
  178. {
  179. Uint32 productId;
  180. Uint32 val;
  181. val = VpuReadReg(coreIdx, VPU_PRODUCT_CODE_REGISTER);
  182. if (val == BODA950_CODE)
  183. productId = PRODUCT_ID_950;
  184. else if (val == CODA960_CODE)
  185. productId = PRODUCT_ID_960;
  186. else if (val == CODA980_CODE)
  187. productId = PRODUCT_ID_980;
  188. else
  189. productId = PRODUCT_ID_NONE;
  190. if (productId != PRODUCT_ID_NONE)
  191. SetupCoda9Properties(coreIdx, productId);
  192. return productId;
  193. }
  194. RetCode Coda9VpuGetVersion(Uint32 coreIdx, Uint32* versionInfo, Uint32* revision)
  195. {
  196. /* Get Firmware version */
  197. VpuWriteReg(coreIdx, RET_FW_VER_NUM , 0);
  198. Coda9BitIssueCommand(coreIdx, NULL, FIRMWARE_GET);
  199. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1)
  200. return RETCODE_VPU_RESPONSE_TIMEOUT;
  201. if (versionInfo != NULL) {
  202. *versionInfo = VpuReadReg(coreIdx, RET_FW_VER_NUM);
  203. }
  204. if (revision != NULL) {
  205. *revision = VpuReadReg(coreIdx, RET_FW_CODE_REV);
  206. }
  207. return RETCODE_SUCCESS;
  208. }
  209. RetCode Coda9VpuInit(Uint32 coreIdx, void* firmware, Uint32 size)
  210. {
  211. Uint32 data;
  212. vpu_buffer_t vb;
  213. PhysicalAddress tempBuffer;
  214. PhysicalAddress paraBuffer;
  215. PhysicalAddress codeBuffer;
  216. vdi_get_common_memory((unsigned long)coreIdx, &vb);
  217. codeBuffer = vb.phys_addr;
  218. tempBuffer = codeBuffer + CODE_BUF_SIZE;
  219. paraBuffer = tempBuffer + TEMP_BUF_SIZE;
  220. BitLoadFirmware(coreIdx, codeBuffer, (const Uint16 *)firmware, size);
  221. /* Clear registers */
  222. if (vdi_read_register(coreIdx, BIT_CUR_PC) == 0) {
  223. Uint32 i;
  224. for (i=0; i<64; i++) {
  225. vdi_write_register(coreIdx, (i*4) + 0x100, 0x0);
  226. }
  227. }
  228. VpuWriteReg(coreIdx, BIT_PARA_BUF_ADDR, paraBuffer);
  229. VpuWriteReg(coreIdx, BIT_CODE_BUF_ADDR, codeBuffer);
  230. VpuWriteReg(coreIdx, BIT_TEMP_BUF_ADDR, tempBuffer);
  231. VpuWriteReg(coreIdx, BIT_BIT_STREAM_CTRL, VPU_STREAM_ENDIAN);
  232. VpuWriteReg(coreIdx, BIT_FRAME_MEM_CTRL, CBCR_INTERLEAVE<<2|VPU_FRAME_ENDIAN); // Interleave bit position is modified
  233. VpuWriteReg(coreIdx, BIT_BIT_STREAM_PARAM, 0);
  234. VpuWriteReg(coreIdx, BIT_AXI_SRAM_USE, 0);
  235. VpuWriteReg(coreIdx, BIT_INT_ENABLE, 0);
  236. VpuWriteReg(coreIdx, BIT_ROLLBACK_STATUS, 0);
  237. data = (1<<INT_BIT_BIT_BUF_FULL);
  238. data |= (1<<INT_BIT_BIT_BUF_EMPTY);
  239. data |= (1<<INT_BIT_DEC_MB_ROWS);
  240. data |= (1<<INT_BIT_SEQ_INIT);
  241. data |= (1<<INT_BIT_DEC_FIELD);
  242. data |= (1<<INT_BIT_PIC_RUN);
  243. VpuWriteReg(coreIdx, BIT_INT_ENABLE, data);
  244. VpuWriteReg(coreIdx, BIT_INT_CLEAR, 0x1);
  245. VpuWriteReg(coreIdx, BIT_BUSY_FLAG, 0x1);
  246. VpuWriteReg(coreIdx, BIT_CODE_RESET, 1);
  247. VpuWriteReg(coreIdx, BIT_CODE_RUN, 1);
  248. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1)
  249. return RETCODE_VPU_RESPONSE_TIMEOUT;
  250. return RETCODE_SUCCESS;
  251. }
  252. RetCode Coda9VpuReInit(Uint32 coreIdx, void* firmware, Uint32 size)
  253. {
  254. vpu_buffer_t vb;
  255. PhysicalAddress tempBuffer;
  256. PhysicalAddress paraBuffer;
  257. PhysicalAddress codeBuffer;
  258. PhysicalAddress oldCodeBuffer;
  259. vdi_get_common_memory((unsigned long)coreIdx, &vb);
  260. codeBuffer = vb.phys_addr;
  261. tempBuffer = codeBuffer + CODE_BUF_SIZE;
  262. paraBuffer = tempBuffer + TEMP_BUF_SIZE;
  263. oldCodeBuffer = VpuReadReg(coreIdx, BIT_CODE_BUF_ADDR);
  264. VpuWriteReg(coreIdx, BIT_PARA_BUF_ADDR, paraBuffer);
  265. VpuWriteReg(coreIdx, BIT_CODE_BUF_ADDR, codeBuffer);
  266. VpuWriteReg(coreIdx, BIT_TEMP_BUF_ADDR, tempBuffer);
  267. if (oldCodeBuffer != codeBuffer) {
  268. LoadBitCode(coreIdx, codeBuffer, (const Uint16 *)firmware, size);
  269. }
  270. return RETCODE_SUCCESS;
  271. }
  272. Uint32 Coda9VpuIsInit(Uint32 coreIdx)
  273. {
  274. Uint32 pc;
  275. pc = VpuReadReg(coreIdx, BIT_CUR_PC);
  276. return pc;
  277. }
  278. Int32 Coda9VpuIsBusy(Uint32 coreIdx)
  279. {
  280. return VpuReadReg(coreIdx, BIT_BUSY_FLAG);
  281. }
  282. Int32 Coda9VpuWaitInterrupt(CodecInst* handle, Int32 timeout)
  283. {
  284. Int32 reason = 0;
  285. #ifdef SUPPORT_MULTI_INST_INTR
  286. reason = vdi_wait_interrupt(handle->coreIdx, 0, timeout);
  287. #else
  288. reason = vdi_wait_interrupt(handle->coreIdx, timeout);
  289. #endif
  290. if (reason != INTERRUPT_TIMEOUT_VALUE) {
  291. VpuWriteReg(handle->coreIdx, BIT_INT_CLEAR, 1); // clear HW signal
  292. }
  293. return reason;
  294. }
  295. RetCode Coda9VpuClearInterrupt(Uint32 coreIdx)
  296. {
  297. VpuWriteReg(coreIdx, BIT_INT_REASON, 0); // tell to F/W that HOST received an interrupt.
  298. return RETCODE_SUCCESS;
  299. }
  300. RetCode Coda9VpuReset(Uint32 coreIdx, SWResetMode resetMode)
  301. {
  302. Uint32 cmd;
  303. Int32 productId = Coda9VpuGetProductId(coreIdx);
  304. if (productId == PRODUCT_ID_960 || productId == PRODUCT_ID_980) {
  305. if (resetMode != SW_RESET_ON_BOOT) {
  306. cmd = VpuReadReg(coreIdx, BIT_RUN_COMMAND);
  307. if (cmd == DEC_SEQ_INIT || cmd == PIC_RUN) {
  308. if (VpuReadReg(coreIdx, BIT_BUSY_FLAG) || VpuReadReg(coreIdx, BIT_INT_REASON)) {
  309. #define MBC_SET_SUBBLK_EN (MBC_BASE+0xA0) // subblk_man_mode[20] cr_subblk_man_en[19:0]
  310. // stop all of pipeline
  311. VpuWriteReg(coreIdx, MBC_SET_SUBBLK_EN, ((1<<20) | 0));
  312. // force to set the end of Bitstream to be decoded.
  313. cmd = VpuReadReg(coreIdx, BIT_BIT_STREAM_PARAM);
  314. cmd |= 1 << 2;
  315. VpuWriteReg(coreIdx, BIT_BIT_STREAM_PARAM, cmd);
  316. cmd = VpuReadReg(coreIdx, BIT_RD_PTR);
  317. VpuWriteReg(coreIdx, BIT_WR_PTR, cmd);
  318. #ifdef SUPPORT_MULTI_INST_INTR
  319. cmd = vdi_wait_interrupt(coreIdx, 0, __VPU_BUSY_TIMEOUT);
  320. #else
  321. cmd = vdi_wait_interrupt(coreIdx, __VPU_BUSY_TIMEOUT);
  322. #endif
  323. if ((Int32)cmd != INTERRUPT_TIMEOUT_VALUE) {
  324. VpuWriteReg(coreIdx, BIT_INT_REASON, 0);
  325. VpuWriteReg(coreIdx, BIT_INT_CLEAR, 1); // clear HW signal
  326. }
  327. // now all of hardwares would be stop.
  328. }
  329. }
  330. }
  331. // Waiting for completion of BWB transaction first
  332. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, GDI_BWB_STATUS) == -1) {
  333. vdi_log(coreIdx, 0x10, 2);
  334. return RETCODE_VPU_RESPONSE_TIMEOUT;
  335. }
  336. // Waiting for completion of bus transaction
  337. // Step1 : No more request
  338. VpuWriteReg(coreIdx, GDI_BUS_CTRL, 0x11); // no more request {3'b0,no_more_req_sec,3'b0,no_more_req}
  339. // Step2 : Waiting for completion of bus transaction
  340. if (vdi_wait_bus_busy(coreIdx, __VPU_BUSY_TIMEOUT, GDI_BUS_STATUS) == -1) {
  341. VpuWriteReg(coreIdx, GDI_BUS_CTRL, 0x00);
  342. vdi_log(coreIdx, 0x10, 2);
  343. return RETCODE_VPU_RESPONSE_TIMEOUT;
  344. }
  345. cmd = 0;
  346. // Software Reset Trigger
  347. if (resetMode != SW_RESET_ON_BOOT)
  348. cmd = VPU_SW_RESET_BPU_CORE | VPU_SW_RESET_BPU_BUS;
  349. cmd |= VPU_SW_RESET_VCE_CORE | VPU_SW_RESET_VCE_BUS;
  350. if (resetMode == SW_RESET_ON_BOOT)
  351. cmd |= VPU_SW_RESET_GDI_CORE | VPU_SW_RESET_GDI_BUS;// If you reset GDI, tiled map should be reconfigured
  352. VpuWriteReg(coreIdx, BIT_SW_RESET, cmd);
  353. // wait until reset is done
  354. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, BIT_SW_RESET_STATUS) == -1) {
  355. VpuWriteReg(coreIdx, BIT_SW_RESET, 0x00);
  356. VpuWriteReg(coreIdx, GDI_BUS_CTRL, 0x00);
  357. vdi_log(coreIdx, 0x10, 2);
  358. return RETCODE_VPU_RESPONSE_TIMEOUT;
  359. }
  360. VpuWriteReg(coreIdx, BIT_SW_RESET, 0);
  361. // Step3 : must clear GDI_BUS_CTRL after done SW_RESET
  362. VpuWriteReg(coreIdx, GDI_BUS_CTRL, 0x00);
  363. }
  364. else {
  365. vdi_log(coreIdx, 0x10, 0);
  366. return RETCODE_NOT_FOUND_VPU_DEVICE;
  367. }
  368. return RETCODE_SUCCESS;
  369. }
  370. RetCode Coda9VpuSleepWake(Uint32 coreIdx, int iSleepWake, const Uint16* code, Uint32 size)
  371. {
  372. static unsigned int regBk[64];
  373. int i=0;
  374. const Uint16* bit_code = NULL;
  375. if (code && size > 0)
  376. bit_code = code;
  377. if (!bit_code)
  378. return RETCODE_INVALID_PARAM;
  379. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1) {
  380. return RETCODE_VPU_RESPONSE_TIMEOUT;
  381. }
  382. if(iSleepWake==1)
  383. {
  384. for ( i = 0 ; i < 64 ; i++)
  385. regBk[i] = VpuReadReg(coreIdx, BIT_BASE + 0x100 + (i * 4));
  386. }
  387. else
  388. {
  389. VpuWriteReg(coreIdx, BIT_CODE_RUN, 0);
  390. for ( i = 0 ; i < 64 ; i++)
  391. VpuWriteReg(coreIdx, BIT_BASE + 0x100 + (i * 4), regBk[i]);
  392. VpuWriteReg(coreIdx, BIT_BUSY_FLAG, 1);
  393. VpuWriteReg(coreIdx, BIT_CODE_RESET, 1);
  394. VpuWriteReg(coreIdx, BIT_CODE_RUN, 1);
  395. if (vdi_wait_vpu_busy(coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1) {
  396. return RETCODE_VPU_RESPONSE_TIMEOUT;
  397. }
  398. }
  399. return RETCODE_SUCCESS;
  400. }
  401. static RetCode SetupDecCodecInstance(Int32 productId, CodecInst* pCodec)
  402. {
  403. DecInfo* pDecInfo = &pCodec->CodecInfo->decInfo;
  404. pDecInfo->streamRdPtrRegAddr = BIT_RD_PTR;
  405. pDecInfo->streamWrPtrRegAddr = BIT_WR_PTR;
  406. pDecInfo->frameDisplayFlagRegAddr = BIT_FRM_DIS_FLG;
  407. pDecInfo->currentPC = BIT_CUR_PC;
  408. pDecInfo->busyFlagAddr = BIT_BUSY_FLAG;
  409. if (productId == PRODUCT_ID_960) {
  410. pDecInfo->dramCfg.rasBit = EM_RAS;
  411. pDecInfo->dramCfg.casBit = EM_CAS;
  412. pDecInfo->dramCfg.bankBit = EM_BANK;
  413. pDecInfo->dramCfg.busBit = EM_WIDTH;
  414. }
  415. return RETCODE_SUCCESS;
  416. }
  417. static RetCode SetupEncCodecInstance(Int32 productId, CodecInst* pCodec)
  418. {
  419. EncInfo* pEncInfo = &pCodec->CodecInfo->encInfo;
  420. pEncInfo->streamRdPtrRegAddr = BIT_RD_PTR;
  421. pEncInfo->streamWrPtrRegAddr = BIT_WR_PTR;
  422. pEncInfo->currentPC = BIT_CUR_PC;
  423. pEncInfo->busyFlagAddr = BIT_BUSY_FLAG;
  424. if (productId == PRODUCT_ID_960) {
  425. pEncInfo->dramCfg.rasBit = EM_RAS;
  426. pEncInfo->dramCfg.casBit = EM_CAS;
  427. pEncInfo->dramCfg.bankBit = EM_BANK;
  428. pEncInfo->dramCfg.busBit = EM_WIDTH;
  429. }
  430. return RETCODE_SUCCESS;
  431. }
  432. RetCode Coda9VpuBuildUpDecParam(CodecInst* pCodec, DecOpenParam* param)
  433. {
  434. RetCode ret = RETCODE_SUCCESS;
  435. Uint32 coreIdx;
  436. Uint32 productId;
  437. DecInfo* pDecInfo = &pCodec->CodecInfo->decInfo;
  438. coreIdx = pCodec->coreIdx;
  439. productId = Coda9VpuGetProductId(coreIdx);
  440. if ((ret=SetupDecCodecInstance(productId, pCodec)) != RETCODE_SUCCESS)
  441. return ret;
  442. if (param->vbWork.size) {
  443. pDecInfo->vbWork = param->vbWork;
  444. pDecInfo->workBufferAllocExt = 1;
  445. }
  446. else {
  447. pDecInfo->vbWork.size = WORK_BUF_SIZE;
  448. if (pCodec->codecMode == AVC_DEC)
  449. pDecInfo->vbWork.size += PS_SAVE_SIZE;
  450. if (vdi_allocate_dma_memory(pCodec->coreIdx, &pDecInfo->vbWork, DEC_WORK, pCodec->instIndex) < 0)
  451. return RETCODE_INSUFFICIENT_RESOURCE;
  452. param->vbWork = pDecInfo->vbWork;
  453. pDecInfo->workBufferAllocExt = 0;
  454. }
  455. if (productId == PRODUCT_ID_960) {
  456. pDecInfo->dramCfg.bankBit = EM_BANK;
  457. pDecInfo->dramCfg.casBit = EM_CAS;
  458. pDecInfo->dramCfg.rasBit = EM_RAS;
  459. pDecInfo->dramCfg.busBit = EM_WIDTH;
  460. }
  461. return ret;
  462. }
  463. RetCode Coda9VpuDecInitSeq(DecHandle handle)
  464. {
  465. CodecInst* pCodecInst = (CodecInst*)handle;
  466. DecInfo* pDecInfo = &pCodecInst->CodecInfo->decInfo;
  467. Uint32 val = 0;
  468. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_BB_START, pDecInfo->streamBufStartAddr);
  469. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_BB_SIZE, pDecInfo->streamBufSize / 1024); // size in KBytes
  470. if(pDecInfo->userDataEnable == TRUE) {
  471. val = 0;
  472. val |= (pDecInfo->userDataReportMode << 10);
  473. val |= (pDecInfo->userDataEnable << 5);
  474. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_USER_DATA_OPTION, val);
  475. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_USER_DATA_BASE_ADDR, pDecInfo->userDataBufAddr);
  476. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_USER_DATA_BUF_SIZE, pDecInfo->userDataBufSize);
  477. }
  478. else {
  479. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_USER_DATA_OPTION, 0);
  480. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_USER_DATA_BASE_ADDR, 0);
  481. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_USER_DATA_BUF_SIZE, 0);
  482. }
  483. val = 0;
  484. val |= (pDecInfo->reorderEnable<<1) & 0x2;
  485. val |= (pDecInfo->openParam.mp4DeblkEnable & 0x1);
  486. val |= (pDecInfo->avcErrorConcealMode << 2);
  487. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_OPTION, val);
  488. switch(pCodecInst->codecMode) {
  489. case VC1_DEC:
  490. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_VC1_STREAM_FMT, (0 << 3) & 0x08);
  491. break;
  492. case MP4_DEC:
  493. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_MP4_ASP_CLASS, (VPU_GMC_PROCESS_METHOD<<3)|pDecInfo->openParam.mp4Class);
  494. break;
  495. case AVC_DEC:
  496. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_X264_MV_EN, VPU_AVC_X264_SUPPORT);
  497. break;
  498. }
  499. if( pCodecInst->codecMode == AVC_DEC )
  500. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_SEQ_SPP_CHUNK_SIZE, VPU_GBU_SIZE);
  501. VpuWriteReg(pCodecInst->coreIdx, pDecInfo->streamWrPtrRegAddr, pDecInfo->streamWrPtr);
  502. VpuWriteReg(pCodecInst->coreIdx, pDecInfo->streamRdPtrRegAddr, pDecInfo->streamRdPtr);
  503. if (pCodecInst->productId == PRODUCT_ID_980 || pCodecInst->productId == PRODUCT_ID_960) {
  504. pDecInfo->streamEndflag &= ~(3<<3);
  505. if (pDecInfo->openParam.bitstreamMode == BS_MODE_PIC_END)
  506. pDecInfo->streamEndflag |= (2<<3);
  507. else { // Interrupt Mode
  508. if (pDecInfo->seqInitEscape) {
  509. pDecInfo->streamEndflag |= (2<<3);
  510. }
  511. }
  512. }
  513. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_PARAM, pDecInfo->streamEndflag);
  514. val = pDecInfo->openParam.streamEndian;
  515. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_CTRL, val);
  516. if (pCodecInst->productId == PRODUCT_ID_980) {
  517. val = 0;
  518. val |= (pDecInfo->openParam.bwbEnable<<15);
  519. val |= (pDecInfo->wtlMode<<17)|(pDecInfo->tiled2LinearMode<<13)|(FORMAT_420<<6);
  520. val |= ((pDecInfo->openParam.cbcrInterleave)<<2); // Interleave bit position is modified
  521. val |= pDecInfo->openParam.frameEndian;
  522. VpuWriteReg(pCodecInst->coreIdx, BIT_FRAME_MEM_CTRL, val);
  523. }
  524. else if (pCodecInst->productId == PRODUCT_ID_960) {
  525. val = 0;
  526. val |= (pDecInfo->wtlEnable<<17);
  527. val |= (pDecInfo->openParam.bwbEnable<<12);
  528. val |= ((pDecInfo->openParam.cbcrInterleave)<<2); // Interleave bit position is modified
  529. val |= pDecInfo->openParam.frameEndian;
  530. VpuWriteReg(pCodecInst->coreIdx, BIT_FRAME_MEM_CTRL, val);
  531. }
  532. else {
  533. return RETCODE_NOT_FOUND_VPU_DEVICE;
  534. }
  535. VpuWriteReg(pCodecInst->coreIdx, pDecInfo->frameDisplayFlagRegAddr, 0);
  536. Coda9BitIssueCommand(pCodecInst->coreIdx, pCodecInst, DEC_SEQ_INIT);
  537. return RETCODE_SUCCESS;
  538. }
  539. RetCode Coda9VpuFiniSeq(CodecInst* instance)
  540. {
  541. Coda9BitIssueCommand(instance->coreIdx, instance, DEC_SEQ_END);
  542. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1) {
  543. return RETCODE_VPU_RESPONSE_TIMEOUT;
  544. }
  545. return RETCODE_SUCCESS;
  546. }
  547. RetCode Coda9VpuDecode(CodecInst* instance, DecParam* param)
  548. {
  549. CodecInst* pCodecInst;
  550. DecInfo* pDecInfo;
  551. Uint32 rotMir;
  552. Int32 val;
  553. vpu_instance_pool_t *vip;
  554. pCodecInst = instance;
  555. pDecInfo = &pCodecInst->CodecInfo->decInfo;
  556. vip = (vpu_instance_pool_t *)vdi_get_instance_pool(pCodecInst->coreIdx);
  557. if (!vip) {
  558. return RETCODE_INVALID_HANDLE;
  559. }
  560. rotMir = 0;
  561. if (pDecInfo->rotationEnable) {
  562. rotMir |= 0x10; // Enable rotator
  563. switch (pDecInfo->rotationAngle) {
  564. case 0:
  565. rotMir |= 0x0;
  566. break;
  567. case 90:
  568. rotMir |= 0x1;
  569. break;
  570. case 180:
  571. rotMir |= 0x2;
  572. break;
  573. case 270:
  574. rotMir |= 0x3;
  575. break;
  576. }
  577. }
  578. if (pDecInfo->mirrorEnable) {
  579. rotMir |= 0x10; // Enable rotator
  580. switch (pDecInfo->mirrorDirection) {
  581. case MIRDIR_NONE :
  582. rotMir |= 0x0;
  583. break;
  584. case MIRDIR_VER :
  585. rotMir |= 0x4;
  586. break;
  587. case MIRDIR_HOR :
  588. rotMir |= 0x8;
  589. break;
  590. case MIRDIR_HOR_VER :
  591. rotMir |= 0xc;
  592. break;
  593. }
  594. }
  595. if (pDecInfo->tiled2LinearEnable) {
  596. rotMir |= 0x10;
  597. }
  598. if (pDecInfo->deringEnable) {
  599. rotMir |= 0x20; // Enable Dering Filter
  600. }
  601. if (rotMir && !pDecInfo->rotatorOutputValid) {
  602. return RETCODE_ROTATOR_OUTPUT_NOT_SET;
  603. }
  604. VpuWriteReg(pCodecInst->coreIdx, RET_DEC_PIC_CROP_LEFT_RIGHT, 0); // frame crop information(left, right)
  605. VpuWriteReg(pCodecInst->coreIdx, RET_DEC_PIC_CROP_TOP_BOTTOM, 0); // frame crop information(top, bottom)
  606. if (pCodecInst->productId == PRODUCT_ID_960) {
  607. if (pDecInfo->mapType>LINEAR_FRAME_MAP && pDecInfo->mapType<=TILED_MIXED_V_MAP) {
  608. SetTiledFrameBase(pCodecInst->coreIdx, pDecInfo->mapCfg.tiledBaseAddr);
  609. }
  610. else {
  611. SetTiledFrameBase(pCodecInst->coreIdx, 0);
  612. }
  613. }
  614. if (pDecInfo->mapType != LINEAR_FRAME_MAP && pDecInfo->mapType != LINEAR_FIELD_MAP) {
  615. val = SetTiledMapType(pCodecInst->coreIdx, &pDecInfo->mapCfg, pDecInfo->mapType,
  616. (pDecInfo->stride > pDecInfo->frameBufferHeight)?pDecInfo->stride: pDecInfo->frameBufferHeight,
  617. pDecInfo->openParam.cbcrInterleave, &pDecInfo->dramCfg);
  618. } else {
  619. val = SetTiledMapType(pCodecInst->coreIdx, &pDecInfo->mapCfg, pDecInfo->mapType,
  620. pDecInfo->stride, pDecInfo->openParam.cbcrInterleave, &pDecInfo->dramCfg);
  621. }
  622. if (val == 0) {
  623. return RETCODE_INVALID_PARAM;
  624. }
  625. if (rotMir & 0x30) { // rotator or dering or tiled2linear enabled
  626. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_MODE, rotMir);
  627. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_INDEX, pDecInfo->rotatorOutput.myIndex);
  628. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_ADDR_Y, pDecInfo->rotatorOutput.bufY);
  629. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_ADDR_CB, pDecInfo->rotatorOutput.bufCb);
  630. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_ADDR_CR, pDecInfo->rotatorOutput.bufCr);
  631. if (pCodecInst->productId == PRODUCT_ID_980) {
  632. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_BOTTOM_Y, pDecInfo->rotatorOutput.bufYBot);
  633. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_BOTTOM_CB, pDecInfo->rotatorOutput.bufCbBot);
  634. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_BOTTOM_CR, pDecInfo->rotatorOutput.bufCrBot);
  635. }
  636. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_STRIDE, pDecInfo->rotatorStride);
  637. }
  638. else {
  639. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_ROT_MODE, rotMir);
  640. }
  641. if(pDecInfo->userDataEnable) {
  642. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_USER_DATA_BASE_ADDR, pDecInfo->userDataBufAddr);
  643. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_USER_DATA_BUF_SIZE, pDecInfo->userDataBufSize);
  644. }
  645. else {
  646. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_USER_DATA_BASE_ADDR, 0);
  647. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_USER_DATA_BUF_SIZE, 0);
  648. }
  649. val = 0;
  650. if (param->iframeSearchEnable == TRUE) { // if iframeSearch is Enable, other bit is ignore;
  651. val |= (pDecInfo->userDataReportMode <<10);
  652. if (pCodecInst->codecMode == AVC_DEC || pCodecInst->codecMode == VC1_DEC) {
  653. if (param->iframeSearchEnable==1)
  654. val |= (1<< 11) | (1<<2);
  655. else if (param->iframeSearchEnable==2)
  656. val |= (1<<2);
  657. }
  658. else {
  659. val |= (( param->iframeSearchEnable &0x1) << 2 );
  660. }
  661. }
  662. else {
  663. val |= (pDecInfo->userDataReportMode <<10);
  664. val |= (pDecInfo->userDataEnable << 5);
  665. val |= (param->skipframeMode << 3);
  666. }
  667. if (pCodecInst->productId == PRODUCT_ID_980) {
  668. if (pCodecInst->codecMode == AVC_DEC && pDecInfo->lowDelayInfo.lowDelayEn) {
  669. val |= (pDecInfo->lowDelayInfo.lowDelayEn <<18 );
  670. }
  671. }
  672. if (pCodecInst->codecMode == MP2_DEC) {
  673. val |= ((param->DecStdParam.mp2PicFlush&1)<<15);
  674. }
  675. if (pCodecInst->codecMode == RV_DEC) {
  676. val |= ((param->DecStdParam.rvDbkMode&0x0f)<<16);
  677. }
  678. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_OPTION, val);
  679. if (pCodecInst->productId == PRODUCT_ID_980) {
  680. if (pDecInfo->lowDelayInfo.lowDelayEn == TRUE) {
  681. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_NUM_ROWS, pDecInfo->lowDelayInfo.numRows);
  682. }
  683. else {
  684. VpuWriteReg(pCodecInst->coreIdx, CMD_DEC_PIC_NUM_ROWS, 0);
  685. }
  686. }
  687. val = 0;
  688. val = (
  689. (pDecInfo->secAxiInfo.u.coda9.useBitEnable&0x01)<<0 |
  690. (pDecInfo->secAxiInfo.u.coda9.useIpEnable&0x01)<<1 |
  691. (pDecInfo->secAxiInfo.u.coda9.useDbkYEnable&0x01)<<2 |
  692. (pDecInfo->secAxiInfo.u.coda9.useDbkCEnable&0x01)<<3 |
  693. (pDecInfo->secAxiInfo.u.coda9.useOvlEnable&0x01)<<4 |
  694. (pDecInfo->secAxiInfo.u.coda9.useBtpEnable&0x01)<<5 |
  695. (pDecInfo->secAxiInfo.u.coda9.useBitEnable&0x01)<<8 |
  696. (pDecInfo->secAxiInfo.u.coda9.useIpEnable&0x01)<<9 |
  697. (pDecInfo->secAxiInfo.u.coda9.useDbkYEnable&0x01)<<10 |
  698. (pDecInfo->secAxiInfo.u.coda9.useDbkCEnable&0x01)<<11 |
  699. (pDecInfo->secAxiInfo.u.coda9.useOvlEnable&0x01)<<12 |
  700. (pDecInfo->secAxiInfo.u.coda9.useBtpEnable&0x01)<<13 );
  701. VpuWriteReg(pCodecInst->coreIdx, BIT_AXI_SRAM_USE, val);
  702. VpuWriteReg(pCodecInst->coreIdx, pDecInfo->streamWrPtrRegAddr, pDecInfo->streamWrPtr);
  703. VpuWriteReg(pCodecInst->coreIdx, pDecInfo->streamRdPtrRegAddr, pDecInfo->streamRdPtr);
  704. pDecInfo->streamEndflag &= ~(3<<3);
  705. if (pDecInfo->openParam.bitstreamMode == BS_MODE_PIC_END)
  706. pDecInfo->streamEndflag |= (2<<3);
  707. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_PARAM, pDecInfo->streamEndflag);
  708. if (pCodecInst->productId == PRODUCT_ID_980) {
  709. val = 0;
  710. val |= (pDecInfo->openParam.bwbEnable<<15);
  711. val |= (pDecInfo->wtlMode<<17)|(pDecInfo->tiled2LinearMode<<13)|(pDecInfo->mapType<<9)|(FORMAT_420<<6);
  712. }
  713. else if (pCodecInst->productId == PRODUCT_ID_960) {
  714. val = 0;
  715. val |= (pDecInfo->wtlEnable<<17);
  716. val |= (pDecInfo->openParam.bwbEnable<<12);
  717. if (pDecInfo->mapType) {
  718. if (pDecInfo->mapType == TILED_FRAME_MB_RASTER_MAP || pDecInfo->mapType == TILED_FIELD_MB_RASTER_MAP)
  719. val |= (pDecInfo->tiled2LinearEnable<<11)|(0x03<<9)|(FORMAT_420<<6);
  720. else
  721. val |= (pDecInfo->tiled2LinearEnable<<11)|(0x02<<9)|(FORMAT_420<<6);
  722. }
  723. }
  724. else {
  725. return RETCODE_NOT_FOUND_VPU_DEVICE;
  726. }
  727. val |= ((pDecInfo->openParam.cbcrInterleave)<<2); // Interleave bit position is modified
  728. val |= pDecInfo->openParam.frameEndian;
  729. VpuWriteReg(pCodecInst->coreIdx, BIT_FRAME_MEM_CTRL, val);
  730. val = pDecInfo->openParam.streamEndian;
  731. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_CTRL, val);
  732. Coda9BitIssueCommand(pCodecInst->coreIdx, pCodecInst, PIC_RUN);
  733. return RETCODE_SUCCESS;
  734. }
  735. RetCode Coda9VpuDecGetResult(CodecInst* instance, DecOutputInfo* result)
  736. {
  737. CodecInst* pCodecInst;
  738. DecInfo* pDecInfo;
  739. Uint32 val = 0;
  740. pCodecInst = instance;
  741. pDecInfo = &pCodecInst->CodecInfo->decInfo;
  742. if (pCodecInst->loggingEnable)
  743. vdi_log(pCodecInst->coreIdx, PIC_RUN, 0);
  744. result->warnInfo = 0;
  745. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_SUCCESS);
  746. result->decodingSuccess = val;
  747. if (result->decodingSuccess & (1UL<<31)) {
  748. return RETCODE_MEMORY_ACCESS_VIOLATION;
  749. }
  750. if( pCodecInst->codecMode == AVC_DEC ) {
  751. result->notSufficientPsBuffer = (val >> 3) & 0x1;
  752. result->notSufficientSliceBuffer = (val >> 2) & 0x1;
  753. result->refMissingFrameFlag = (val>>21) & 0x1;
  754. }
  755. result->chunkReuseRequired = 0;
  756. if (pDecInfo->openParam.bitstreamMode == BS_MODE_PIC_END) {
  757. switch (pCodecInst->codecMode) {
  758. case AVC_DEC:
  759. result->chunkReuseRequired = ((val >> 16) & 0x01); // in case of NPF frame
  760. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_DECODED_IDX);
  761. if (val == (Uint32)-1) {
  762. result->chunkReuseRequired = TRUE;
  763. }
  764. break;
  765. case MP2_DEC:
  766. case MP4_DEC:
  767. result->chunkReuseRequired = ((val >> 16) & 0x01);
  768. break;
  769. default:
  770. break;
  771. }
  772. }
  773. result->indexFrameDecoded = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_DECODED_IDX);
  774. result->indexFrameDisplay = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_DISPLAY_IDX);
  775. if (pDecInfo->mapType == LINEAR_FRAME_MAP) {
  776. result->indexFrameDecodedForTiled = -1;
  777. result->indexFrameDisplayForTiled = -1;
  778. }
  779. else {
  780. result->indexFrameDecodedForTiled = result->indexFrameDecoded;
  781. result->indexFrameDisplayForTiled = result->indexFrameDisplay;
  782. }
  783. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_SIZE); // decoding picture size
  784. result->decPicWidth = (val>>16) & 0xFFFF;
  785. result->decPicHeight = (val) & 0xFFFF;
  786. if (result->indexFrameDecoded >= 0 && result->indexFrameDecoded < MAX_GDI_IDX) {
  787. switch (pCodecInst->codecMode) {
  788. case VPX_DEC:
  789. if ( pCodecInst->codecModeAux == VPX_AUX_VP8 ) {
  790. // VP8 specific header information
  791. // h_scale[31:30] v_scale[29:28] pic_width[27:14] pic_height[13:0]
  792. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_VP8_SCALE_INFO);
  793. result->vp8ScaleInfo.hScaleFactor = (val >> 30) & 0x03;
  794. result->vp8ScaleInfo.vScaleFactor = (val >> 28) & 0x03;
  795. result->vp8ScaleInfo.picWidth = (val >> 14) & 0x3FFF;
  796. result->vp8ScaleInfo.picHeight = (val >> 0) & 0x3FFF;
  797. // ref_idx_gold[31:24], ref_idx_altr[23:16], ref_idx_last[15: 8],
  798. // version_number[3:1], show_frame[0]
  799. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_VP8_PIC_REPORT);
  800. result->vp8PicInfo.refIdxGold = (val >> 24) & 0x0FF;
  801. result->vp8PicInfo.refIdxAltr = (val >> 16) & 0x0FF;
  802. result->vp8PicInfo.refIdxLast = (val >> 8) & 0x0FF;
  803. result->vp8PicInfo.versionNumber = (val >> 1) & 0x07;
  804. result->vp8PicInfo.showFrame = (val >> 0) & 0x01;
  805. }
  806. break;
  807. case AVC_DEC:
  808. case AVS_DEC:
  809. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_CROP_LEFT_RIGHT); // frame crop information(left, right)
  810. pDecInfo->initialInfo.picCropRect.left = (val>>16) & 0xffff;
  811. pDecInfo->initialInfo.picCropRect.right = pDecInfo->initialInfo.picWidth - (val&0xffff);
  812. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_CROP_TOP_BOTTOM); // frame crop information(top, bottom)
  813. pDecInfo->initialInfo.picCropRect.top = (val>>16) & 0xffff;
  814. pDecInfo->initialInfo.picCropRect.bottom = pDecInfo->initialInfo.picHeight - (val&0xffff);
  815. break;
  816. case MP2_DEC:
  817. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_MP2_BAR_LEFT_RIGHT);
  818. pDecInfo->initialInfo.mp2BardataInfo.barLeft = ((val>>16) & 0xFFFF);
  819. pDecInfo->initialInfo.mp2BardataInfo.barRight = (val&0xFFFF);
  820. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_MP2_BAR_TOP_BOTTOM);
  821. pDecInfo->initialInfo.mp2BardataInfo.barTop = ((val>>16) & 0xFFFF);
  822. pDecInfo->initialInfo.mp2BardataInfo.barBottom = (val&0xFFFF);
  823. result->mp2BardataInfo = pDecInfo->initialInfo.mp2BardataInfo;
  824. result->mp2PicDispExtInfo.offsetNum = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_MP2_OFFSET_NUM);
  825. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_MP2_OFFSET1);
  826. result->mp2PicDispExtInfo.horizontalOffset1 = (Int16) (val >> 16) & 0xFFFF;
  827. result->mp2PicDispExtInfo.verticalOffset1 = (Int16) (val & 0xFFFF);
  828. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_MP2_OFFSET2);
  829. result->mp2PicDispExtInfo.horizontalOffset2 = (Int16) (val >> 16) & 0xFFFF;
  830. result->mp2PicDispExtInfo.verticalOffset2 = (Int16) (val & 0xFFFF);
  831. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_MP2_OFFSET3);
  832. result->mp2PicDispExtInfo.horizontalOffset3 = (Int16) (val >> 16) & 0xFFFF;
  833. result->mp2PicDispExtInfo.verticalOffset3 = (Int16) (val & 0xFFFF);
  834. break;
  835. }
  836. }
  837. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_TYPE);
  838. result->interlacedFrame = (val >> 18) & 0x1;
  839. result->topFieldFirst = (val >> 21) & 0x0001; // TopFieldFirst[21]
  840. if (result->interlacedFrame) {
  841. result->picTypeFirst = (val & 0x38) >> 3; // pic_type of 1st field
  842. result->picType = val & 7; // pic_type of 2nd field
  843. }
  844. else {
  845. result->picTypeFirst = PIC_TYPE_MAX; // no meaning
  846. result->picType = val & 7;
  847. }
  848. result->pictureStructure = (val >> 19) & 0x0003; // MbAffFlag[17], FieldPicFlag[16]
  849. result->repeatFirstField = (val >> 22) & 0x0001;
  850. result->progressiveFrame = (val >> 23) & 0x0003;
  851. if( pCodecInst->codecMode == AVC_DEC)
  852. {
  853. result->decFrameInfo = (val >> 15) & 0x0001;
  854. result->picStrPresent = (val >> 27) & 0x0001;
  855. result->picTimingStruct = (val >> 28) & 0x000f;
  856. //update picture type when IDR frame
  857. if (val & 0x40) { // 6th bit
  858. if (result->interlacedFrame)
  859. result->picTypeFirst = PIC_TYPE_IDR;
  860. else
  861. result->picType = PIC_TYPE_IDR;
  862. }
  863. result->decFrameInfo = (val >> 16) & 0x0003;
  864. if (result->indexFrameDisplay >= 0) {
  865. if (result->indexFrameDisplay == result->indexFrameDecoded)
  866. result->avcNpfFieldInfo = result->decFrameInfo;
  867. else
  868. result->avcNpfFieldInfo = pDecInfo->decOutInfo[result->indexFrameDisplay].decFrameInfo;
  869. }
  870. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_HRD_INFO);
  871. result->avcHrdInfo.cpbMinus1 = val>>2;
  872. result->avcHrdInfo.vclHrdParamFlag = (val>>1)&1;
  873. result->avcHrdInfo.nalHrdParamFlag = val&1;
  874. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_VUI_INFO);
  875. result->avcVuiInfo.fixedFrameRateFlag = val &1;
  876. result->avcVuiInfo.timingInfoPresent = (val>>1) & 0x01;
  877. result->avcVuiInfo.chromaLocBotField = (val>>2) & 0x07;
  878. result->avcVuiInfo.chromaLocTopField = (val>>5) & 0x07;
  879. result->avcVuiInfo.chromaLocInfoPresent = (val>>8) & 0x01;
  880. result->avcVuiInfo.colorPrimaries = (val>>16) & 0xff;
  881. result->avcVuiInfo.colorDescPresent = (val>>24) & 0x01;
  882. result->avcVuiInfo.isExtSAR = (val>>25) & 0x01;
  883. result->avcVuiInfo.vidFullRange = (val>>26) & 0x01;
  884. result->avcVuiInfo.vidFormat = (val>>27) & 0x07;
  885. result->avcVuiInfo.vidSigTypePresent = (val>>30) & 0x01;
  886. result->avcVuiInfo.vuiParamPresent = (val>>31) & 0x01;
  887. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_VUI_PIC_STRUCT);
  888. result->avcVuiInfo.vuiPicStructPresent = (val & 0x1);
  889. result->avcVuiInfo.vuiPicStruct = (val>>1);
  890. }
  891. if( pCodecInst->codecMode == MP2_DEC)
  892. {
  893. result->fieldSequence = (val >> 25) & 0x0007;
  894. result->frameDct = (val >> 28) & 0x0001;
  895. result->progressiveSequence = (val >> 29) & 0x0001;
  896. }
  897. result->fRateNumerator = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_FRATE_NR); //Frame rate, Aspect ratio can be changed frame by frame.
  898. result->fRateDenominator = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_FRATE_DR);
  899. if (pCodecInst->codecMode == AVC_DEC && result->fRateDenominator > 0)
  900. result->fRateDenominator *= 2;
  901. if (pCodecInst->codecMode == MP4_DEC)
  902. {
  903. result->mp4ModuloTimeBase = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_MODULO_TIME_BASE);
  904. result->mp4TimeIncrement = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_VOP_TIME_INCREMENT);
  905. }
  906. if (pCodecInst->codecMode == RV_DEC) {
  907. result->rvTr = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_RV_TR);
  908. result->rvTrB = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_RV_TR_BFRAME);
  909. }
  910. if (pCodecInst->codecMode == VPX_DEC) {
  911. result->aspectRateInfo = 0;
  912. }
  913. else {
  914. result->aspectRateInfo = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_ASPECT);
  915. }
  916. // User Data
  917. if (pDecInfo->userDataEnable) {
  918. int userDataNum;
  919. int userDataSize;
  920. BYTE tempBuf[8] = {0,};
  921. VpuReadMem(pCodecInst->coreIdx, pDecInfo->userDataBufAddr + 0, tempBuf, 8, VPU_USER_DATA_ENDIAN);
  922. val = ((tempBuf[0]<<24) & 0xFF000000) |
  923. ((tempBuf[1]<<16) & 0x00FF0000) |
  924. ((tempBuf[2]<< 8) & 0x0000FF00) |
  925. ((tempBuf[3]<< 0) & 0x000000FF);
  926. userDataNum = (val >> 16) & 0xFFFF;
  927. userDataSize = (val >> 0) & 0xFFFF;
  928. if (userDataNum == 0)
  929. userDataSize = 0;
  930. result->decOutputExtData.userDataNum = userDataNum;
  931. result->decOutputExtData.userDataSize = userDataSize;
  932. val = ((tempBuf[4]<<24) & 0xFF000000) |
  933. ((tempBuf[5]<<16) & 0x00FF0000) |
  934. ((tempBuf[6]<< 8) & 0x0000FF00) |
  935. ((tempBuf[7]<< 0) & 0x000000FF);
  936. if (userDataNum == 0)
  937. result->decOutputExtData.userDataBufFull = 0;
  938. else
  939. result->decOutputExtData.userDataBufFull = (val >> 16) & 0xFFFF;
  940. result->decOutputExtData.activeFormat = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_ATSC_USER_DATA_INFO)&0xf;
  941. }
  942. result->numOfErrMBs = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_ERR_MB);
  943. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_SUCCESS);
  944. result->sequenceChanged = ((val>>20) & 0x1);
  945. result->streamEndFlag = ((pDecInfo->streamEndflag>>2) & 0x01);
  946. if (pCodecInst->codecMode == VC1_DEC && result->indexFrameDisplay != -3) {
  947. if (pDecInfo->vc1BframeDisplayValid == 0) {
  948. if (result->picType == 2) {
  949. result->indexFrameDisplay = -3;
  950. } else {
  951. pDecInfo->vc1BframeDisplayValid = 1;
  952. }
  953. }
  954. }
  955. if (pCodecInst->codecMode == AVC_DEC && pCodecInst->codecModeAux == AVC_AUX_MVC)
  956. {
  957. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_MVC_REPORT);
  958. result->mvcPicInfo.viewIdxDisplay = (val>>0) & 1;
  959. result->mvcPicInfo.viewIdxDecoded = (val>>1) & 1;
  960. }
  961. if (pCodecInst->codecMode == AVC_DEC)
  962. {
  963. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_AVC_FPA_SEI0);
  964. if ((int)val < 0) {
  965. result->avcFpaSei.exist = 0;
  966. }
  967. else {
  968. result->avcFpaSei.exist = 1;
  969. result->avcFpaSei.framePackingArrangementId = val;
  970. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_AVC_FPA_SEI1);
  971. result->avcFpaSei.contentInterpretationType = val&0x3F; // [5:0]
  972. result->avcFpaSei.framePackingArrangementType = (val >> 6)&0x7F; // [12:6]
  973. result->avcFpaSei.framePackingArrangementExtensionFlag = (val >> 13)&0x01; // [13]
  974. result->avcFpaSei.frame1SelfContainedFlag = (val >> 14)&0x01; // [14]
  975. result->avcFpaSei.frame0SelfContainedFlag = (val >> 15)&0x01; // [15]
  976. result->avcFpaSei.currentFrameIsFrame0Flag = (val >> 16)&0x01; // [16]
  977. result->avcFpaSei.fieldViewsFlag = (val >> 17)&0x01; // [17]
  978. result->avcFpaSei.frame0FlippedFlag = (val >> 18)&0x01; // [18]
  979. result->avcFpaSei.spatialFlippingFlag = (val >> 19)&0x01; // [19]
  980. result->avcFpaSei.quincunxSamplingFlag = (val >> 20)&0x01; // [20]
  981. result->avcFpaSei.framePackingArrangementCancelFlag = (val >> 21)&0x01; // [21]
  982. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_AVC_FPA_SEI2);
  983. result->avcFpaSei.framePackingArrangementRepetitionPeriod = val&0x7FFF; // [14:0]
  984. result->avcFpaSei.frame1GridPositionY = (val >> 16)&0x0F; // [19:16]
  985. result->avcFpaSei.frame1GridPositionX = (val >> 20)&0x0F; // [23:20]
  986. result->avcFpaSei.frame0GridPositionY = (val >> 24)&0x0F; // [27:24]
  987. result->avcFpaSei.frame0GridPositionX = (val >> 28)&0x0F; // [31:28]
  988. }
  989. result->avcPocTop = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_POC_TOP);
  990. result->avcPocBot = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_POC_BOT);
  991. if (result->interlacedFrame)
  992. {
  993. if (result->avcPocTop > result->avcPocBot) {
  994. result->avcPocPic = result->avcPocBot;
  995. } else {
  996. result->avcPocPic = result->avcPocTop;
  997. }
  998. }
  999. else
  1000. result->avcPocPic = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_POC);
  1001. }
  1002. if (pCodecInst->codecMode == AVC_DEC)
  1003. {
  1004. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_PIC_AVC_SEI_RP_INFO);
  1005. if ((int)val < 0) {
  1006. result->avcRpSei.exist = 0;
  1007. }
  1008. else {
  1009. result->avcRpSei.exist = 1;
  1010. result->avcRpSei.changingSliceGroupIdc = val & 0x3; // [1:0]
  1011. result->avcRpSei.brokenLinkFlag = (val >> 2)&0x01; // [2]
  1012. result->avcRpSei.exactMatchFlag = (val >> 3)&0x01; // [3]
  1013. result->avcRpSei.recoveryFrameCnt = (val >> 4)&0x3F; // [9:4]
  1014. }
  1015. }
  1016. result->bytePosFrameStart = VpuReadReg(pCodecInst->coreIdx, BIT_BYTE_POS_FRAME_START);
  1017. result->bytePosFrameEnd = VpuReadReg(pCodecInst->coreIdx, BIT_BYTE_POS_FRAME_END);
  1018. if (result->indexFrameDecoded >= 0 && result->indexFrameDecoded < MAX_GDI_IDX)
  1019. pDecInfo->decOutInfo[result->indexFrameDecoded] = *result;
  1020. result->frameDisplayFlag = pDecInfo->frameDisplayFlag;
  1021. result->frameCycle = VpuReadReg(pCodecInst->coreIdx, BIT_FRAME_CYCLE);
  1022. return RETCODE_SUCCESS;
  1023. }
  1024. RetCode Coda9VpuDecSetBitstreamFlag(CodecInst* instance, BOOL running, BOOL eos)
  1025. {
  1026. Uint32 val;
  1027. DecInfo* pDecInfo;
  1028. pDecInfo = &instance->CodecInfo->decInfo;
  1029. if (eos&0x01) {
  1030. val = VpuReadReg(instance->coreIdx, BIT_BIT_STREAM_PARAM);
  1031. val |= 1 << 2;
  1032. pDecInfo->streamEndflag = val;
  1033. if (running == TRUE)
  1034. VpuWriteReg(instance->coreIdx, BIT_BIT_STREAM_PARAM, val);
  1035. return RETCODE_SUCCESS;
  1036. }
  1037. else {
  1038. val = VpuReadReg(instance->coreIdx, BIT_BIT_STREAM_PARAM);
  1039. val &= ~(1 << 2);
  1040. pDecInfo->streamEndflag = val;
  1041. if (running == TRUE)
  1042. VpuWriteReg(instance->coreIdx, BIT_BIT_STREAM_PARAM, val);
  1043. return RETCODE_SUCCESS;
  1044. }
  1045. }
  1046. RetCode Coda9VpuDecGetSeqInfo(CodecInst* instance, DecInitialInfo* info)
  1047. {
  1048. CodecInst* pCodecInst = NULL;
  1049. DecInfo* pDecInfo = NULL;
  1050. Uint32 val, val2;
  1051. pCodecInst = instance;
  1052. pDecInfo = &pCodecInst->CodecInfo->decInfo;
  1053. if (pCodecInst->loggingEnable) {
  1054. vdi_log(pCodecInst->coreIdx, DEC_SEQ_INIT, 0);
  1055. }
  1056. info->warnInfo = 0;
  1057. if (pDecInfo->openParam.bitstreamMode == BS_MODE_INTERRUPT && pDecInfo->seqInitEscape) {
  1058. pDecInfo->streamEndflag &= ~(3<<3);
  1059. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_PARAM, pDecInfo->streamEndflag);
  1060. pDecInfo->seqInitEscape = 0;
  1061. }
  1062. pDecInfo->streamRdPtr = VpuReadReg(instance->coreIdx, pDecInfo->streamRdPtrRegAddr);
  1063. pDecInfo->frameDisplayFlag = VpuReadReg(pCodecInst->coreIdx, pDecInfo->frameDisplayFlagRegAddr);
  1064. pDecInfo->streamEndflag = VpuReadReg(pCodecInst->coreIdx, BIT_BIT_STREAM_PARAM);
  1065. info->seqInitErrReason = 0;
  1066. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_SUCCESS);
  1067. if (val & (1UL<<31)) {
  1068. return RETCODE_MEMORY_ACCESS_VIOLATION;
  1069. }
  1070. if ( pDecInfo->openParam.bitstreamMode == BS_MODE_PIC_END) {
  1071. if (val & (1<<4)) {
  1072. info->seqInitErrReason = (VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_SEQ_ERR_REASON));
  1073. return RETCODE_FAILURE;
  1074. }
  1075. }
  1076. if (val == 0) {
  1077. info->seqInitErrReason = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_SEQ_ERR_REASON);
  1078. return RETCODE_FAILURE;
  1079. }
  1080. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_SRC_SIZE);
  1081. info->picWidth = ( (val >> 16) & 0xffff );
  1082. info->picHeight = ( val & 0xffff );
  1083. info->lumaBitdepth = 8;
  1084. info->chromaBitdepth = 8;
  1085. info->fRateNumerator = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_FRATE_NR);
  1086. info->fRateDenominator = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_FRATE_DR);
  1087. if (pCodecInst->codecMode == AVC_DEC && info->fRateDenominator > 0) {
  1088. info->fRateDenominator *= 2;
  1089. }
  1090. if (pCodecInst->codecMode == MP4_DEC) {
  1091. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_INFO);
  1092. info->mp4ShortVideoHeader = (val >> 2) & 1;
  1093. info->mp4DataPartitionEnable = val & 1;
  1094. info->mp4ReversibleVlcEnable = info->mp4DataPartitionEnable ? ((val >> 1) & 1) : 0;
  1095. info->h263AnnexJEnable = (val >> 3) & 1;
  1096. }
  1097. else if (pCodecInst->codecMode == VPX_DEC && pCodecInst->codecModeAux == VPX_AUX_VP8) {
  1098. // h_scale[31:30] v_scale[29:28] pic_width[27:14] pic_height[13:0]
  1099. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_VP8_SCALE_INFO);
  1100. info->vp8ScaleInfo.hScaleFactor = (val >> 30) & 0x03;
  1101. info->vp8ScaleInfo.vScaleFactor = (val >> 28) & 0x03;
  1102. info->vp8ScaleInfo.picWidth = (val >> 14) & 0x3FFF;
  1103. info->vp8ScaleInfo.picHeight = (val >> 0) & 0x3FFF;
  1104. }
  1105. info->minFrameBufferCount = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_FRAME_NEED);
  1106. info->frameBufDelay = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_FRAME_DELAY);
  1107. if (pCodecInst->codecMode == AVC_DEC || pCodecInst->codecMode == MP2_DEC || pCodecInst->codecMode == AVS_DEC) {
  1108. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_CROP_LEFT_RIGHT);
  1109. val2 = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_CROP_TOP_BOTTOM);
  1110. info->picCropRect.left = ((val>>16) & 0xFFFF);
  1111. info->picCropRect.right = info->picWidth - (val & 0xFFFF);;
  1112. info->picCropRect.top = ((val2>>16) & 0xFFFF);
  1113. info->picCropRect.bottom = info->picHeight - (val2 & 0xFFFF);
  1114. val = (info->picWidth * info->picHeight * 3 / 2) / 1024;
  1115. info->normalSliceSize = val / 4;
  1116. info->worstSliceSize = val / 2;
  1117. }
  1118. else {
  1119. info->picCropRect.left = 0;
  1120. info->picCropRect.right = info->picWidth;
  1121. info->picCropRect.top = 0;
  1122. info->picCropRect.bottom = info->picHeight;
  1123. }
  1124. if (pCodecInst->codecMode == MP2_DEC) {
  1125. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_MP2_BAR_LEFT_RIGHT);
  1126. val2 = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_MP2_BAR_TOP_BOTTOM);
  1127. info->mp2BardataInfo.barLeft = ((val>>16) & 0xFFFF);
  1128. info->mp2BardataInfo.barRight = (val&0xFFFF);
  1129. info->mp2BardataInfo.barTop = ((val2>>16) & 0xFFFF);
  1130. info->mp2BardataInfo.barBottom = (val2&0xFFFF);
  1131. }
  1132. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_HEADER_REPORT);
  1133. info->profile = (val >> 0) & 0xFF;
  1134. info->level = (val >> 8) & 0xFF;
  1135. info->interlace = (val >> 16) & 0x01;
  1136. info->direct8x8Flag = (val >> 17) & 0x01;
  1137. info->vc1Psf = (val >> 18) & 0x01;
  1138. info->constraint_set_flag[0] = (val >> 19) & 0x01;
  1139. info->constraint_set_flag[1] = (val >> 20) & 0x01;
  1140. info->constraint_set_flag[2] = (val >> 21) & 0x01;
  1141. info->constraint_set_flag[3] = (val >> 22) & 0x01;
  1142. info->chromaFormatIDC = (val >> 23) & 0x03;
  1143. info->isExtSAR = (val >> 25) & 0x01;
  1144. info->maxNumRefFrm = (val >> 27) & 0x0f;
  1145. info->maxNumRefFrmFlag = (val >> 31) & 0x01;
  1146. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_ASPECT);
  1147. info->aspectRateInfo = val;
  1148. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_BIT_RATE);
  1149. info->bitRate = val;
  1150. if (pCodecInst->codecMode == AVC_DEC) {
  1151. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_VUI_INFO);
  1152. info->avcVuiInfo.fixedFrameRateFlag = val &1;
  1153. info->avcVuiInfo.timingInfoPresent = (val>>1) & 0x01;
  1154. info->avcVuiInfo.chromaLocBotField = (val>>2) & 0x07;
  1155. info->avcVuiInfo.chromaLocTopField = (val>>5) & 0x07;
  1156. info->avcVuiInfo.chromaLocInfoPresent = (val>>8) & 0x01;
  1157. info->avcVuiInfo.colorPrimaries = (val>>16) & 0xff;
  1158. info->avcVuiInfo.colorDescPresent = (val>>24) & 0x01;
  1159. info->avcVuiInfo.isExtSAR = (val>>25) & 0x01;
  1160. info->avcVuiInfo.vidFullRange = (val>>26) & 0x01;
  1161. info->avcVuiInfo.vidFormat = (val>>27) & 0x07;
  1162. info->avcVuiInfo.vidSigTypePresent = (val>>30) & 0x01;
  1163. info->avcVuiInfo.vuiParamPresent = (val>>31) & 0x01;
  1164. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_VUI_PIC_STRUCT);
  1165. info->avcVuiInfo.vuiPicStructPresent = (val & 0x1);
  1166. info->avcVuiInfo.vuiPicStruct = (val>>1);
  1167. }
  1168. if (pCodecInst->codecMode == MP2_DEC) {
  1169. // seq_ext info
  1170. val = VpuReadReg(pCodecInst->coreIdx, RET_DEC_SEQ_EXT_INFO);
  1171. info->mp2LowDelay = val & 1;
  1172. info->mp2DispVerSize = (val>>1) & 0x3fff;
  1173. info->mp2DispHorSize = (val>>15) & 0x3fff;
  1174. if (pDecInfo->userDataEnable) {
  1175. Uint32 userDataNum = 0;
  1176. Uint32 userDataSize = 0;
  1177. BYTE tempBuf[8] = {0,};
  1178. // user data
  1179. VpuReadMem(pCodecInst->coreIdx, pDecInfo->userDataBufAddr, tempBuf, 8, VPU_USER_DATA_ENDIAN);
  1180. val = ((tempBuf[0]<<24) & 0xFF000000) |
  1181. ((tempBuf[1]<<16) & 0x00FF0000) |
  1182. ((tempBuf[2]<< 8) & 0x0000FF00) |
  1183. ((tempBuf[3]<< 0) & 0x000000FF);
  1184. userDataNum = (val >> 16) & 0xFFFF;
  1185. userDataSize = (val >> 0) & 0xFFFF;
  1186. if (userDataNum == 0) {
  1187. userDataSize = 0;
  1188. }
  1189. info->userDataNum = userDataNum;
  1190. info->userDataSize = userDataSize;
  1191. val = ((tempBuf[4]<<24) & 0xFF000000) |
  1192. ((tempBuf[5]<<16) & 0x00FF0000) |
  1193. ((tempBuf[6]<< 8) & 0x0000FF00) |
  1194. ((tempBuf[7]<< 0) & 0x000000FF);
  1195. if (userDataNum == 0) {
  1196. info->userDataBufFull = 0;
  1197. }
  1198. else {
  1199. info->userDataBufFull = (val >> 16) & 0xFFFF;
  1200. }
  1201. }
  1202. }
  1203. return RETCODE_SUCCESS;
  1204. }
  1205. RetCode Coda9VpuDecRegisterFramebuffer(CodecInst* instance)
  1206. {
  1207. CodecInst* pCodecInst;
  1208. DecInfo* pDecInfo;
  1209. PhysicalAddress paraBuffer;
  1210. vpu_buffer_t vb;
  1211. Uint32 val;
  1212. int i;
  1213. BYTE frameAddr[MAX_GDI_IDX][3][4];
  1214. BYTE colMvAddr[MAX_GDI_IDX][4];
  1215. pCodecInst = instance;
  1216. pDecInfo = &pCodecInst->CodecInfo->decInfo;
  1217. vdi_get_common_memory(pCodecInst->coreIdx, &vb);
  1218. paraBuffer = vb.phys_addr + CODE_BUF_SIZE + TEMP_BUF_SIZE;
  1219. pDecInfo->mapCfg.productId = pCodecInst->productId;
  1220. if (pDecInfo->mapType != LINEAR_FRAME_MAP && pDecInfo->mapType != LINEAR_FIELD_MAP) {
  1221. val = SetTiledMapType(pCodecInst->coreIdx, &pDecInfo->mapCfg, pDecInfo->mapType, (pDecInfo->stride > pDecInfo->frameBufferHeight)?pDecInfo->stride:pDecInfo->frameBufferHeight,
  1222. pDecInfo->openParam.cbcrInterleave, &pDecInfo->dramCfg);
  1223. }
  1224. else {
  1225. val = SetTiledMapType(pCodecInst->coreIdx, &pDecInfo->mapCfg, pDecInfo->mapType,pDecInfo->stride, pDecInfo->openParam.cbcrInterleave, &pDecInfo->dramCfg);
  1226. }
  1227. if (val == 0) {
  1228. return RETCODE_INVALID_PARAM;
  1229. }
  1230. //Allocate frame buffer
  1231. for (i=0; i<pDecInfo->numFbsForDecoding; i++) {
  1232. frameAddr[i][0][0] = (pDecInfo->frameBufPool[i].bufY >> 24) & 0xFF;
  1233. frameAddr[i][0][1] = (pDecInfo->frameBufPool[i].bufY >> 16) & 0xFF;
  1234. frameAddr[i][0][2] = (pDecInfo->frameBufPool[i].bufY >> 8) & 0xFF;
  1235. frameAddr[i][0][3] = (pDecInfo->frameBufPool[i].bufY >> 0) & 0xFF;
  1236. if (pDecInfo->openParam.cbcrOrder == CBCR_ORDER_NORMAL) {
  1237. frameAddr[i][1][0] = (pDecInfo->frameBufPool[i].bufCb >> 24) & 0xFF;
  1238. frameAddr[i][1][1] = (pDecInfo->frameBufPool[i].bufCb >> 16) & 0xFF;
  1239. frameAddr[i][1][2] = (pDecInfo->frameBufPool[i].bufCb >> 8) & 0xFF;
  1240. frameAddr[i][1][3] = (pDecInfo->frameBufPool[i].bufCb >> 0) & 0xFF;
  1241. frameAddr[i][2][0] = (pDecInfo->frameBufPool[i].bufCr >> 24) & 0xFF;
  1242. frameAddr[i][2][1] = (pDecInfo->frameBufPool[i].bufCr >> 16) & 0xFF;
  1243. frameAddr[i][2][2] = (pDecInfo->frameBufPool[i].bufCr >> 8) & 0xFF;
  1244. frameAddr[i][2][3] = (pDecInfo->frameBufPool[i].bufCr >> 0) & 0xFF;
  1245. }
  1246. else {
  1247. frameAddr[i][2][0] = (pDecInfo->frameBufPool[i].bufCb >> 24) & 0xFF;
  1248. frameAddr[i][2][1] = (pDecInfo->frameBufPool[i].bufCb >> 16) & 0xFF;
  1249. frameAddr[i][2][2] = (pDecInfo->frameBufPool[i].bufCb >> 8) & 0xFF;
  1250. frameAddr[i][2][3] = (pDecInfo->frameBufPool[i].bufCb >> 0) & 0xFF;
  1251. frameAddr[i][1][0] = (pDecInfo->frameBufPool[i].bufCr >> 24) & 0xFF;
  1252. frameAddr[i][1][1] = (pDecInfo->frameBufPool[i].bufCr >> 16) & 0xFF;
  1253. frameAddr[i][1][2] = (pDecInfo->frameBufPool[i].bufCr >> 8) & 0xFF;
  1254. frameAddr[i][1][3] = (pDecInfo->frameBufPool[i].bufCr >> 0) & 0xFF;
  1255. }
  1256. }
  1257. VpuWriteMem(pCodecInst->coreIdx, paraBuffer, (BYTE*)frameAddr, sizeof(frameAddr), VDI_BIG_ENDIAN);
  1258. // MV allocation and register
  1259. if (pCodecInst->codecMode == AVC_DEC || pCodecInst->codecMode == VC1_DEC || pCodecInst->codecMode == MP4_DEC ||
  1260. pCodecInst->codecMode == RV_DEC || pCodecInst->codecMode == AVS_DEC)
  1261. {
  1262. int size_mvcolbuf;
  1263. vpu_buffer_t vbBuffer;
  1264. size_mvcolbuf = ((pDecInfo->initialInfo.picWidth+31)&~31)*((pDecInfo->initialInfo.picHeight+31)&~31);
  1265. size_mvcolbuf = (size_mvcolbuf*3)/2;
  1266. size_mvcolbuf = (size_mvcolbuf+4)/5;
  1267. size_mvcolbuf = ((size_mvcolbuf+7)/8)*8;
  1268. vbBuffer.size = size_mvcolbuf;
  1269. vbBuffer.phys_addr = 0;
  1270. for (i=0 ; i<pDecInfo->numFbsForDecoding ; i++) {
  1271. if (vdi_allocate_dma_memory(pCodecInst->coreIdx, &vbBuffer, DEC_MV, pCodecInst->instIndex)<0){
  1272. return RETCODE_FAILURE;
  1273. }
  1274. pDecInfo->vbMV[i] = vbBuffer;
  1275. }
  1276. if (pCodecInst->codecMode == AVC_DEC) {
  1277. for (i=0; i<pDecInfo->numFbsForDecoding; i++) {
  1278. colMvAddr[i][0] = (pDecInfo->vbMV[i].phys_addr >> 24) & 0xFF;
  1279. colMvAddr[i][1] = (pDecInfo->vbMV[i].phys_addr >> 16) & 0xFF;
  1280. colMvAddr[i][2] = (pDecInfo->vbMV[i].phys_addr >> 8) & 0xFF;
  1281. colMvAddr[i][3] = (pDecInfo->vbMV[i].phys_addr >> 0) & 0xFF;
  1282. }
  1283. }
  1284. else {
  1285. colMvAddr[0][0] = (pDecInfo->vbMV[0].phys_addr >> 24) & 0xFF;
  1286. colMvAddr[0][1] = (pDecInfo->vbMV[0].phys_addr >> 16) & 0xFF;
  1287. colMvAddr[0][2] = (pDecInfo->vbMV[0].phys_addr >> 8) & 0xFF;
  1288. colMvAddr[0][3] = (pDecInfo->vbMV[0].phys_addr >> 0) & 0xFF;
  1289. }
  1290. VpuWriteMem(pCodecInst->coreIdx, paraBuffer+384, (BYTE*)colMvAddr, sizeof(colMvAddr), VDI_BIG_ENDIAN);
  1291. }
  1292. if (pCodecInst->productId == PRODUCT_ID_980) {
  1293. for (i=0; i<pDecInfo->numFbsForDecoding; i++) {
  1294. frameAddr[i][0][0] = (pDecInfo->frameBufPool[i].bufYBot >> 24) & 0xFF;
  1295. frameAddr[i][0][1] = (pDecInfo->frameBufPool[i].bufYBot >> 16) & 0xFF;
  1296. frameAddr[i][0][2] = (pDecInfo->frameBufPool[i].bufYBot >> 8) & 0xFF;
  1297. frameAddr[i][0][3] = (pDecInfo->frameBufPool[i].bufYBot >> 0) & 0xFF;
  1298. if (pDecInfo->openParam.cbcrOrder == CBCR_ORDER_NORMAL) {
  1299. frameAddr[i][1][0] = (pDecInfo->frameBufPool[i].bufCbBot >> 24) & 0xFF;
  1300. frameAddr[i][1][1] = (pDecInfo->frameBufPool[i].bufCbBot >> 16) & 0xFF;
  1301. frameAddr[i][1][2] = (pDecInfo->frameBufPool[i].bufCbBot >> 8) & 0xFF;
  1302. frameAddr[i][1][3] = (pDecInfo->frameBufPool[i].bufCbBot >> 0) & 0xFF;
  1303. frameAddr[i][2][0] = (pDecInfo->frameBufPool[i].bufCrBot >> 24) & 0xFF;
  1304. frameAddr[i][2][1] = (pDecInfo->frameBufPool[i].bufCrBot >> 16) & 0xFF;
  1305. frameAddr[i][2][2] = (pDecInfo->frameBufPool[i].bufCrBot >> 8) & 0xFF;
  1306. frameAddr[i][2][3] = (pDecInfo->frameBufPool[i].bufCrBot >> 0) & 0xFF;
  1307. }
  1308. else {
  1309. frameAddr[i][2][0] = (pDecInfo->frameBufPool[i].bufCbBot >> 24) & 0xFF;
  1310. frameAddr[i][2][1] = (pDecInfo->frameBufPool[i].bufCbBot >> 16) & 0xFF;
  1311. frameAddr[i][2][2] = (pDecInfo->frameBufPool[i].bufCbBot >> 8) & 0xFF;
  1312. frameAddr[i][2][3] = (pDecInfo->frameBufPool[i].bufCbBot >> 0) & 0xFF;
  1313. frameAddr[i][1][0] = (pDecInfo->frameBufPool[i].bufCrBot >> 24) & 0xFF;
  1314. frameAddr[i][1][1] = (pDecInfo->frameBufPool[i].bufCrBot >> 16) & 0xFF;
  1315. frameAddr[i][1][2] = (pDecInfo->frameBufPool[i].bufCrBot >> 8) & 0xFF;
  1316. frameAddr[i][1][3] = (pDecInfo->frameBufPool[i].bufCrBot >> 0) & 0xFF;
  1317. }
  1318. }
  1319. VpuWriteMem(pCodecInst->coreIdx, paraBuffer+384+128, (BYTE*)frameAddr, sizeof(frameAddr), VDI_BIG_ENDIAN);
  1320. if (pDecInfo->wtlEnable) {
  1321. int num = pDecInfo->numFbsForDecoding; /* start index of WTL fb array */
  1322. int end = pDecInfo->numFrameBuffers;
  1323. for (i=num; i<end; i++) {
  1324. frameAddr[i-num][0][0] = (pDecInfo->frameBufPool[i].bufY >> 24) & 0xFF;
  1325. frameAddr[i-num][0][1] = (pDecInfo->frameBufPool[i].bufY >> 16) & 0xFF;
  1326. frameAddr[i-num][0][2] = (pDecInfo->frameBufPool[i].bufY >> 8) & 0xFF;
  1327. frameAddr[i-num][0][3] = (pDecInfo->frameBufPool[i].bufY >> 0) & 0xFF;
  1328. if (pDecInfo->openParam.cbcrOrder == CBCR_ORDER_NORMAL) {
  1329. frameAddr[i-num][1][0] = (pDecInfo->frameBufPool[i].bufCb >> 24) & 0xFF;
  1330. frameAddr[i-num][1][1] = (pDecInfo->frameBufPool[i].bufCb >> 16) & 0xFF;
  1331. frameAddr[i-num][1][2] = (pDecInfo->frameBufPool[i].bufCb >> 8) & 0xFF;
  1332. frameAddr[i-num][1][3] = (pDecInfo->frameBufPool[i].bufCb >> 0) & 0xFF;
  1333. frameAddr[i-num][2][0] = (pDecInfo->frameBufPool[i].bufCr >> 24) & 0xFF;
  1334. frameAddr[i-num][2][1] = (pDecInfo->frameBufPool[i].bufCr >> 16) & 0xFF;
  1335. frameAddr[i-num][2][2] = (pDecInfo->frameBufPool[i].bufCr >> 8) & 0xFF;
  1336. frameAddr[i-num][2][3] = (pDecInfo->frameBufPool[i].bufCr >> 0) & 0xFF;
  1337. }
  1338. else {
  1339. frameAddr[i-num][2][0] = (pDecInfo->frameBufPool[i].bufCb >> 24) & 0xFF;
  1340. frameAddr[i-num][2][1] = (pDecInfo->frameBufPool[i].bufCb >> 16) & 0xFF;
  1341. frameAddr[i-num][2][2] = (pDecInfo->frameBufPool[i].bufCb >> 8) & 0xFF;
  1342. frameAddr[i-num][2][3] = (pDecInfo->frameBufPool[i].bufCb >> 0) & 0xFF;
  1343. frameAddr[i-num][1][0] = (pDecInfo->frameBufPool[i].bufCr >> 24) & 0xFF;
  1344. frameAddr[i-num][1][1] = (pDecInfo->frameBufPool[i].bufCr >> 16) & 0xFF;
  1345. frameAddr[i-num][1][2] = (pDecInfo->frameBufPool[i].bufCr >> 8) & 0xFF;
  1346. frameAddr[i-num][1][3] = (pDecInfo->frameBufPool[i].bufCr >> 0) & 0xFF;
  1347. }
  1348. }
  1349. VpuWriteMem(pCodecInst->coreIdx, paraBuffer+384+128+384, (BYTE*)frameAddr, sizeof(frameAddr), VDI_BIG_ENDIAN);
  1350. if (pDecInfo->wtlMode == FF_FIELD ) {
  1351. for (i=num; i<num*2; i++) {
  1352. frameAddr[i-num][0][0] = (pDecInfo->frameBufPool[i].bufYBot >> 24) & 0xFF;
  1353. frameAddr[i-num][0][1] = (pDecInfo->frameBufPool[i].bufYBot >> 16) & 0xFF;
  1354. frameAddr[i-num][0][2] = (pDecInfo->frameBufPool[i].bufYBot >> 8) & 0xFF;
  1355. frameAddr[i-num][0][3] = (pDecInfo->frameBufPool[i].bufYBot >> 0) & 0xFF;
  1356. if (pDecInfo->openParam.cbcrOrder == CBCR_ORDER_NORMAL) {
  1357. frameAddr[i-num][1][0] = (pDecInfo->frameBufPool[i].bufCbBot >> 24) & 0xFF;
  1358. frameAddr[i-num][1][1] = (pDecInfo->frameBufPool[i].bufCbBot >> 16) & 0xFF;
  1359. frameAddr[i-num][1][2] = (pDecInfo->frameBufPool[i].bufCbBot >> 8) & 0xFF;
  1360. frameAddr[i-num][1][3] = (pDecInfo->frameBufPool[i].bufCbBot >> 0) & 0xFF;
  1361. frameAddr[i-num][2][0] = (pDecInfo->frameBufPool[i].bufCrBot >> 24) & 0xFF;
  1362. frameAddr[i-num][2][1] = (pDecInfo->frameBufPool[i].bufCrBot >> 16) & 0xFF;
  1363. frameAddr[i-num][2][2] = (pDecInfo->frameBufPool[i].bufCrBot >> 8) & 0xFF;
  1364. frameAddr[i-num][2][3] = (pDecInfo->frameBufPool[i].bufCrBot >> 0) & 0xFF;
  1365. }
  1366. else {
  1367. frameAddr[i-num][2][0] = (pDecInfo->frameBufPool[i].bufCbBot >> 24) & 0xFF;
  1368. frameAddr[i-num][2][1] = (pDecInfo->frameBufPool[i].bufCbBot >> 16) & 0xFF;
  1369. frameAddr[i-num][2][2] = (pDecInfo->frameBufPool[i].bufCbBot >> 8) & 0xFF;
  1370. frameAddr[i-num][2][3] = (pDecInfo->frameBufPool[i].bufCbBot >> 0) & 0xFF;
  1371. frameAddr[i-num][1][0] = (pDecInfo->frameBufPool[i].bufCrBot >> 24) & 0xFF;
  1372. frameAddr[i-num][1][1] = (pDecInfo->frameBufPool[i].bufCrBot >> 16) & 0xFF;
  1373. frameAddr[i-num][1][2] = (pDecInfo->frameBufPool[i].bufCrBot >> 8) & 0xFF;
  1374. frameAddr[i-num][1][3] = (pDecInfo->frameBufPool[i].bufCrBot >> 0) & 0xFF;
  1375. }
  1376. }
  1377. VpuWriteMem(pCodecInst->coreIdx, paraBuffer+384+128+384+384, (BYTE*)frameAddr, sizeof(frameAddr), VDI_BIG_ENDIAN);
  1378. }
  1379. }
  1380. }
  1381. else {
  1382. if (pDecInfo->wtlEnable) {
  1383. int num = pDecInfo->numFbsForDecoding; /* start index of WTL fb array */
  1384. int end = pDecInfo->numFrameBuffers;
  1385. for (i=num; i<end; i++) {
  1386. frameAddr[i-num][0][0] = (pDecInfo->frameBufPool[i].bufY >> 24) & 0xFF;
  1387. frameAddr[i-num][0][1] = (pDecInfo->frameBufPool[i].bufY >> 16) & 0xFF;
  1388. frameAddr[i-num][0][2] = (pDecInfo->frameBufPool[i].bufY >> 8) & 0xFF;
  1389. frameAddr[i-num][0][3] = (pDecInfo->frameBufPool[i].bufY >> 0) & 0xFF;
  1390. if (pDecInfo->openParam.cbcrOrder == CBCR_ORDER_NORMAL) {
  1391. frameAddr[i-num][1][0] = (pDecInfo->frameBufPool[i].bufCb >> 24) & 0xFF;
  1392. frameAddr[i-num][1][1] = (pDecInfo->frameBufPool[i].bufCb >> 16) & 0xFF;
  1393. frameAddr[i-num][1][2] = (pDecInfo->frameBufPool[i].bufCb >> 8) & 0xFF;
  1394. frameAddr[i-num][1][3] = (pDecInfo->frameBufPool[i].bufCb >> 0) & 0xFF;
  1395. frameAddr[i-num][2][0] = (pDecInfo->frameBufPool[i].bufCr >> 24) & 0xFF;
  1396. frameAddr[i-num][2][1] = (pDecInfo->frameBufPool[i].bufCr >> 16) & 0xFF;
  1397. frameAddr[i-num][2][2] = (pDecInfo->frameBufPool[i].bufCr >> 8) & 0xFF;
  1398. frameAddr[i-num][2][3] = (pDecInfo->frameBufPool[i].bufCr >> 0) & 0xFF;
  1399. }
  1400. else {
  1401. frameAddr[i-num][2][0] = (pDecInfo->frameBufPool[i].bufCb >> 24) & 0xFF;
  1402. frameAddr[i-num][2][1] = (pDecInfo->frameBufPool[i].bufCb >> 16) & 0xFF;
  1403. frameAddr[i-num][2][2] = (pDecInfo->frameBufPool[i].bufCb >> 8) & 0xFF;
  1404. frameAddr[i-num][2][3] = (pDecInfo->frameBufPool[i].bufCb >> 0) & 0xFF;
  1405. frameAddr[i-num][1][0] = (pDecInfo->frameBufPool[i].bufCr >> 24) & 0xFF;
  1406. frameAddr[i-num][1][1] = (pDecInfo->frameBufPool[i].bufCr >> 16) & 0xFF;
  1407. frameAddr[i-num][1][2] = (pDecInfo->frameBufPool[i].bufCr >> 8) & 0xFF;
  1408. frameAddr[i-num][1][3] = (pDecInfo->frameBufPool[i].bufCr >> 0) & 0xFF;
  1409. }
  1410. }
  1411. VpuWriteMem(pCodecInst->coreIdx, paraBuffer+384+128+384, (BYTE*)frameAddr, sizeof(frameAddr), VDI_BIG_ENDIAN);
  1412. }
  1413. }
  1414. if (!ConfigSecAXICoda9(pCodecInst->coreIdx, pCodecInst->codecMode, &pDecInfo->secAxiInfo, pDecInfo->initialInfo.picWidth,
  1415. pDecInfo->frameBufferHeight, pDecInfo->initialInfo.profile&0xff)) {
  1416. return RETCODE_INSUFFICIENT_RESOURCE;
  1417. }
  1418. // Tell the decoder how much frame buffers were allocated.
  1419. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_BUF_NUM, pDecInfo->numFrameBuffers);
  1420. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_BUF_STRIDE, pDecInfo->stride);
  1421. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_BIT_ADDR, pDecInfo->secAxiInfo.u.coda9.bufBitUse);
  1422. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_IPACDC_ADDR, pDecInfo->secAxiInfo.u.coda9.bufIpAcDcUse);
  1423. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_DBKY_ADDR, pDecInfo->secAxiInfo.u.coda9.bufDbkYUse);
  1424. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_DBKC_ADDR, pDecInfo->secAxiInfo.u.coda9.bufDbkCUse);
  1425. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_OVL_ADDR, pDecInfo->secAxiInfo.u.coda9.bufOvlUse);
  1426. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_BTP_ADDR, pDecInfo->secAxiInfo.u.coda9.bufBtpUse);
  1427. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_DELAY, pDecInfo->frameDelay);
  1428. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_CACHE_CONFIG, pDecInfo->cacheConfig.type2.CacheMode);
  1429. if (pCodecInst->codecMode == VPX_DEC) {
  1430. vpu_buffer_t *pvbSlice = &pDecInfo->vbSlice;
  1431. if (pvbSlice->size == 0) {
  1432. pvbSlice->size = VP8_MB_SAVE_SIZE;
  1433. if (vdi_allocate_dma_memory(pCodecInst->coreIdx, pvbSlice, DEC_ETC, pCodecInst->instIndex) < 0) {
  1434. return RETCODE_INSUFFICIENT_RESOURCE;
  1435. }
  1436. }
  1437. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_MB_BUF_BASE, pvbSlice->phys_addr);
  1438. }
  1439. if (pCodecInst->codecMode == AVC_DEC) {
  1440. vpu_buffer_t *pvbSlice = &pDecInfo->vbSlice;
  1441. if (pvbSlice->size == 0) {
  1442. pvbSlice->size = SLICE_SAVE_SIZE;
  1443. if (vdi_allocate_dma_memory(pCodecInst->coreIdx, pvbSlice, DEC_ETC, pCodecInst->instIndex) < 0) {
  1444. return RETCODE_INSUFFICIENT_RESOURCE;
  1445. }
  1446. }
  1447. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_SLICE_BB_START, pvbSlice->phys_addr);
  1448. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_SLICE_BB_SIZE, (pvbSlice->size/1024));
  1449. }
  1450. if (pCodecInst->productId == PRODUCT_ID_980) {
  1451. val = 0;
  1452. val |= (pDecInfo->openParam.bwbEnable<<15);
  1453. val |= (pDecInfo->wtlMode<<17)|(pDecInfo->tiled2LinearMode<<13)|(pDecInfo->mapType<<9)|(FORMAT_420<<6);
  1454. val |= ((pDecInfo->openParam.cbcrInterleave)<<2); // Interleave bit position is modified
  1455. val |= pDecInfo->openParam.frameEndian;
  1456. VpuWriteReg(pCodecInst->coreIdx, BIT_FRAME_MEM_CTRL, val);
  1457. }
  1458. else if (pCodecInst->productId == PRODUCT_ID_960) {
  1459. val = 0;
  1460. val |= (pDecInfo->wtlEnable<<17);
  1461. val |= (pDecInfo->openParam.bwbEnable<<12);
  1462. if (pDecInfo->mapType) {
  1463. if (pDecInfo->mapType == TILED_FRAME_MB_RASTER_MAP || pDecInfo->mapType == TILED_FIELD_MB_RASTER_MAP)
  1464. val |= (pDecInfo->tiled2LinearEnable<<11)|(0x03<<9)|(FORMAT_420<<6);
  1465. else
  1466. val |= (pDecInfo->tiled2LinearEnable<<11)|(0x02<<9)|(FORMAT_420<<6);
  1467. }
  1468. val |= ((pDecInfo->openParam.cbcrInterleave)<<2); // Interleave bit position is modified
  1469. val |= pDecInfo->openParam.frameEndian;
  1470. VpuWriteReg(pCodecInst->coreIdx, BIT_FRAME_MEM_CTRL, val);
  1471. }
  1472. else {
  1473. return RETCODE_NOT_FOUND_VPU_DEVICE;
  1474. }
  1475. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_MAX_DEC_SIZE, 0);
  1476. Coda9BitIssueCommand(pCodecInst->coreIdx, pCodecInst, SET_FRAME_BUF);
  1477. if (vdi_wait_vpu_busy(pCodecInst->coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1) {
  1478. if (pCodecInst->loggingEnable)
  1479. vdi_log(pCodecInst->coreIdx, SET_FRAME_BUF, 2);
  1480. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1481. }
  1482. if (pCodecInst->loggingEnable)
  1483. vdi_log(pCodecInst->coreIdx, SET_FRAME_BUF, 0);
  1484. if (VpuReadReg(pCodecInst->coreIdx, RET_SET_FRAME_SUCCESS) & (1UL<<31)) {
  1485. return RETCODE_MEMORY_ACCESS_VIOLATION;
  1486. }
  1487. return RETCODE_SUCCESS;
  1488. }
  1489. RetCode Coda9VpuDecFlush(CodecInst* instance, FramebufferIndex* framebufferIndexes, Uint32 size)
  1490. {
  1491. Uint32 i;
  1492. DecInfo* pDecInfo = &instance->CodecInfo->decInfo;
  1493. Coda9BitIssueCommand(instance->coreIdx, instance, DEC_BUF_FLUSH);
  1494. if (vdi_wait_vpu_busy(instance->coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1) {
  1495. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1496. }
  1497. pDecInfo->frameDisplayFlag = 0;
  1498. if (framebufferIndexes != NULL) {
  1499. for (i=0; i<size; i++) {
  1500. framebufferIndexes[i].linearIndex = -2;
  1501. framebufferIndexes[i].tiledIndex = -2;
  1502. }
  1503. }
  1504. return RETCODE_SUCCESS;
  1505. }
  1506. /************************************************************************/
  1507. /* Encoder */
  1508. /************************************************************************/
  1509. RetCode Coda9VpuBuildUpEncParam(CodecInst* pCodec, EncOpenParam* param)
  1510. {
  1511. RetCode ret = RETCODE_SUCCESS;
  1512. Uint32 coreIdx;
  1513. Int32 productId;
  1514. EncInfo* pEncInfo = &pCodec->CodecInfo->encInfo;
  1515. coreIdx = pCodec->coreIdx;
  1516. productId = Coda9VpuGetProductId(coreIdx);
  1517. if ((ret=SetupEncCodecInstance(productId, pCodec)) != RETCODE_SUCCESS)
  1518. return ret;
  1519. if (param->bitstreamFormat == STD_MPEG4 || param->bitstreamFormat == STD_H263)
  1520. pCodec->codecMode = MP4_ENC;
  1521. else if (param->bitstreamFormat == STD_AVC)
  1522. pCodec->codecMode = AVC_ENC;
  1523. pCodec->codecModeAux = 0;
  1524. if (productId == PRODUCT_ID_980) {
  1525. pEncInfo->ActivePPSIdx = 0;
  1526. pEncInfo->frameIdx = 0;
  1527. pEncInfo->fieldDone = 0;
  1528. }
  1529. pEncInfo->vbWork.size = WORK_BUF_SIZE;
  1530. if (vdi_allocate_dma_memory(pCodec->coreIdx, &pEncInfo->vbWork, ENC_WORK, pCodec->instIndex) < 0)
  1531. return RETCODE_INSUFFICIENT_RESOURCE;
  1532. pEncInfo->streamRdPtr = param->bitstreamBuffer;
  1533. pEncInfo->streamWrPtr = param->bitstreamBuffer;
  1534. pEncInfo->lineBufIntEn = param->lineBufIntEn;
  1535. pEncInfo->streamBufStartAddr = param->bitstreamBuffer;
  1536. pEncInfo->streamBufSize = param->bitstreamBufferSize;
  1537. pEncInfo->streamBufEndAddr = param->bitstreamBuffer + param->bitstreamBufferSize;
  1538. pEncInfo->stride = 0;
  1539. pEncInfo->vbFrame.size = 0;
  1540. pEncInfo->vbPPU.size = 0;
  1541. pEncInfo->frameAllocExt = 0;
  1542. pEncInfo->ppuAllocExt = 0;
  1543. pEncInfo->secAxiInfo.u.coda9.useBitEnable = 0;
  1544. pEncInfo->secAxiInfo.u.coda9.useIpEnable = 0;
  1545. pEncInfo->secAxiInfo.u.coda9.useDbkYEnable = 0;
  1546. pEncInfo->secAxiInfo.u.coda9.useDbkCEnable = 0;
  1547. pEncInfo->secAxiInfo.u.coda9.useOvlEnable = 0;
  1548. pEncInfo->rotationEnable = 0;
  1549. pEncInfo->mirrorEnable = 0;
  1550. pEncInfo->mirrorDirection = MIRDIR_NONE;
  1551. pEncInfo->rotationAngle = 0;
  1552. pEncInfo->initialInfoObtained = 0;
  1553. pEncInfo->ringBufferEnable = param->ringBufferEnable;
  1554. pEncInfo->linear2TiledEnable = param->linear2TiledEnable;
  1555. pEncInfo->linear2TiledMode = param->linear2TiledMode; // coda980 only
  1556. if (!pEncInfo->linear2TiledEnable)
  1557. pEncInfo->linear2TiledMode = 0;
  1558. /* Maverick Cache I */
  1559. osal_memset((void*)&pEncInfo->cacheConfig, 0x00, sizeof(MaverickCacheConfig));
  1560. if (productId == PRODUCT_ID_960) {
  1561. pEncInfo->dramCfg.bankBit = EM_BANK;
  1562. pEncInfo->dramCfg.casBit = EM_CAS;
  1563. pEncInfo->dramCfg.rasBit = EM_RAS;
  1564. pEncInfo->dramCfg.busBit = EM_WIDTH;
  1565. }
  1566. return ret;
  1567. }
  1568. RetCode Coda9VpuEncSetup(CodecInst* pCodecInst)
  1569. {
  1570. Int32 picWidth, picHeight;
  1571. Int32 data, val;
  1572. Int32 productId, rcEnable;
  1573. EncInfo* pEncInfo = &pCodecInst->CodecInfo->encInfo;
  1574. rcEnable = pEncInfo->openParam.rcEnable&0xf;
  1575. productId = pCodecInst->productId;
  1576. picWidth = pEncInfo->openParam.picWidth;
  1577. picHeight = pEncInfo->openParam.picHeight;
  1578. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_BB_START, pEncInfo->streamBufStartAddr);
  1579. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_BB_SIZE, pEncInfo->streamBufSize / 1024); // size in KB
  1580. // Rotation Left 90 or 270 case : Swap XY resolution for VPU internal usage
  1581. if (pEncInfo->rotationAngle == 90 || pEncInfo->rotationAngle == 270)
  1582. data = (picHeight<< 16) | picWidth;
  1583. else
  1584. data = (picWidth << 16) | picHeight;
  1585. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_SRC_SIZE, data);
  1586. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_SRC_F_RATE, pEncInfo->openParam.frameRateInfo);
  1587. if (pEncInfo->openParam.bitstreamFormat == STD_MPEG4) {
  1588. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_COD_STD, 3);
  1589. data = pEncInfo->openParam.EncStdParam.mp4Param.mp4IntraDcVlcThr << 2 |
  1590. pEncInfo->openParam.EncStdParam.mp4Param.mp4ReversibleVlcEnable << 1 |
  1591. pEncInfo->openParam.EncStdParam.mp4Param.mp4DataPartitionEnable;
  1592. data |= ((pEncInfo->openParam.EncStdParam.mp4Param.mp4HecEnable >0)? 1:0)<<5;
  1593. data |= ((pEncInfo->openParam.EncStdParam.mp4Param.mp4Verid == 2)? 0:1) << 6;
  1594. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_MP4_PARA, data);
  1595. if (productId == PRODUCT_ID_980)
  1596. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_ME_OPTION, (VPU_ME_LINEBUFFER_MODE << 9) |
  1597. (pEncInfo->openParam.meBlkMode << 5) |
  1598. (pEncInfo->openParam.MEUseZeroPmv << 4) |
  1599. (pEncInfo->openParam.MESearchRangeY<<2) |
  1600. pEncInfo->openParam.MESearchRangeX);
  1601. else
  1602. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_ME_OPTION, (pEncInfo->openParam.meBlkMode << 3) |
  1603. (pEncInfo->openParam.MEUseZeroPmv << 2) |
  1604. pEncInfo->openParam.MESearchRange);
  1605. }
  1606. else if (pEncInfo->openParam.bitstreamFormat == STD_H263) {
  1607. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_COD_STD, 11);
  1608. data = pEncInfo->openParam.EncStdParam.h263Param.h263AnnexIEnable << 3 |
  1609. pEncInfo->openParam.EncStdParam.h263Param.h263AnnexJEnable << 2 |
  1610. pEncInfo->openParam.EncStdParam.h263Param.h263AnnexKEnable << 1|
  1611. pEncInfo->openParam.EncStdParam.h263Param.h263AnnexTEnable;
  1612. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_263_PARA, data);
  1613. if (productId == PRODUCT_ID_980)
  1614. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_ME_OPTION, (VPU_ME_LINEBUFFER_MODE << 9) |
  1615. (pEncInfo->openParam.meBlkMode << 5) |
  1616. (pEncInfo->openParam.MEUseZeroPmv << 4) |
  1617. (pEncInfo->openParam.MESearchRangeY<<2) |
  1618. pEncInfo->openParam.MESearchRangeX);
  1619. else
  1620. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_ME_OPTION, (pEncInfo->openParam.meBlkMode << 3) |
  1621. (pEncInfo->openParam.MEUseZeroPmv << 2) |
  1622. pEncInfo->openParam.MESearchRange);
  1623. }
  1624. else if (pEncInfo->openParam.bitstreamFormat == STD_AVC) {
  1625. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_COD_STD, 0x0);
  1626. data = (pEncInfo->openParam.EncStdParam.avcParam.deblkFilterOffsetBeta & 15) << 12 |
  1627. (pEncInfo->openParam.EncStdParam.avcParam.deblkFilterOffsetAlpha & 15) << 8 |
  1628. pEncInfo->openParam.EncStdParam.avcParam.disableDeblk << 6 |
  1629. pEncInfo->openParam.EncStdParam.avcParam.constrainedIntraPredFlag << 5 |
  1630. (pEncInfo->openParam.EncStdParam.avcParam.chromaQpOffset & 31);
  1631. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_264_PARA, data);
  1632. if (productId == PRODUCT_ID_980) {
  1633. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_ME_OPTION, (VPU_ME_LINEBUFFER_MODE << 9) |
  1634. (pEncInfo->openParam.meBlkMode << 5) |
  1635. (pEncInfo->openParam.MEUseZeroPmv << 4) |
  1636. (pEncInfo->openParam.MESearchRangeY<<2) |
  1637. pEncInfo->openParam.MESearchRangeX);
  1638. }
  1639. else {
  1640. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_ME_OPTION, (pEncInfo->openParam.meBlkMode << 3) | (pEncInfo->openParam.MEUseZeroPmv << 2) | pEncInfo->openParam.MESearchRange);
  1641. }
  1642. }
  1643. if (productId == PRODUCT_ID_980) {
  1644. data = 0;
  1645. if (pEncInfo->openParam.sliceMode.sliceMode!=0) {
  1646. data = pEncInfo->openParam.sliceMode.sliceSize << 2 |
  1647. (pEncInfo->openParam.sliceMode.sliceSizeMode+1); // encoding mode 0,1,2
  1648. }
  1649. }
  1650. else {
  1651. data = pEncInfo->openParam.sliceMode.sliceSize << 2 |
  1652. pEncInfo->openParam.sliceMode.sliceSizeMode << 1 |
  1653. pEncInfo->openParam.sliceMode.sliceMode;
  1654. }
  1655. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_SLICE_MODE, data);
  1656. if (rcEnable) { // rate control enabled
  1657. if (productId == PRODUCT_ID_980) {
  1658. if (pEncInfo->openParam.bitstreamFormat == STD_AVC) {
  1659. int MinDeltaQp, MaxDeltaQp, QpMin, QpMax;
  1660. data = (pEncInfo->openParam.idrInterval << 21) | (pEncInfo->openParam.rcGopIQpOffsetEn<<20) | ((pEncInfo->openParam.rcGopIQpOffset & 0xF)<<16) | pEncInfo->openParam.gopSize ;
  1661. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_GOP_NUM, data);
  1662. data = (pEncInfo->openParam.frameSkipDisable) << 31 |
  1663. pEncInfo->openParam.rcInitDelay << 16 | 0;
  1664. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA, data);
  1665. data = (pEncInfo->openParam.bitRate<<4)|(rcEnable);
  1666. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA2, data);
  1667. data = 0;
  1668. if (pEncInfo->openParam.maxIntraSize>0)
  1669. data = (1<<16) | (pEncInfo->openParam.maxIntraSize & 0xFFFF);
  1670. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_MAX_INTRA_SIZE, data);
  1671. if (pEncInfo->openParam.userMinDeltaQp<0)
  1672. MinDeltaQp = 0;
  1673. else
  1674. MinDeltaQp = (1<<6)|pEncInfo->openParam.userMinDeltaQp;
  1675. if (pEncInfo->openParam.userMaxDeltaQp<0)
  1676. MaxDeltaQp = 0;
  1677. else
  1678. MaxDeltaQp = (1<<6)|pEncInfo->openParam.userMaxDeltaQp;
  1679. if (pEncInfo->openParam.userQpMin<0)
  1680. QpMin = 0;
  1681. else
  1682. QpMin = (1<<6)|pEncInfo->openParam.userQpMin;
  1683. if (pEncInfo->openParam.userQpMax<0)
  1684. QpMax = 0;
  1685. else
  1686. QpMax = (1<<6)|pEncInfo->openParam.userQpMax;
  1687. data = MinDeltaQp<<24 | MaxDeltaQp<<16 | QpMin<<8 | QpMax;
  1688. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_QP_RANGE_SET, data);
  1689. }
  1690. else { // MP4
  1691. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_GOP_NUM, pEncInfo->openParam.gopSize);
  1692. data = (pEncInfo->openParam.frameSkipDisable) << 31 |
  1693. pEncInfo->openParam.rcInitDelay << 16 |
  1694. pEncInfo->openParam.bitRate<<1 | 1;
  1695. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA, data);
  1696. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_QP_RANGE_SET, 0);
  1697. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA2, 0);
  1698. }
  1699. }
  1700. else {
  1701. /* coda960 ENCODER */
  1702. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_GOP_NUM, pEncInfo->openParam.gopSize);
  1703. data = (pEncInfo->openParam.frameSkipDisable) << 31 |
  1704. pEncInfo->openParam.rcInitDelay << 16 |
  1705. pEncInfo->openParam.bitRate<<1 | 1;
  1706. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA, data);
  1707. }
  1708. }
  1709. else {
  1710. if (pEncInfo->openParam.bitstreamFormat == STD_AVC)
  1711. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_GOP_NUM, (pEncInfo->openParam.idrInterval << 21) | pEncInfo->openParam.gopSize);
  1712. else
  1713. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_GOP_NUM, pEncInfo->openParam.gopSize);
  1714. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA, 0);
  1715. if (productId == PRODUCT_ID_980) {
  1716. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_QP_RANGE_SET, 0);
  1717. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_PARA2, 0);
  1718. }
  1719. }
  1720. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_BUF_SIZE, pEncInfo->openParam.vbvBufferSize);
  1721. data = pEncInfo->openParam.intraRefreshNum | pEncInfo->openParam.ConscIntraRefreshEnable<<16;
  1722. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_INTRA_REFRESH, data);
  1723. data = 0;
  1724. if(pEncInfo->openParam.rcIntraQp>=0) {
  1725. data = (1 << 5);
  1726. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_INTRA_QP, pEncInfo->openParam.rcIntraQp);
  1727. }
  1728. else {
  1729. data = 0;
  1730. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_INTRA_QP, (Uint32)-1);
  1731. }
  1732. if (pCodecInst->codecMode == AVC_ENC) {
  1733. data |= (pEncInfo->openParam.EncStdParam.avcParam.audEnable << 2);
  1734. }
  1735. if(pEncInfo->openParam.userQpMax>=0) {
  1736. data |= (1<<6);
  1737. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_QP_MAX, pEncInfo->openParam.userQpMax);
  1738. }
  1739. else {
  1740. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_QP_MAX, 0);
  1741. }
  1742. if(pEncInfo->openParam.userGamma >= 0) {
  1743. data |= (1<<7);
  1744. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_GAMMA, pEncInfo->openParam.userGamma);
  1745. }
  1746. else {
  1747. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_GAMMA, 0);
  1748. }
  1749. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_OPTION, data);
  1750. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_RC_INTERVAL_MODE, (pEncInfo->openParam.mbInterval<<2) | pEncInfo->openParam.rcIntervalMode);
  1751. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_SEQ_INTRA_WEIGHT, pEncInfo->openParam.intraCostWeight);
  1752. VpuWriteReg(pCodecInst->coreIdx, pEncInfo->streamWrPtrRegAddr, pEncInfo->streamWrPtr);
  1753. VpuWriteReg(pCodecInst->coreIdx, pEncInfo->streamRdPtrRegAddr, pEncInfo->streamRdPtr);
  1754. SetEncFrameMemInfo(pCodecInst);
  1755. val = 0;
  1756. if (pEncInfo->ringBufferEnable == 0) {
  1757. if (pEncInfo->lineBufIntEn)
  1758. val |= (0x1<<6);
  1759. val |= (0x1<<5);
  1760. val |= (0x1<<4);
  1761. }
  1762. else {
  1763. val |= (0x1<<3);
  1764. }
  1765. val |= pEncInfo->openParam.streamEndian;
  1766. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_CTRL, val);
  1767. Coda9BitIssueCommand(pCodecInst->coreIdx, pCodecInst, ENC_SEQ_INIT);
  1768. #ifdef SUPPORT_MULTI_INST_INTR
  1769. if (vdi_wait_interrupt(pCodecInst->coreIdx, 0, __VPU_BUSY_TIMEOUT) == -1) {
  1770. #else
  1771. if (vdi_wait_interrupt(pCodecInst->coreIdx, __VPU_BUSY_TIMEOUT) == -1) {
  1772. #endif
  1773. if (pCodecInst->loggingEnable)
  1774. vdi_log(pCodecInst->coreIdx, ENC_SEQ_INIT, 2);
  1775. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1776. }
  1777. VpuWriteReg(pCodecInst->coreIdx, BIT_INT_CLEAR, 1); // that is OK. HW signal already is clear by device driver
  1778. VpuWriteReg(pCodecInst->coreIdx, BIT_INT_REASON, 0);
  1779. if (pCodecInst->loggingEnable)
  1780. vdi_log(pCodecInst->coreIdx, ENC_SEQ_INIT, 0);
  1781. if (VpuReadReg(pCodecInst->coreIdx, RET_ENC_SEQ_END_SUCCESS) & (1UL<<31))
  1782. return RETCODE_MEMORY_ACCESS_VIOLATION;
  1783. if (VpuReadReg(pCodecInst->coreIdx, RET_ENC_SEQ_END_SUCCESS) == 0)
  1784. return RETCODE_FAILURE;
  1785. pEncInfo->streamWrPtr = VpuReadReg(pCodecInst->coreIdx, pEncInfo->streamWrPtrRegAddr);
  1786. pEncInfo->streamEndflag = VpuReadReg(pCodecInst->coreIdx, BIT_BIT_STREAM_PARAM);
  1787. return RETCODE_SUCCESS;
  1788. }
  1789. RetCode Coda9VpuEncRegisterFramebuffer(CodecInst* instance)
  1790. {
  1791. CodecInst* pCodecInst = instance;
  1792. EncInfo* pEncInfo;
  1793. Int32 i, val;
  1794. RetCode ret;
  1795. PhysicalAddress paraBuffer;
  1796. BYTE frameAddr[MAX_FRAMEBUFFER_COUNT][3][4];
  1797. Int32 stride, height, mapType, num;
  1798. VpuAttr* pAttr = &g_VpuCoreAttributes[instance->coreIdx];
  1799. pEncInfo = &instance->CodecInfo->encInfo;
  1800. stride = pEncInfo->stride;
  1801. height = pEncInfo->frameBufferHeight;
  1802. mapType = pEncInfo->mapType;
  1803. if (pCodecInst->productId == PRODUCT_ID_960) {
  1804. pEncInfo->mapCfg.tiledBaseAddr = pEncInfo->vbFrame.phys_addr;
  1805. }
  1806. if (!ConfigSecAXICoda9(pCodecInst->coreIdx, instance->codecMode, &pEncInfo->secAxiInfo, stride, height, 0))
  1807. return RETCODE_INSUFFICIENT_RESOURCE;
  1808. if (pCodecInst->productId == PRODUCT_ID_960) {
  1809. val = SetTiledMapType(pCodecInst->coreIdx, &pEncInfo->mapCfg, mapType,stride, pEncInfo->openParam.cbcrInterleave, &pEncInfo->dramCfg);
  1810. }
  1811. else {
  1812. if (mapType != LINEAR_FRAME_MAP && mapType != LINEAR_FIELD_MAP)
  1813. val = SetTiledMapType(pCodecInst->coreIdx, &pEncInfo->mapCfg, mapType, (stride > height)?stride:height, pEncInfo->openParam.cbcrInterleave, &pEncInfo->dramCfg);
  1814. else
  1815. val = SetTiledMapType(pCodecInst->coreIdx, &pEncInfo->mapCfg, mapType,stride, pEncInfo->openParam.cbcrInterleave, &pEncInfo->dramCfg);
  1816. }
  1817. if (val == 0)
  1818. return RETCODE_INVALID_PARAM;
  1819. SetEncFrameMemInfo(pCodecInst);
  1820. paraBuffer = VpuReadReg(pCodecInst->coreIdx, BIT_PARA_BUF_ADDR);
  1821. // Let the decoder know the addresses of the frame buffers.
  1822. for (i=0; i<pEncInfo->numFrameBuffers; i++)
  1823. {
  1824. frameAddr[i][0][0] = (pEncInfo->frameBufPool[i].bufY >> 24) & 0xFF;
  1825. frameAddr[i][0][1] = (pEncInfo->frameBufPool[i].bufY >> 16) & 0xFF;
  1826. frameAddr[i][0][2] = (pEncInfo->frameBufPool[i].bufY >> 8) & 0xFF;
  1827. frameAddr[i][0][3] = (pEncInfo->frameBufPool[i].bufY >> 0) & 0xFF;
  1828. frameAddr[i][1][0] = (pEncInfo->frameBufPool[i].bufCb >> 24) & 0xFF;
  1829. frameAddr[i][1][1] = (pEncInfo->frameBufPool[i].bufCb >> 16) & 0xFF;
  1830. frameAddr[i][1][2] = (pEncInfo->frameBufPool[i].bufCb >> 8) & 0xFF;
  1831. frameAddr[i][1][3] = (pEncInfo->frameBufPool[i].bufCb >> 0) & 0xFF;
  1832. frameAddr[i][2][0] = (pEncInfo->frameBufPool[i].bufCr >> 24) & 0xFF;
  1833. frameAddr[i][2][1] = (pEncInfo->frameBufPool[i].bufCr >> 16) & 0xFF;
  1834. frameAddr[i][2][2] = (pEncInfo->frameBufPool[i].bufCr >> 8) & 0xFF;
  1835. frameAddr[i][2][3] = (pEncInfo->frameBufPool[i].bufCr >> 0) & 0xFF;
  1836. }
  1837. VpuWriteMem(pCodecInst->coreIdx, paraBuffer, (BYTE *)frameAddr, sizeof(frameAddr), VDI_BIG_ENDIAN);
  1838. if (pCodecInst->productId == PRODUCT_ID_980) {
  1839. for (i=0; i<pEncInfo->numFrameBuffers; i++) {
  1840. frameAddr[i][0][0] = (pEncInfo->frameBufPool[i].bufYBot >> 24) & 0xFF;
  1841. frameAddr[i][0][1] = (pEncInfo->frameBufPool[i].bufYBot >> 16) & 0xFF;
  1842. frameAddr[i][0][2] = (pEncInfo->frameBufPool[i].bufYBot >> 8) & 0xFF;
  1843. frameAddr[i][0][3] = (pEncInfo->frameBufPool[i].bufYBot >> 0) & 0xFF;
  1844. frameAddr[i][1][0] = (pEncInfo->frameBufPool[i].bufCbBot >> 24) & 0xFF;
  1845. frameAddr[i][1][1] = (pEncInfo->frameBufPool[i].bufCbBot >> 16) & 0xFF;
  1846. frameAddr[i][1][2] = (pEncInfo->frameBufPool[i].bufCbBot >> 8) & 0xFF;
  1847. frameAddr[i][1][3] = (pEncInfo->frameBufPool[i].bufCbBot >> 0) & 0xFF;
  1848. frameAddr[i][2][0] = (pEncInfo->frameBufPool[i].bufCrBot >> 24) & 0xFF;
  1849. frameAddr[i][2][1] = (pEncInfo->frameBufPool[i].bufCrBot >> 16) & 0xFF;
  1850. frameAddr[i][2][2] = (pEncInfo->frameBufPool[i].bufCrBot >> 8) & 0xFF;
  1851. frameAddr[i][2][3] = (pEncInfo->frameBufPool[i].bufCrBot >> 0) & 0xFF;
  1852. }
  1853. VpuWriteMem(pCodecInst->coreIdx, paraBuffer+384+128, (BYTE *)frameAddr, sizeof(frameAddr), VDI_BIG_ENDIAN);
  1854. }
  1855. // Tell the codec how much frame buffers were allocated.
  1856. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_BUF_NUM, pEncInfo->numFrameBuffers);
  1857. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_BUF_STRIDE, stride);
  1858. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_BIT_ADDR, pEncInfo->secAxiInfo.u.coda9.bufBitUse);
  1859. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_IPACDC_ADDR, pEncInfo->secAxiInfo.u.coda9.bufIpAcDcUse);
  1860. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_DBKY_ADDR, pEncInfo->secAxiInfo.u.coda9.bufDbkYUse);
  1861. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_DBKC_ADDR, pEncInfo->secAxiInfo.u.coda9.bufDbkCUse);
  1862. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_AXI_OVL_ADDR, pEncInfo->secAxiInfo.u.coda9.bufOvlUse);
  1863. if (pAttr->framebufferCacheType == FramebufCacheMaverickII) {
  1864. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_CACHE_CONFIG, pEncInfo->cacheConfig.type2.CacheMode);
  1865. }
  1866. else if (pAttr->framebufferCacheType == FramebufCacheMaverickI) {
  1867. // Maverick Cache Configuration
  1868. val = (pEncInfo->cacheConfig.type1.luma.cfg.PageSizeX << 28) |
  1869. (pEncInfo->cacheConfig.type1.luma.cfg.PageSizeY << 24) |
  1870. (pEncInfo->cacheConfig.type1.luma.cfg.CacheSizeX << 20) |
  1871. (pEncInfo->cacheConfig.type1.luma.cfg.CacheSizeY << 16) |
  1872. (pEncInfo->cacheConfig.type1.chroma.cfg.PageSizeX << 12) |
  1873. (pEncInfo->cacheConfig.type1.chroma.cfg.PageSizeY << 8) |
  1874. (pEncInfo->cacheConfig.type1.chroma.cfg.CacheSizeX << 4) |
  1875. (pEncInfo->cacheConfig.type1.chroma.cfg.CacheSizeY << 0);
  1876. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_CACHE_SIZE, val);
  1877. val = (pEncInfo->cacheConfig.type1.Bypass << 4) |
  1878. (pEncInfo->cacheConfig.type1.DualConf << 2) |
  1879. (pEncInfo->cacheConfig.type1.PageMerge << 0);
  1880. val = val << 24;
  1881. val |= (pEncInfo->cacheConfig.type1.luma.cfg.BufferSize << 16) |
  1882. (pEncInfo->cacheConfig.type1.chroma.cfg.BufferSize << 8) |
  1883. (pEncInfo->cacheConfig.type1.chroma.cfg.BufferSize << 8);
  1884. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_CACHE_CONFIG, val);
  1885. }
  1886. num = pEncInfo->numFrameBuffers;
  1887. if (pCodecInst->productId == PRODUCT_ID_960) {
  1888. Uint32 subsampleLumaSize = stride*height;
  1889. Uint32 subsampleChromaSize = stride*height/4; // FORMAT_420
  1890. vpu_buffer_t vbBuf;
  1891. FrameBuffer* pFb;
  1892. vbBuf.size = subsampleLumaSize + 2*subsampleChromaSize;
  1893. vbBuf.phys_addr = (PhysicalAddress)0;
  1894. if (vdi_allocate_dma_memory(pCodecInst->coreIdx, &vbBuf, ENC_ETC, pCodecInst->instIndex) < 0) {
  1895. pEncInfo->vbSubSampFrame.size = 0;
  1896. pEncInfo->vbSubSampFrame.phys_addr = 0;
  1897. return RETCODE_INSUFFICIENT_RESOURCE;
  1898. }
  1899. pFb = &pEncInfo->frameBufPool[num];
  1900. pFb->bufY = vbBuf.phys_addr;
  1901. pFb->bufCb = (PhysicalAddress)-1;
  1902. pFb->bufCr = (PhysicalAddress)-1;
  1903. pFb->updateFbInfo = TRUE;
  1904. ret = UpdateFrameBufferAddr(LINEAR_FRAME_MAP, pFb, 1, subsampleLumaSize, subsampleChromaSize);
  1905. if (ret != RETCODE_SUCCESS) {
  1906. pEncInfo->vbSubSampFrame.size = 0;
  1907. pEncInfo->vbSubSampFrame.phys_addr = 0;
  1908. return RETCODE_INSUFFICIENT_RESOURCE;
  1909. }
  1910. pEncInfo->vbSubSampFrame = vbBuf;
  1911. num++;
  1912. // Set Sub-Sampling buffer for ME-Reference and DBK-Reconstruction
  1913. // BPU will swap below two buffer internally every pic by pic
  1914. val = GetXY2AXIAddr(&pEncInfo->mapCfg, 0, 0, 0, stride, pFb);
  1915. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_SUBSAMP_A, val);
  1916. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_SUBSAMP_B, val+(stride*height/2));
  1917. if (pCodecInst->codecMode == AVC_ENC && pCodecInst->codecModeAux == AVC_AUX_MVC) {
  1918. vbBuf.size = subsampleLumaSize + 2*subsampleChromaSize;
  1919. vbBuf.phys_addr = (PhysicalAddress)0;
  1920. if (vdi_allocate_dma_memory(pCodecInst->coreIdx, &vbBuf, ENC_ETC, pCodecInst->instIndex) < 0) {
  1921. pEncInfo->vbSubSampFrame.size = 0;
  1922. pEncInfo->vbSubSampFrame.phys_addr = 0;
  1923. return RETCODE_INSUFFICIENT_RESOURCE;
  1924. }
  1925. pFb = &pEncInfo->frameBufPool[num];
  1926. pFb->bufY = vbBuf.phys_addr;
  1927. pFb->bufCb = (PhysicalAddress)-1;
  1928. pFb->bufCr = (PhysicalAddress)-1;
  1929. pFb->updateFbInfo = TRUE;
  1930. ret = UpdateFrameBufferAddr(LINEAR_FRAME_MAP, pFb, 1, subsampleLumaSize, subsampleChromaSize);
  1931. if (ret != RETCODE_SUCCESS) {
  1932. pEncInfo->vbMvcSubSampFrame.size = 0;
  1933. pEncInfo->vbMvcSubSampFrame.phys_addr = 0;
  1934. return RETCODE_INSUFFICIENT_RESOURCE;
  1935. }
  1936. pEncInfo->vbMvcSubSampFrame = vbBuf;
  1937. val = GetXY2AXIAddr(&pEncInfo->mapCfg, 0, 0, 0, stride, pFb);
  1938. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_SUBSAMP_A_MVC, val);
  1939. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_SUBSAMP_B_MVC, val+(stride*height/2));
  1940. }
  1941. }
  1942. if (pCodecInst->codecMode == MP4_ENC) {
  1943. // MPEG4 Encoder Data-Partitioned bitstream temporal buffer
  1944. pEncInfo->vbScratch.size = SIZE_MP4ENC_DATA_PARTITION;
  1945. if (vdi_allocate_dma_memory(pCodecInst->coreIdx, &pEncInfo->vbScratch, ENC_ETC, pCodecInst->instIndex)<0)
  1946. return RETCODE_INSUFFICIENT_RESOURCE;
  1947. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_DP_BUF_BASE, pEncInfo->vbScratch.phys_addr);
  1948. VpuWriteReg(pCodecInst->coreIdx, CMD_SET_FRAME_DP_BUF_SIZE, pEncInfo->vbScratch.size>>10);
  1949. }
  1950. SetPendingInst(pCodecInst->coreIdx, pCodecInst);
  1951. Coda9BitIssueCommand(pCodecInst->coreIdx, pCodecInst, SET_FRAME_BUF);
  1952. if (vdi_wait_vpu_busy(pCodecInst->coreIdx, __VPU_BUSY_TIMEOUT, BIT_BUSY_FLAG) == -1) {
  1953. if (pCodecInst->loggingEnable)
  1954. vdi_log(pCodecInst->coreIdx, SET_FRAME_BUF, 2);
  1955. return RETCODE_VPU_RESPONSE_TIMEOUT;
  1956. }
  1957. if (pCodecInst->loggingEnable)
  1958. vdi_log(pCodecInst->coreIdx, SET_FRAME_BUF, 0);
  1959. if (VpuReadReg(pCodecInst->coreIdx, RET_SET_FRAME_SUCCESS) & (1UL<<31)) {
  1960. return RETCODE_MEMORY_ACCESS_VIOLATION;
  1961. }
  1962. return RETCODE_SUCCESS;
  1963. }
  1964. RetCode Coda9VpuEncode(CodecInst* pCodecInst, EncParam* param)
  1965. {
  1966. EncInfo* pEncInfo;
  1967. FrameBuffer* pSrcFrame;
  1968. Uint32 rotMirMode;
  1969. Uint32 val;
  1970. vpu_instance_pool_t *vip;
  1971. #ifdef CLIP_PIC_DELTA_QP
  1972. int row_max_dqp_minus = 0;
  1973. int row_max_dqp_plus = 0;
  1974. #endif
  1975. pEncInfo = &pCodecInst->CodecInfo->encInfo;
  1976. vip = (vpu_instance_pool_t *)vdi_get_instance_pool(pCodecInst->coreIdx);
  1977. if (!vip) {
  1978. return RETCODE_INVALID_HANDLE;
  1979. }
  1980. pSrcFrame = param->sourceFrame;
  1981. rotMirMode = 0;
  1982. if (pEncInfo->rotationEnable == TRUE) {
  1983. switch (pEncInfo->rotationAngle) {
  1984. case 0:
  1985. rotMirMode |= 0x0;
  1986. break;
  1987. case 90:
  1988. rotMirMode |= 0x1;
  1989. break;
  1990. case 180:
  1991. rotMirMode |= 0x2;
  1992. break;
  1993. case 270:
  1994. rotMirMode |= 0x3;
  1995. break;
  1996. }
  1997. }
  1998. if (pEncInfo->mirrorEnable == TRUE) {
  1999. switch (pEncInfo->mirrorDirection) {
  2000. case MIRDIR_NONE :
  2001. rotMirMode |= 0x0;
  2002. break;
  2003. case MIRDIR_VER :
  2004. rotMirMode |= 0x4;
  2005. break;
  2006. case MIRDIR_HOR :
  2007. rotMirMode |= 0x8;
  2008. break;
  2009. case MIRDIR_HOR_VER :
  2010. rotMirMode |= 0xc;
  2011. break;
  2012. }
  2013. }
  2014. if (pCodecInst->productId == PRODUCT_ID_980) {
  2015. rotMirMode |= ((pSrcFrame->endian&0x03)<<16);
  2016. rotMirMode |= ((pSrcFrame->cbcrInterleave&0x01)<<18);
  2017. rotMirMode |= ((pSrcFrame->sourceLBurstEn&0x01)<<4);
  2018. }
  2019. else {
  2020. rotMirMode |= ((pSrcFrame->sourceLBurstEn&0x01)<<4);
  2021. #if defined(SUPPORT_NV21) || defined(SUPPORT_ENC_NV21)
  2022. rotMirMode |= ((pSrcFrame->cbcrInterleave&0x01)<<18);
  2023. rotMirMode |= pEncInfo->openParam.nv21 << 21;
  2024. #endif
  2025. }
  2026. if (pCodecInst->productId == PRODUCT_ID_980 && pCodecInst->codecMode == AVC_ENC)
  2027. {
  2028. }
  2029. if (pCodecInst->productId == PRODUCT_ID_960) {
  2030. if (pEncInfo->mapType > LINEAR_FRAME_MAP && pEncInfo->mapType <= TILED_MIXED_V_MAP) {
  2031. SetTiledFrameBase(pCodecInst->coreIdx, pEncInfo->vbFrame.phys_addr);
  2032. }
  2033. else {
  2034. SetTiledFrameBase(pCodecInst->coreIdx, 0);
  2035. }
  2036. }
  2037. if (pEncInfo->mapType != LINEAR_FRAME_MAP && pEncInfo->mapType != LINEAR_FIELD_MAP) {
  2038. if (pEncInfo->stride > pEncInfo->frameBufferHeight)
  2039. val = SetTiledMapType(pCodecInst->coreIdx, &pEncInfo->mapCfg, pEncInfo->mapType, pEncInfo->stride, pEncInfo->openParam.cbcrInterleave, &pEncInfo->dramCfg);
  2040. else
  2041. val = SetTiledMapType(pCodecInst->coreIdx, &pEncInfo->mapCfg, pEncInfo->mapType, pEncInfo->frameBufferHeight, pEncInfo->openParam.cbcrInterleave, &pEncInfo->dramCfg);
  2042. } else {
  2043. val = SetTiledMapType(pCodecInst->coreIdx, &pEncInfo->mapCfg, pEncInfo->mapType, pEncInfo->stride, pEncInfo->openParam.cbcrInterleave, &pEncInfo->dramCfg);
  2044. }
  2045. if (val == 0) {
  2046. return RETCODE_INVALID_PARAM;
  2047. }
  2048. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_ROT_MODE, rotMirMode);
  2049. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_QS, param->quantParam);
  2050. if (param->skipPicture) {
  2051. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_OPTION, 1);
  2052. }
  2053. else {
  2054. // Registering Source Frame Buffer information
  2055. // Hide GDI IF under FW level
  2056. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_INDEX, pSrcFrame->myIndex);
  2057. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_STRIDE, pSrcFrame->stride);
  2058. if (pEncInfo->openParam.cbcrOrder == CBCR_ORDER_NORMAL) {
  2059. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_ADDR_Y, pSrcFrame->bufY);
  2060. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_ADDR_CB, pSrcFrame->bufCb);
  2061. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_ADDR_CR, pSrcFrame->bufCr);
  2062. }
  2063. else { // CBCR_ORDER_REVERSED (YV12)
  2064. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_ADDR_Y, pSrcFrame->bufY);
  2065. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_ADDR_CB, pSrcFrame->bufCr);
  2066. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_SRC_ADDR_CR, pSrcFrame->bufCb);
  2067. }
  2068. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_OPTION, (param->forceIPicture << 1 & 0x2));
  2069. }
  2070. if (pEncInfo->ringBufferEnable == 0) {
  2071. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_BB_START, param->picStreamBufferAddr);
  2072. VpuWriteReg(pCodecInst->coreIdx, CMD_ENC_PIC_BB_SIZE, param->picStreamBufferSize/1024); // size in KB
  2073. VpuWriteReg(pCodecInst->coreIdx, pEncInfo->streamRdPtrRegAddr, param->picStreamBufferAddr);
  2074. pEncInfo->streamRdPtr = param->picStreamBufferAddr;
  2075. }
  2076. val = 0;
  2077. val = (
  2078. (pEncInfo->secAxiInfo.u.coda9.useBitEnable&0x01)<<0 |
  2079. (pEncInfo->secAxiInfo.u.coda9.useIpEnable&0x01)<<1 |
  2080. (pEncInfo->secAxiInfo.u.coda9.useDbkYEnable&0x01)<<2 |
  2081. (pEncInfo->secAxiInfo.u.coda9.useDbkCEnable&0x01)<<3 |
  2082. (pEncInfo->secAxiInfo.u.coda9.useOvlEnable&0x01)<<4 |
  2083. (pEncInfo->secAxiInfo.u.coda9.useBtpEnable&0x01)<<5 |
  2084. (pEncInfo->secAxiInfo.u.coda9.useBitEnable&0x01)<<8 |
  2085. (pEncInfo->secAxiInfo.u.coda9.useIpEnable&0x01)<<9 |
  2086. (pEncInfo->secAxiInfo.u.coda9.useDbkYEnable&0x01)<<10 |
  2087. (pEncInfo->secAxiInfo.u.coda9.useDbkCEnable&0x01)<<11 |
  2088. (pEncInfo->secAxiInfo.u.coda9.useOvlEnable&0x01)<<12 |
  2089. (pEncInfo->secAxiInfo.u.coda9.useBtpEnable&0x01)<<13 );
  2090. VpuWriteReg(pCodecInst->coreIdx, BIT_AXI_SRAM_USE, val);
  2091. VpuWriteReg(pCodecInst->coreIdx, pEncInfo->streamWrPtrRegAddr, pEncInfo->streamWrPtr);
  2092. VpuWriteReg(pCodecInst->coreIdx, pEncInfo->streamRdPtrRegAddr, pEncInfo->streamRdPtr);
  2093. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_PARAM, pEncInfo->streamEndflag);
  2094. SetEncFrameMemInfo(pCodecInst);
  2095. val = 0;
  2096. if (pEncInfo->ringBufferEnable == 0) {
  2097. if (pEncInfo->lineBufIntEn)
  2098. val |= (0x1<<6);
  2099. val |= (0x1<<5);
  2100. val |= (0x1<<4);
  2101. }
  2102. else {
  2103. val |= (0x1<<3);
  2104. }
  2105. val |= pEncInfo->openParam.streamEndian;
  2106. VpuWriteReg(pCodecInst->coreIdx, BIT_BIT_STREAM_CTRL, val);
  2107. Coda9BitIssueCommand(pCodecInst->coreIdx, pCodecInst, PIC_RUN);
  2108. return RETCODE_SUCCESS;
  2109. }
  2110. RetCode Coda9VpuEncGetResult(CodecInst* pCodecInst, EncOutputInfo* info)
  2111. {
  2112. EncInfo* pEncInfo;
  2113. PhysicalAddress rdPtr;
  2114. PhysicalAddress wrPtr;
  2115. Uint32 pic_enc_result;
  2116. pEncInfo = &pCodecInst->CodecInfo->encInfo;
  2117. if (pCodecInst->loggingEnable)
  2118. vdi_log(pCodecInst->coreIdx, PIC_RUN, 0);
  2119. pic_enc_result = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_SUCCESS);
  2120. if (pic_enc_result & (1UL<<31)) {
  2121. return RETCODE_MEMORY_ACCESS_VIOLATION;
  2122. }
  2123. if (pCodecInst->productId == PRODUCT_ID_980) {
  2124. if (pic_enc_result & 2) { //top field coding done
  2125. if (!pEncInfo->fieldDone)
  2126. pEncInfo->fieldDone = 1;
  2127. }
  2128. else
  2129. {
  2130. pEncInfo->frameIdx = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_FRAME_NUM);
  2131. pEncInfo->fieldDone = 0;
  2132. }
  2133. }
  2134. info->picType = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_TYPE);
  2135. if (pEncInfo->ringBufferEnable == 0) {
  2136. rdPtr = VpuReadReg(pCodecInst->coreIdx, pEncInfo->streamRdPtrRegAddr);
  2137. wrPtr = VpuReadReg(pCodecInst->coreIdx, pEncInfo->streamWrPtrRegAddr);
  2138. info->bitstreamBuffer = rdPtr;
  2139. info->bitstreamSize = wrPtr - rdPtr;
  2140. }
  2141. info->numOfSlices = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_SLICE_NUM);
  2142. info->bitstreamWrapAround = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_FLAG);
  2143. info->reconFrameIndex = VpuReadReg(pCodecInst->coreIdx, RET_ENC_PIC_FRAME_IDX);
  2144. if (info->reconFrameIndex < MAX_REG_FRAME) {
  2145. info->reconFrame = pEncInfo->frameBufPool[info->reconFrameIndex];
  2146. }
  2147. info->encSrcIdx = info->reconFrameIndex;
  2148. pEncInfo->streamWrPtr = VpuReadReg(pCodecInst->coreIdx, pEncInfo->streamWrPtrRegAddr);
  2149. pEncInfo->streamEndflag = VpuReadReg(pCodecInst->coreIdx, BIT_BIT_STREAM_PARAM);
  2150. info->frameCycle = VpuReadReg(pCodecInst->coreIdx, BIT_FRAME_CYCLE);
  2151. info->rdPtr = pEncInfo->streamRdPtr;
  2152. info->wrPtr = pEncInfo->streamWrPtr;
  2153. return RETCODE_SUCCESS;
  2154. }
  2155. RetCode Coda9VpuEncGiveCommand(CodecInst* pCodecInst, CodecCommand cmd, void* param)
  2156. {
  2157. RetCode ret = RETCODE_SUCCESS;
  2158. UNREFERENCED_PARAMETER(cmd);
  2159. UNREFERENCED_PARAMETER(param);
  2160. switch (cmd) {
  2161. default:
  2162. ret = RETCODE_NOT_SUPPORTED_FEATURE;
  2163. }
  2164. return ret;
  2165. }