vdi.c 33 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207
  1. // SPDX-License-Identifier: LGPL-2.1 OR BSD-3-Clause
  2. /*
  3. * Copyright (c) 2019, Chips&Media
  4. * All rights reserved.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. *
  9. * 1. Redistributions of source code must retain the above copyright notice, this
  10. * list of conditions and the following disclaimer.
  11. * 2. Redistributions in binary form must reproduce the above copyright notice,
  12. * this list of conditions and the following disclaimer in the documentation
  13. * and/or other materials provided with the distribution.
  14. *
  15. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  16. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  17. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
  19. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  21. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  22. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  23. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  24. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25. */
  26. #include <stdio.h>
  27. #include <stdlib.h>
  28. #include "../vdi.h"
  29. #include "../vdi_osal.h"
  30. #include "../mm.h"
  31. #include "coda9/coda9_regdefine.h"
  32. #include "wave/wave5_regdefine.h"
  33. #include "vpuapi/vpuapi.h"
  34. #include "main_helper.h"
  35. #include "misc/debug.h"
  36. #if defined(_WIN32) || defined(__WIN32__) || defined(_WIN64) || defined(WIN32) || defined(__MINGW32__)
  37. #elif defined(linux) || defined(__linux) || defined(ANDROID)
  38. #else
  39. #if (REQUIRED_VPU_MEMORY_SIZE > VPUDRV_INIT_VIDEO_MEMORY_SIZE_IN_BYTE)
  40. #error "Warnning : VPU memory will be overflow"
  41. #endif
  42. #endif
  43. #define VPU_BIT_REG_SIZE (0x4000*MAX_NUM_VPU_CORE)
  44. # define VPU_BIT_REG_BASE 0x40000000
  45. #define VDI_SRAM_BASE_ADDR 0x00
  46. #define VDI_CODA9_SRAM_SIZE 0x34600 // FHD MAX size, 0x17D00 4K MAX size 0x34600
  47. #define VDI_WAVE511_SRAM_SIZE 0x2D000 /* H.265 Main10 : 8Kx4K -> 184320, 4Kx2K -> 92160
  48. * H.265 Main : 8Kx4K -> 155648, 4Kx2K -> 77824
  49. */
  50. #define VDI_WAVE521_SRAM_SIZE 0x20400 /* 10bit profile : 8Kx8K -> 132096, 4Kx2K -> 66560
  51. * 8bit profile : 8Kx8K -> 99328, 4Kx2K -> 51176
  52. */
  53. #define VDI_WAVE521C_SRAM_SIZE 0x2D000 /* H.265 Main10 : 8Kx4K -> 184320, 4Kx2K -> 92160
  54. * H.265 Main : 8Kx4K -> 155648, 4Kx2K -> 77824
  55. * NOTE: Decoder > Encoder
  56. */
  57. #define VPU_DRAM_PHYSICAL_BASE 0x00
  58. #define VPU_DRAM_SIZE (128*1024*1024)
  59. #ifdef SUPPORT_MULTI_CORE_IN_ONE_DRIVER
  60. #define VPU_CORE_BASE_OFFSET 0x4000
  61. #endif
  62. #define VDI_SYSTEM_ENDIAN VDI_LITTLE_ENDIAN
  63. #define VDI_128BIT_BUS_SYSTEM_ENDIAN VDI_128BIT_LITTLE_ENDIAN
  64. typedef struct vpu_buffer_t vpudrv_buffer_t;
  65. typedef struct vpu_buffer_pool_t
  66. {
  67. vpudrv_buffer_t vdb;
  68. int inuse;
  69. } vpu_buffer_pool_t;
  70. typedef struct {
  71. unsigned long coreIdx;
  72. int vpu_fd;
  73. vpu_instance_pool_t *pvip;
  74. int task_num;
  75. int clock_state;
  76. vpudrv_buffer_t vdb_video_memory;
  77. vpudrv_buffer_t vdb_register;
  78. vpu_buffer_t vpu_common_memory;
  79. vpu_buffer_pool_t vpu_buffer_pool[MAX_VPU_BUFFER_POOL];
  80. int vpu_buffer_pool_count;
  81. int product_code;
  82. } vdi_info_t;
  83. static vdi_info_t s_vdi_info[MAX_VPU_CORE_NUM];
  84. #ifdef SUPPORT_MULTI_CORE_IN_ONE_DRIVER
  85. static vpu_instance_pool_t s_vip[MAX_VPU_CORE_NUM]; // it can be used for a buffer space to save context for app process. to support running VPU in multiple process. this space should be a shared buffer.
  86. #else
  87. static vpu_instance_pool_t s_vip; // it can be used for a buffer space to save context for app process. to support running VPU in multiple process. this space should be a shared buffer.
  88. #endif
  89. static int swap_endian(unsigned long coreIdx, unsigned char *data, int len, int endian);
  90. int vdi_lock(unsigned long coreIdx)
  91. {
  92. /* need to implement */
  93. return 0;
  94. }
  95. void vdi_unlock(unsigned long coreIdx)
  96. {
  97. /* need to implement */
  98. }
  99. int vdi_disp_lock(unsigned long coreIdx)
  100. {
  101. /* need to implement */
  102. return 0;
  103. }
  104. void vdi_disp_unlock(unsigned long coreIdx)
  105. {
  106. /* need to implement */
  107. }
  108. int vmem_lock_init(unsigned long coreIdx)
  109. {
  110. /* need to implement */
  111. return 0;
  112. }
  113. int vmem_lock(unsigned long coreIdx)
  114. {
  115. /* need to implement */
  116. return 0;
  117. }
  118. void vmem_unlock(unsigned long coreIdx)
  119. {
  120. /* need to implement */
  121. }
  122. int vmem_lock_deinit(unsigned long coreIdx)
  123. {
  124. /* need to implement */
  125. return 0;
  126. }
  127. int vdi_probe(unsigned long coreIdx)
  128. {
  129. int ret;
  130. ret = vdi_init(coreIdx);
  131. vdi_release(coreIdx);
  132. return ret;
  133. }
  134. int vdi_init(unsigned long coreIdx)
  135. {
  136. int ret;
  137. vdi_info_t *vdi;
  138. int i;
  139. Uint32 product_code;
  140. if (coreIdx >= MAX_NUM_VPU_CORE)
  141. return 0;
  142. vdi = &s_vdi_info[coreIdx];
  143. if (vdi->vpu_fd != -1 && vdi->vpu_fd != 0x00)
  144. {
  145. vdi->task_num++;
  146. return 0;
  147. }
  148. vdi->vpu_fd = 1;
  149. osal_memset(vdi->vpu_buffer_pool, 0x00, sizeof(vpu_buffer_pool_t)*MAX_VPU_BUFFER_POOL);
  150. if (!vdi_get_instance_pool(coreIdx))
  151. {
  152. VLOG(ERR, "[VDI] fail to create shared info for saving context \n");
  153. goto ERR_VDI_INIT;
  154. }
  155. vdi->vdb_video_memory.phys_addr = VPU_DRAM_PHYSICAL_BASE;
  156. vdi->vdb_video_memory.size = VPU_DRAM_SIZE;
  157. #if 0
  158. if (REQUIRED_VPU_MEMORY_SIZE > vdi->vdb_video_memory.size)
  159. {
  160. VLOG(ERR, "[VDI] Warning : VPU memory will be overflow\n");
  161. }
  162. #endif
  163. if (vdi_allocate_common_memory(coreIdx) < 0)
  164. {
  165. VLOG(ERR, "[VDI] fail to get vpu common buffer from driver\n");
  166. goto ERR_VDI_INIT;
  167. }
  168. if (!vdi->pvip->instance_pool_inited)
  169. osal_memset(&vdi->pvip->vmem, 0x00, sizeof(video_mm_t));
  170. #ifdef SUPPORT_MULTI_CORE_IN_ONE_DRIVER
  171. ret = vmem_init(&vdi->pvip->vmem, vdi->vdb_video_memory.phys_addr + (vdi->pvip->vpu_common_buffer.size*MAX_VPU_CORE_NUM),
  172. vdi->vdb_video_memory.size - (vdi->pvip->vpu_common_buffer.size*MAX_VPU_CORE_NUM));
  173. #else
  174. ret = vmem_init(&vdi->pvip->vmem, vdi->vdb_video_memory.phys_addr + vdi->pvip->vpu_common_buffer.size,
  175. vdi->vdb_video_memory.size - vdi->pvip->vpu_common_buffer.size);
  176. #endif
  177. vmem_lock_init(coreIdx);
  178. if (ret < 0)
  179. {
  180. VLOG(ERR, "[VDI] fail to init vpu memory management logic\n");
  181. goto ERR_VDI_INIT;
  182. }
  183. vdi->vdb_register.phys_addr = VPU_BIT_REG_BASE;
  184. vdi->vdb_register.virt_addr = VPU_BIT_REG_BASE;
  185. vdi->vdb_register.size = VPU_BIT_REG_SIZE;
  186. vdi_set_clock_gate(coreIdx, TRUE);
  187. vdi->product_code = vdi_read_register(coreIdx, VPU_PRODUCT_CODE_REGISTER);
  188. product_code = vdi->product_code;
  189. if (PRODUCT_CODE_W_SERIES(product_code))
  190. {
  191. if (vdi_read_register(coreIdx, W5_VCPU_CUR_PC) == 0) // if BIT processor is not running.
  192. {
  193. for (i=0; i<64; i++)
  194. vdi_write_register(coreIdx, (i*4) + 0x100, 0x0);
  195. }
  196. }
  197. else // CODA9XX
  198. {
  199. if (vdi_read_register(coreIdx, BIT_CUR_PC) == 0) // if BIT processor is not running.
  200. {
  201. for (i=0; i<64; i++)
  202. vdi_write_register(coreIdx, (i*4) + 0x100, 0x0);
  203. }
  204. }
  205. vdi_set_clock_gate(coreIdx, FALSE);
  206. vdi->coreIdx = coreIdx;
  207. vdi->task_num++;
  208. VLOG(INFO, "[VDI] success to init driver \n");
  209. return 0;
  210. ERR_VDI_INIT:
  211. vdi_release(coreIdx);
  212. return -1;
  213. }
  214. int vdi_set_bit_firmware_to_pm(unsigned long coreIdx, const unsigned short *code)
  215. {
  216. return 0;
  217. }
  218. int vdi_release(unsigned long coreIdx)
  219. {
  220. int i;
  221. vpudrv_buffer_t vdb = {0, };
  222. vdi_info_t *vdi = &s_vdi_info[coreIdx];
  223. if (!vdi || vdi->vpu_fd == -1 || vdi->vpu_fd == 0x00)
  224. return 0;
  225. if (vdi_lock(coreIdx) < 0)
  226. {
  227. VLOG(ERR, "[VDI] fail to handle lock function\n");
  228. return -1;
  229. }
  230. if (vdi->task_num > 1) // means that the opened instance remains
  231. {
  232. vdi->task_num--;
  233. vdi_unlock(coreIdx);
  234. return 0;
  235. }
  236. vmem_lock_deinit(coreIdx);
  237. vmem_exit(&vdi->pvip->vmem);
  238. osal_memset(&vdi->vdb_register, 0x00, sizeof(vpudrv_buffer_t));
  239. // get common memory information to free virtual address
  240. vdb.size = 0;
  241. for (i=0; i<MAX_VPU_BUFFER_POOL; i++)
  242. {
  243. if (vdi->vpu_common_memory.phys_addr >= vdi->vpu_buffer_pool[i].vdb.phys_addr &&
  244. vdi->vpu_common_memory.phys_addr < (vdi->vpu_buffer_pool[i].vdb.phys_addr + vdi->vpu_buffer_pool[i].vdb.size))
  245. {
  246. vdi->vpu_buffer_pool[i].inuse = 0;
  247. vdi->vpu_buffer_pool_count--;
  248. vdb = vdi->vpu_buffer_pool[i].vdb;
  249. break;
  250. }
  251. }
  252. if (vdb.size > 0)
  253. osal_memset(&vdi->vpu_common_memory, 0x00, sizeof(vpu_buffer_t));
  254. vdi->task_num--;
  255. vdi->vpu_fd = -1;
  256. vdi_unlock(coreIdx);
  257. osal_memset(vdi, 0x00, sizeof(vdi_info_t));
  258. return 0;
  259. }
  260. int vdi_get_common_memory(unsigned long coreIdx, vpu_buffer_t *vb)
  261. {
  262. vdi_info_t *vdi;
  263. if (coreIdx >= MAX_NUM_VPU_CORE)
  264. return -1;
  265. vdi = &s_vdi_info[coreIdx];
  266. if(!vdi || vdi->vpu_fd==-1 || vdi->vpu_fd==0x00)
  267. return -1;
  268. osal_memcpy(vb, &vdi->vpu_common_memory, sizeof(vpu_buffer_t));
  269. return 0;
  270. }
  271. int vdi_allocate_common_memory(unsigned long core_idx)
  272. {
  273. vdi_info_t *vdi = &s_vdi_info[core_idx];
  274. vpudrv_buffer_t vdb;
  275. int i;
  276. if (core_idx >= MAX_NUM_VPU_CORE)
  277. return -1;
  278. if(!vdi || vdi->vpu_fd==-1 || vdi->vpu_fd==0x00)
  279. return -1;
  280. if (vdi->pvip->vpu_common_buffer.size == 0)
  281. {
  282. vdb.size = SIZE_COMMON*MAX_VPU_CORE_NUM;
  283. vdb.phys_addr = vdi->vdb_video_memory.phys_addr; // set at the beginning of base address
  284. vdb.virt_addr = vdi->vdb_video_memory.phys_addr;
  285. vdb.base = vdi->vdb_video_memory.base;
  286. // convert os driver buffer type to vpu buffer type
  287. #ifdef SUPPORT_MULTI_CORE_IN_ONE_DRIVER
  288. vdi->pvip->vpu_common_buffer.size = SIZE_COMMON;
  289. vdi->pvip->vpu_common_buffer.phys_addr = (unsigned int)(vdb.phys_addr + (core_idx*SIZE_COMMON));
  290. vdi->pvip->vpu_common_buffer.base = (unsigned long)(vdb.base + (core_idx*SIZE_COMMON));
  291. vdi->pvip->vpu_common_buffer.virt_addr = (unsigned long)(vdb.virt_addr + (core_idx*SIZE_COMMON));
  292. #else
  293. vdi->pvip->vpu_common_buffer.size = SIZE_COMMON;
  294. vdi->pvip->vpu_common_buffer.phys_addr = (unsigned int)(vdb.phys_addr);
  295. vdi->pvip->vpu_common_buffer.base = (unsigned long)(vdb.base);
  296. vdi->pvip->vpu_common_buffer.virt_addr = (unsigned long)(vdb.virt_addr);
  297. #endif
  298. osal_memcpy(&vdi->vpu_common_memory, &vdi->pvip->vpu_common_buffer, sizeof(vpudrv_buffer_t));
  299. }
  300. else
  301. {
  302. vdb.size = SIZE_COMMON*MAX_VPU_CORE_NUM;
  303. vdb.phys_addr = vdi->vdb_video_memory.phys_addr; // set at the beginning of base address
  304. vdb.base = vdi->vdb_video_memory.base;
  305. vdb.virt_addr = vdi->vdb_video_memory.phys_addr;
  306. #ifdef SUPPORT_MULTI_CORE_IN_ONE_DRIVER
  307. vdi->pvip->vpu_common_buffer.virt_addr = (unsigned long)(vdb.virt_addr + (core_idx*SIZE_COMMON));
  308. #else
  309. vdi->pvip->vpu_common_buffer.virt_addr = vdb.virt_addr;
  310. #endif
  311. osal_memcpy(&vdi->vpu_common_memory, &vdi->pvip->vpu_common_buffer, sizeof(vpudrv_buffer_t));
  312. VLOG(INFO, "[VDI] vdi_allocate_common_memory, physaddr=0x%x, virtaddr=0x%x\n", (int)vdi->pvip->vpu_common_buffer.phys_addr, (int)vdi->pvip->vpu_common_buffer.virt_addr);
  313. }
  314. for (i=0; i<MAX_VPU_BUFFER_POOL; i++)
  315. {
  316. if (vdi->vpu_buffer_pool[i].inuse == 0)
  317. {
  318. vdi->vpu_buffer_pool[i].vdb = vdb;
  319. vdi->vpu_buffer_pool_count++;
  320. vdi->vpu_buffer_pool[i].inuse = 1;
  321. break;
  322. }
  323. }
  324. VLOG(INFO, "[VDI] vdi_get_common_memory physaddr=0x%x, size=%d, virtaddr=0x%x\n", vdi->vpu_common_memory.phys_addr, vdi->vpu_common_memory.size, vdi->vpu_common_memory.virt_addr);
  325. return 0;
  326. }
  327. vpu_instance_pool_t *vdi_get_instance_pool(unsigned long coreIdx)
  328. {
  329. vdi_info_t *vdi;
  330. if (coreIdx >= MAX_VPU_CORE_NUM)
  331. return NULL;
  332. vdi = &s_vdi_info[coreIdx];
  333. if(!vdi || vdi->vpu_fd == -1 || vdi->vpu_fd ==0x00 )
  334. return NULL;
  335. if (!vdi->pvip)
  336. {
  337. #ifdef SUPPORT_MULTI_CORE_IN_ONE_DRIVER
  338. vdi->pvip = &s_vip[coreIdx];
  339. #else
  340. vdi->pvip = &s_vip;
  341. #endif
  342. osal_memset(vdi->pvip, 0, sizeof(vpu_instance_pool_t));
  343. }
  344. return (vpu_instance_pool_t *)vdi->pvip;
  345. }
  346. int vdi_open_instance(unsigned long coreIdx, unsigned long instIdx)
  347. {
  348. vdi_info_t *vdi = NULL;
  349. if (coreIdx >= MAX_VPU_CORE_NUM)
  350. return -1;
  351. vdi = &s_vdi_info[coreIdx];
  352. if(!vdi || vdi->vpu_fd ==-1 || vdi->vpu_fd == 0x00)
  353. return -1;
  354. vdi->pvip->vpu_instance_num++;
  355. return 0;
  356. }
  357. int vdi_close_instance(unsigned long coreIdx, unsigned long instIdx)
  358. {
  359. vdi_info_t *vdi = NULL;
  360. if (coreIdx >= MAX_VPU_CORE_NUM)
  361. return -1;
  362. vdi = &s_vdi_info[coreIdx];
  363. if(!vdi || vdi->vpu_fd ==-1 || vdi->vpu_fd == 0x00)
  364. return -1;
  365. vdi->pvip->vpu_instance_num--;
  366. return 0;
  367. }
  368. int vdi_get_instance_num(unsigned long coreIdx)
  369. {
  370. vdi_info_t *vdi = NULL;
  371. if (coreIdx >= MAX_VPU_CORE_NUM)
  372. return -1;
  373. vdi = &s_vdi_info[coreIdx];
  374. if(!vdi || vdi->vpu_fd ==-1 || vdi->vpu_fd == 0x00)
  375. return -1;
  376. return vdi->pvip->vpu_instance_num;
  377. }
  378. int vdi_hw_reset(unsigned long coreIdx) // DEVICE_ADDR_SW_RESET
  379. {
  380. vdi_info_t *vdi = NULL;
  381. if (coreIdx >= MAX_VPU_CORE_NUM)
  382. return -1;
  383. vdi = &s_vdi_info[coreIdx];
  384. if(!vdi || !vdi || vdi->vpu_fd ==-1 || vdi->vpu_fd == 0x00)
  385. return -1;
  386. // to do any action for hw reset
  387. return 0;
  388. }
  389. void vdi_write_register(unsigned long coreIdx, unsigned int addr, unsigned int data)
  390. {
  391. vdi_info_t *vdi = NULL;
  392. unsigned long *reg_addr;
  393. if (coreIdx >= MAX_NUM_VPU_CORE)
  394. return;
  395. vdi = &s_vdi_info[coreIdx];
  396. if(!vdi || vdi->vpu_fd==-1 || vdi->vpu_fd == 0x00)
  397. return;
  398. #ifdef SUPPORT_MULTI_CORE_IN_ONE_DRIVER
  399. reg_addr = (unsigned long *)(addr + (unsigned long)vdi->vdb_register.virt_addr + (coreIdx*VPU_CORE_BASE_OFFSET));
  400. #else
  401. reg_addr = (unsigned long *)(addr + (unsigned long)vdi->vdb_register.virt_addr);
  402. #endif
  403. *(volatile unsigned long *)reg_addr = data;
  404. }
  405. unsigned int vdi_read_register(unsigned long coreIdx, unsigned int addr)
  406. {
  407. vdi_info_t *vdi = NULL;
  408. unsigned long *reg_addr;
  409. if (coreIdx >= MAX_NUM_VPU_CORE)
  410. return (unsigned int)-1;
  411. vdi = &s_vdi_info[coreIdx];
  412. if(!vdi || vdi->vpu_fd==-1 || vdi->vpu_fd == 0x00)
  413. return (unsigned int)-1;
  414. #ifdef SUPPORT_MULTI_CORE_IN_ONE_DRIVER
  415. reg_addr = (unsigned long *)(addr + (unsigned long)vdi->vdb_register.virt_addr + (coreIdx*VPU_CORE_BASE_OFFSET));
  416. #else
  417. reg_addr = (unsigned long *)(addr + (unsigned long)vdi->vdb_register.virt_addr);
  418. #endif
  419. return *(volatile unsigned long *)reg_addr;
  420. }
  421. #define FIO_TIMEOUT 10000
  422. unsigned int vdi_fio_read_register(unsigned long coreIdx, unsigned int addr)
  423. {
  424. unsigned int ctrl;
  425. unsigned int count = 0;
  426. unsigned int data = 0xffffffff;
  427. ctrl = (addr&0xffff);
  428. ctrl |= (0<<16); /* read operation */
  429. vdi_write_register(coreIdx, W5_VPU_FIO_CTRL_ADDR, ctrl);
  430. count = FIO_TIMEOUT;
  431. while (count--) {
  432. ctrl = vdi_read_register(coreIdx, W5_VPU_FIO_CTRL_ADDR);
  433. if (ctrl & 0x80000000) {
  434. data = vdi_read_register(coreIdx, W5_VPU_FIO_DATA);
  435. break;
  436. }
  437. }
  438. return data;
  439. }
  440. void vdi_fio_write_register(unsigned long coreIdx, unsigned int addr, unsigned int data)
  441. {
  442. unsigned int ctrl;
  443. unsigned int count = 0;
  444. vdi_write_register(coreIdx, W5_VPU_FIO_DATA, data);
  445. ctrl = (addr&0xffff);
  446. ctrl |= (1<<16); /* write operation */
  447. vdi_write_register(coreIdx, W5_VPU_FIO_CTRL_ADDR, ctrl);
  448. count = FIO_TIMEOUT;
  449. while (count--) {
  450. ctrl = vdi_read_register(coreIdx, W5_VPU_FIO_CTRL_ADDR);
  451. if (ctrl & 0x80000000) {
  452. break;
  453. }
  454. }
  455. }
  456. int vdi_clear_memory(unsigned long coreIdx, PhysicalAddress addr, int len, int endian)
  457. {
  458. vdi_info_t *vdi;
  459. vpudrv_buffer_t vdb;
  460. unsigned long offset;
  461. int i;
  462. Uint8* zero;
  463. #ifdef SUPPORT_MULTI_CORE_IN_ONE_DRIVER
  464. coreIdx = 0;
  465. #endif
  466. if (coreIdx >= MAX_NUM_VPU_CORE)
  467. return -1;
  468. vdi = &s_vdi_info[coreIdx];
  469. if(!vdi || vdi->vpu_fd == -1 || vdi->vpu_fd == 0x00)
  470. return -1;
  471. osal_memset(&vdb, 0x00, sizeof(vpudrv_buffer_t));
  472. for (i=0; i<MAX_VPU_BUFFER_POOL; i++)
  473. {
  474. if (vdi->vpu_buffer_pool[i].inuse == 1)
  475. {
  476. vdb = vdi->vpu_buffer_pool[i].vdb;
  477. if (addr >= vdb.phys_addr && addr < (vdb.phys_addr + vdb.size))
  478. break;
  479. }
  480. }
  481. if (!vdb.size) {
  482. VLOG(ERR, "address 0x%08x is not mapped address!!!\n", (int)addr);
  483. return -1;
  484. }
  485. offset = (unsigned long)(addr - vdb.phys_addr);
  486. zero = (Uint8*)osal_malloc(len);
  487. osal_memset((void*)zero, 0x00, len);
  488. osal_memcpy((void *)((unsigned long)vdb.virt_addr+offset), zero, len);
  489. osal_free(zero);
  490. return len;
  491. }
  492. int vdi_write_memory(unsigned long coreIdx, PhysicalAddress addr, unsigned char *data, int len, int endian)
  493. {
  494. vdi_info_t *vdi;
  495. vpudrv_buffer_t vdb = {0};
  496. unsigned long offset;
  497. int i;
  498. #ifdef SUPPORT_MULTI_CORE_IN_ONE_DRIVER
  499. coreIdx = 0;
  500. #endif
  501. vdi = &s_vdi_info[coreIdx];
  502. if(!vdi || vdi->vpu_fd==-1 || vdi->vpu_fd == 0x00)
  503. return -1;
  504. for (i=0; i<MAX_VPU_BUFFER_POOL; i++)
  505. {
  506. if (vdi->vpu_buffer_pool[i].inuse == 1)
  507. {
  508. vdb = vdi->vpu_buffer_pool[i].vdb;
  509. if (addr >= vdb.phys_addr && addr < (vdb.phys_addr + vdb.size))
  510. break;
  511. }
  512. }
  513. if (!vdb.size) { //lint !e644
  514. VLOG(ERR, "address 0x%08x is not mapped address!!!\n", addr);
  515. return -1;
  516. }
  517. offset = (unsigned long)(addr -vdb.phys_addr);
  518. swap_endian(coreIdx, data, len, endian);
  519. osal_memcpy((void *)((unsigned long)vdb.virt_addr+offset), data, len);
  520. return len;
  521. }
  522. int vdi_read_memory(unsigned long coreIdx, PhysicalAddress addr, unsigned char *data, int len, int endian)
  523. {
  524. vdi_info_t *vdi = NULL;
  525. vpudrv_buffer_t vdb = {0};
  526. unsigned long offset;
  527. int i;
  528. #ifdef SUPPORT_MULTI_CORE_IN_ONE_DRIVER
  529. coreIdx = 0;
  530. #endif
  531. if (coreIdx >= MAX_NUM_VPU_CORE)
  532. return -1;
  533. vdi = &s_vdi_info[coreIdx];
  534. if(!vdi || vdi->vpu_fd==-1 || vdi->vpu_fd == 0x00)
  535. return -1;
  536. for (i=0; i<MAX_VPU_BUFFER_POOL; i++)
  537. {
  538. if (vdi->vpu_buffer_pool[i].inuse == 1)
  539. {
  540. vdb = vdi->vpu_buffer_pool[i].vdb;
  541. if (addr >= vdb.phys_addr && addr < (vdb.phys_addr + vdb.size))
  542. break;
  543. }
  544. }
  545. if (!vdb.size) //lint !e644
  546. return -1;
  547. offset = (unsigned long)(addr -vdb.phys_addr);
  548. osal_memcpy(data, (const void *)((unsigned long)vdb.virt_addr+offset), len);
  549. swap_endian(coreIdx, data, len, endian);
  550. return len;
  551. }
  552. int vdi_allocate_dma_memory(unsigned long coreIdx, vpu_buffer_t *vb, int memTypes, int instIndex)
  553. {
  554. vdi_info_t *vdi = NULL;
  555. int i;
  556. unsigned long offset;
  557. vpudrv_buffer_t vdb = {0};
  558. #ifdef SUPPORT_MULTI_CORE_IN_ONE_DRIVER
  559. coreIdx = 0;
  560. #endif
  561. if (coreIdx >= MAX_NUM_VPU_CORE)
  562. return -1;
  563. vdi = &s_vdi_info[coreIdx];
  564. if(!vdi || vdi->vpu_fd==-1 || vdi->vpu_fd == 0x00)
  565. return -1;
  566. vdb.size = vb->size;
  567. vmem_lock(coreIdx);
  568. vdb.phys_addr = (PhysicalAddress)vmem_alloc(&vdi->pvip->vmem, vdb.size, 0);
  569. vmem_unlock(coreIdx);
  570. if ((PhysicalAddress)vdb.phys_addr == (PhysicalAddress)-1)
  571. return -1; // not enough memory
  572. offset = (unsigned long)(vdb.phys_addr - vdi->vdb_video_memory.phys_addr);
  573. vdb.base = (unsigned long )vdi->vdb_video_memory.base + offset;
  574. vdb.virt_addr = vdb.phys_addr;
  575. vb->phys_addr = (unsigned long)vdb.phys_addr;
  576. vb->base = (unsigned long)vdb.base;
  577. vb->virt_addr = (unsigned long)vb->phys_addr;
  578. for (i=0; i<MAX_VPU_BUFFER_POOL; i++)
  579. {
  580. if (vdi->vpu_buffer_pool[i].inuse == 0)
  581. {
  582. vdi->vpu_buffer_pool[i].vdb = vdb;
  583. vdi->vpu_buffer_pool_count++;
  584. vdi->vpu_buffer_pool[i].inuse = 1;
  585. break;
  586. }
  587. }
  588. return 0;
  589. }
  590. int vdi_attach_dma_memory(unsigned long coreIdx, vpu_buffer_t *vb)
  591. {
  592. vdi_info_t *vdi;
  593. int i;
  594. unsigned long offset;
  595. vpudrv_buffer_t vdb = {0};
  596. #ifdef SUPPORT_MULTI_CORE_IN_ONE_DRIVER
  597. coreIdx = 0;
  598. #endif
  599. if (coreIdx >= MAX_NUM_VPU_CORE)
  600. return -1;
  601. vdi = &s_vdi_info[coreIdx];
  602. if(!vb || !vdi || vdi->vpu_fd==-1 || vdi->vpu_fd == 0x00)
  603. return -1;
  604. vdb.size = vb->size;
  605. vdb.phys_addr = vb->phys_addr;
  606. offset = (unsigned long)(vdb.phys_addr - vdi->vdb_video_memory.phys_addr);
  607. vdb.base = (unsigned long )vdi->vdb_video_memory.base + offset;
  608. vdb.virt_addr = vb->virt_addr;
  609. for (i=0; i<MAX_VPU_BUFFER_POOL; i++)
  610. {
  611. if (vdi->vpu_buffer_pool[i].vdb.phys_addr == vb->phys_addr)
  612. {
  613. vdi->vpu_buffer_pool[i].vdb = vdb;
  614. vdi->vpu_buffer_pool[i].inuse = 1;
  615. break;
  616. }
  617. else
  618. {
  619. if (vdi->vpu_buffer_pool[i].inuse == 0)
  620. {
  621. vdi->vpu_buffer_pool[i].vdb = vdb;
  622. vdi->vpu_buffer_pool_count++;
  623. vdi->vpu_buffer_pool[i].inuse = 1;
  624. break;
  625. }
  626. }
  627. }
  628. return 0;
  629. }
  630. int vdi_dettach_dma_memory(unsigned long coreIdx, vpu_buffer_t *vb)
  631. {
  632. vdi_info_t *vdi;
  633. int i;
  634. #ifdef SUPPORT_MULTI_CORE_IN_ONE_DRIVER
  635. coreIdx = 0;
  636. #endif
  637. if (coreIdx >= MAX_NUM_VPU_CORE)
  638. return -1;
  639. vdi = &s_vdi_info[coreIdx];
  640. if(!vb || !vdi || vdi->vpu_fd==-1 || vdi->vpu_fd == 0x00)
  641. return -1;
  642. if (vb->size == 0)
  643. return -1;
  644. for (i=0; i<MAX_VPU_BUFFER_POOL; i++)
  645. {
  646. if (vdi->vpu_buffer_pool[i].vdb.phys_addr == vb->phys_addr)
  647. {
  648. vdi->vpu_buffer_pool[i].inuse = 0;
  649. vdi->vpu_buffer_pool_count--;
  650. break;
  651. }
  652. }
  653. return 0;
  654. }
  655. void vdi_free_dma_memory(unsigned long coreIdx, vpu_buffer_t *vb, int memTypes, int instIndex)
  656. {
  657. vdi_info_t *vdi;
  658. int i;
  659. vpudrv_buffer_t vdb = {0};
  660. #ifdef SUPPORT_MULTI_CORE_IN_ONE_DRIVER
  661. coreIdx = 0;
  662. #endif
  663. if (coreIdx >= MAX_NUM_VPU_CORE)
  664. return;
  665. vdi = &s_vdi_info[coreIdx];
  666. if(!vb || !vdi || vdi->vpu_fd==-1 || vdi->vpu_fd == 0x00)
  667. return;
  668. if (vb->size == 0)
  669. return;
  670. for (i=0; i<MAX_VPU_BUFFER_POOL; i++)
  671. {
  672. if (vdi->vpu_buffer_pool[i].vdb.phys_addr == vb->phys_addr)
  673. {
  674. vdi->vpu_buffer_pool[i].inuse = 0;
  675. vdi->vpu_buffer_pool_count--;
  676. vdb = vdi->vpu_buffer_pool[i].vdb;
  677. break;
  678. }
  679. }
  680. if (!vdb.size) //lint !e644
  681. {
  682. VLOG(ERR, "[VDI] invalid buffer to free address = 0x%x\n", (int)vdb.virt_addr);
  683. return ;
  684. }
  685. vmem_lock(coreIdx);
  686. vmem_free(&vdi->pvip->vmem, (unsigned long)vdb.phys_addr, 0);
  687. vmem_unlock(coreIdx);
  688. osal_memset(vb, 0, sizeof(vpu_buffer_t));
  689. }
  690. int vdi_get_sram_memory(unsigned long coreIdx, vpu_buffer_t *vb)
  691. {
  692. vdi_info_t *vdi = &s_vdi_info[coreIdx];
  693. Uint32 sram_size=0;
  694. if (coreIdx >= MAX_NUM_VPU_CORE)
  695. return -1;
  696. if(!vb || !vdi)
  697. return -1;
  698. switch (vdi->product_code) {
  699. case BODA950_CODE:
  700. case CODA960_CODE:
  701. case CODA980_CODE:
  702. sram_size = VDI_CODA9_SRAM_SIZE; break;
  703. case WAVE511_CODE:
  704. sram_size = VDI_WAVE511_SRAM_SIZE; break;
  705. case WAVE521_CODE:
  706. sram_size = VDI_WAVE521_SRAM_SIZE; break;
  707. case WAVE521C_CODE:
  708. sram_size = VDI_WAVE521C_SRAM_SIZE; break;
  709. case WAVE521C_DUAL_CODE:
  710. sram_size = VDI_WAVE521C_SRAM_SIZE; break;
  711. case WAVE517_CODE:
  712. sram_size = VDI_WAVE521C_SRAM_SIZE; break;
  713. default:
  714. VLOG(ERR, "[VDI] check product_code(%x)\n", vdi->product_code);
  715. break;
  716. }
  717. // if we can know the sram address directly in vdi layer, we use it first for sdram address
  718. vb->phys_addr = VDI_SRAM_BASE_ADDR+(coreIdx*sram_size);
  719. vb->size = sram_size;
  720. return 0;
  721. }
  722. int vdi_set_clock_gate(unsigned long coreIdx, int enable)
  723. {
  724. vdi_info_t *vdi = NULL;
  725. if (coreIdx >= MAX_NUM_VPU_CORE)
  726. return -1;
  727. vdi = &s_vdi_info[coreIdx];
  728. if(!vdi || vdi->vpu_fd==-1 || vdi->vpu_fd == 0x00)
  729. return -1;
  730. if (vdi->product_code == WAVE512_CODE || vdi->product_code == WAVE515_CODE || vdi->product_code == WAVE517_CODE ||
  731. vdi->product_code == WAVE521_CODE || vdi->product_code == WAVE521C_CODE || vdi->product_code == WAVE511_CODE || vdi->product_code == WAVE521C_DUAL_CODE ) {
  732. return 0;
  733. }
  734. vdi->clock_state = enable;
  735. return 0;
  736. }
  737. int vdi_get_clock_gate(unsigned long coreIdx)
  738. {
  739. vdi_info_t *vdi = NULL;
  740. if (coreIdx >= MAX_NUM_VPU_CORE)
  741. return -1;
  742. vdi = &s_vdi_info[coreIdx];
  743. if(!vdi || vdi->vpu_fd==-1 || vdi->vpu_fd == 0x00)
  744. return -1;
  745. return vdi->clock_state;
  746. }
  747. int vdi_wait_bus_busy(unsigned long coreIdx, int timeout, unsigned int gdi_busy_flag)
  748. {
  749. vdi_info_t *vdi = &s_vdi_info[coreIdx];
  750. if(!vdi || vdi->vpu_fd==-1 || vdi->vpu_fd == 0x00)
  751. return -1;
  752. //VDI must implement timeout action in this function for multi-vpu core scheduling efficiency.
  753. //the setting small value as timeout gives a chance to wait the other vpu core.
  754. while(1)
  755. {
  756. if (vdi->product_code == WAVE521_CODE || vdi->product_code == WAVE521C_CODE || vdi->product_code == WAVE511_CODE || vdi->product_code == WAVE521C_DUAL_CODE ||
  757. vdi->product_code == WAVE517_CODE) {
  758. if (vdi_fio_read_register(coreIdx, gdi_busy_flag) == 0x3f) break;
  759. }
  760. else if (PRODUCT_CODE_W_SERIES(vdi->product_code)) {
  761. if (vdi_fio_read_register(coreIdx, gdi_busy_flag) == 0x738) break;
  762. }
  763. else {
  764. if (vdi_read_register(coreIdx, gdi_busy_flag) == 0x77) break;
  765. }
  766. //Sleep(1); // 1ms sec
  767. //if (count++ > timeout)
  768. // return -1;
  769. }
  770. return 0;
  771. }
  772. int vdi_wait_vpu_busy(unsigned long coreIdx, int timeout, unsigned int addr_bit_busy_flag)
  773. {
  774. vdi_info_t *vdi = &s_vdi_info[coreIdx];
  775. int normalReg = TRUE;
  776. if(!vdi || vdi->vpu_fd==-1 || vdi->vpu_fd == 0x00)
  777. return -1;
  778. //VDI must implement timeout action in this function for multi-vpu core scheduling efficiency.
  779. //the setting small value as timeout gives a chance to wait the other vpu core.
  780. if (PRODUCT_CODE_W_SERIES(vdi->product_code)) {
  781. if (addr_bit_busy_flag&0x8000) normalReg = FALSE;
  782. }
  783. while(1)
  784. {
  785. if (normalReg == TRUE) {
  786. if (vdi_read_register(coreIdx, addr_bit_busy_flag) == 0) break;
  787. }
  788. else {
  789. if (vdi_fio_read_register(coreIdx, addr_bit_busy_flag) == 0) break;
  790. }
  791. //Sleep(1); // 1ms sec
  792. //if (count++ > timeout)
  793. // return -1;
  794. }
  795. return 0;
  796. }
  797. int vdi_wait_vcpu_bus_busy(unsigned long coreIdx, int timeout, unsigned int addr_bit_busy_flag)
  798. {
  799. vdi_info_t *vdi = &s_vdi_info[coreIdx];
  800. int normalReg = TRUE;
  801. if(!vdi || vdi->vpu_fd==-1 || vdi->vpu_fd == 0x00)
  802. return -1;
  803. //VDI must implement timeout action in this function for multi-vpu core scheduling efficiency.
  804. //the setting small value as timeout gives a chance to wait the other vpu core.
  805. if (PRODUCT_CODE_W_SERIES(vdi->product_code)) {
  806. if (addr_bit_busy_flag&0x8000) normalReg = FALSE;
  807. }
  808. while(1)
  809. {
  810. if (normalReg == TRUE) {
  811. if (vdi_read_register(coreIdx, addr_bit_busy_flag) == 0x40) break;
  812. }
  813. else {
  814. if (vdi_fio_read_register(coreIdx, addr_bit_busy_flag) == 0x40) break;
  815. }
  816. //Sleep(1); // 1ms sec
  817. //if (count++ > timeout)
  818. // return -1;
  819. }
  820. return 0;
  821. }
  822. #ifdef SUPPORT_MULTI_INST_INTR
  823. int vdi_wait_interrupt(unsigned long core_idx, unsigned int instIdx, int timeout)
  824. #else
  825. int vdi_wait_interrupt(unsigned long core_idx, int timeout)
  826. #endif
  827. {
  828. vdi_info_t *vdi = &s_vdi_info[core_idx];
  829. int intr_reason;
  830. //unsigned long cur_time;
  831. //VDI must implement timeout action in this function for multi-vpu core scheduling efficiency.
  832. //the setting small value as timeout gives a chance to wait the other vpu core.
  833. #ifdef SUPPORT_INTERRUPT
  834. #error "Need to implement"
  835. if(!vdi || vdi->vpu_fd==-1 || vdi->vpu_fd == 0x00)
  836. return -1;
  837. #else
  838. int int_sts_reg;
  839. int int_reason_reg;
  840. if(!vdi || vdi->vpu_fd==-1 || vdi->vpu_fd == 0x00)
  841. return -1;
  842. if (PRODUCT_CODE_W_SERIES(vdi->product_code)) {
  843. int_sts_reg = W5_VPU_VPU_INT_STS;
  844. }
  845. else {
  846. int_sts_reg = BIT_INT_STS;
  847. }
  848. if (PRODUCT_CODE_W_SERIES(vdi->product_code)) {
  849. int_reason_reg = W5_VPU_VINT_REASON;
  850. }
  851. else {
  852. int_reason_reg = BIT_INT_REASON;
  853. }
  854. //cur_time = jiffies;
  855. while(1)
  856. {
  857. if (vdi_read_register(core_idx, int_sts_reg))
  858. {
  859. if ((intr_reason=vdi_read_register(core_idx, int_reason_reg)))
  860. {
  861. if (PRODUCT_CODE_W_SERIES(vdi->product_code))
  862. {
  863. vdi_write_register(core_idx, W5_VPU_VINT_REASON_CLR, intr_reason);
  864. vdi_write_register(core_idx, W5_VPU_VINT_CLEAR, 0x1);
  865. }
  866. else
  867. {
  868. vdi_write_register(core_idx, BIT_INT_CLEAR, 0x1);
  869. }
  870. break;
  871. }
  872. }
  873. /*
  874. if(jiffies_to_msecs(jiffies - cur_time) > timeout) {
  875. return -1;
  876. }
  877. */
  878. }
  879. #endif
  880. return intr_reason;
  881. }
  882. int vdi_get_system_endian(unsigned long coreIdx)
  883. {
  884. vdi_info_t *vdi = &s_vdi_info[coreIdx];
  885. if(!vdi || vdi->vpu_fd == -1 || vdi->vpu_fd == 0x00)
  886. return -1;
  887. if (PRODUCT_CODE_W_SERIES(vdi->product_code))
  888. return VDI_128BIT_BUS_SYSTEM_ENDIAN;
  889. else
  890. return VDI_SYSTEM_ENDIAN;
  891. }
  892. int vdi_convert_endian(unsigned long coreIdx, unsigned int endian)
  893. {
  894. Uint32 productCode;
  895. productCode = vdi_read_register(coreIdx, VPU_PRODUCT_CODE_REGISTER);
  896. if (PRODUCT_CODE_W_SERIES(productCode)) {
  897. switch (endian) {
  898. case VDI_LITTLE_ENDIAN: endian = 0x00; break;
  899. case VDI_BIG_ENDIAN: endian = 0x0f; break;
  900. case VDI_32BIT_LITTLE_ENDIAN: endian = 0x04; break;
  901. case VDI_32BIT_BIG_ENDIAN: endian = 0x03; break;
  902. }
  903. }
  904. return (endian&0x0f);
  905. }
  906. static Uint32 convert_endian_coda9_to_wave4(Uint32 endian)
  907. {
  908. Uint32 converted_endian = endian;
  909. switch(endian) {
  910. case VDI_LITTLE_ENDIAN: converted_endian = 0; break;
  911. case VDI_BIG_ENDIAN: converted_endian = 7; break;
  912. case VDI_32BIT_LITTLE_ENDIAN: converted_endian = 4; break;
  913. case VDI_32BIT_BIG_ENDIAN: converted_endian = 3; break;
  914. }
  915. return converted_endian;
  916. }
  917. int swap_endian(unsigned long coreIdx, unsigned char *data, int len, int endian)
  918. {
  919. vdi_info_t* vdi = &s_vdi_info[coreIdx];
  920. int changes;
  921. int sys_endian;
  922. BOOL byteChange, wordChange, dwordChange, lwordChange;
  923. if (PRODUCT_CODE_W_SERIES(vdi->product_code)) {
  924. sys_endian = VDI_128BIT_BUS_SYSTEM_ENDIAN;
  925. }
  926. else if(PRODUCT_CODE_NOT_W_SERIES(vdi->product_code)) {
  927. sys_endian = VDI_SYSTEM_ENDIAN;
  928. }
  929. else {
  930. VLOG(ERR, "Unknown product id : %08x\n", vdi->product_code);
  931. return -1;
  932. }
  933. endian = vdi_convert_endian(coreIdx, endian);
  934. sys_endian = vdi_convert_endian(coreIdx, sys_endian);
  935. if (endian == sys_endian)
  936. return 0;
  937. if (PRODUCT_CODE_W_SERIES(vdi->product_code)) {
  938. }
  939. else if (PRODUCT_CODE_NOT_W_SERIES(vdi->product_code)) {
  940. endian = convert_endian_coda9_to_wave4(endian);
  941. sys_endian = convert_endian_coda9_to_wave4(sys_endian);
  942. }
  943. else {
  944. VLOG(ERR, "Unknown product id : %08x\n", vdi->product_code);
  945. return -1;
  946. }
  947. changes = endian ^ sys_endian;
  948. byteChange = changes&0x01;
  949. wordChange = ((changes&0x02) == 0x02);
  950. dwordChange = ((changes&0x04) == 0x04);
  951. lwordChange = ((changes&0x08) == 0x08);
  952. if (byteChange) byte_swap(data, len);
  953. if (wordChange) word_swap(data, len);
  954. if (dwordChange) dword_swap(data, len);
  955. if (lwordChange) lword_swap(data, len);
  956. return 1;
  957. }