vdec.c 78 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (c) 2022, Chips&Media
  4. * All rights reserved.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. *
  9. * 1. Redistributions of source code must retain the above copyright notice, this
  10. * list of conditions and the following disclaimer.
  11. * 2. Redistributions in binary form must reproduce the above copyright notice,
  12. * this list of conditions and the following disclaimer in the documentation
  13. * and/or other materials provided with the distribution.
  14. *
  15. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  16. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  17. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
  19. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  21. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  22. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  23. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  24. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25. *
  26. * Copyright (C) 2022 StarFive Technology Co., Ltd.
  27. */
  28. #include <linux/kernel.h>
  29. #include <linux/mm.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/ioport.h>
  32. #include <linux/module.h>
  33. #include <linux/mutex.h>
  34. #include <linux/platform_device.h>
  35. #include <linux/dma-mapping.h>
  36. #include <linux/of.h>
  37. #include <linux/pm_runtime.h>
  38. #include <linux/wait.h>
  39. #include <linux/list.h>
  40. #include <linux/clk.h>
  41. #include <linux/delay.h>
  42. #include <linux/uaccess.h>
  43. #include <linux/cdev.h>
  44. #include <linux/slab.h>
  45. #include <linux/of_address.h>
  46. #include <linux/sched.h>
  47. #include <linux/sched/signal.h>
  48. #include <linux/version.h>
  49. #include <linux/kfifo.h>
  50. #include <linux/kthread.h>
  51. #include <linux/reset.h>
  52. #include <asm/io.h>
  53. #include <soc/sifive/sifive_l2_cache.h>
  54. #include "../../../vpuapi/vpuconfig.h"
  55. #include "vpu.h"
  56. //#define ENABLE_DEBUG_MSG
  57. #ifdef ENABLE_DEBUG_MSG
  58. #define DPRINTK(args...) printk(KERN_INFO args);
  59. #else
  60. #define DPRINTK(args...)
  61. #endif
  62. /* definitions to be changed as customer configuration */
  63. /* if you want to have clock gating scheme frame by frame */
  64. /* #define VPU_SUPPORT_CLOCK_CONTROL */
  65. /* if the driver want to use interrupt service from kernel ISR */
  66. #define VPU_SUPPORT_ISR
  67. #ifdef VPU_SUPPORT_ISR
  68. /* if the driver want to disable and enable IRQ whenever interrupt asserted. */
  69. //#define VPU_IRQ_CONTROL
  70. #endif
  71. //#define CONFIG_USE_PLL_DYNAMIC_FREQ
  72. #define VPU_SUPPORT_CLOCK_CONTROL
  73. /* if clktree is work,try this...*/
  74. #define STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  75. /* if the platform driver knows the name of this driver */
  76. /* VPU_PLATFORM_DEVICE_NAME */
  77. #define VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  78. /* if this driver knows the dedicated video memory address */
  79. //#define VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  80. static void starfive_flush_dcache(unsigned long start, unsigned long len)
  81. {
  82. sifive_l2_flush64_range(start, len);
  83. }
  84. #define VPU_PLATFORM_DEVICE_NAME "vdec"
  85. #define VPU_CLK_NAME "vcodec"
  86. #define VPU_DEV_NAME "vdec"
  87. /* if the platform driver knows this driver */
  88. /* the definition of VPU_REG_BASE_ADDR and VPU_REG_SIZE are not meaningful */
  89. #define VPU_REG_BASE_ADDR 0x118F0000
  90. #define VPU_REG_SIZE (0x4000*MAX_NUM_VPU_CORE)
  91. #ifdef VPU_SUPPORT_ISR
  92. #define VPU_IRQ_NUM (23)
  93. #endif
  94. /* this definition is only for chipsnmedia FPGA board env */
  95. /* so for SOC env of customers can be ignored */
  96. #ifndef VM_RESERVED /*for kernel up to 3.7.0 version*/
  97. #define VM_RESERVED (VM_DONTEXPAND | VM_DONTDUMP)
  98. #endif
  99. struct device *vpu_dev;
  100. typedef struct vpu_drv_context_t {
  101. struct fasync_struct *async_queue;
  102. #ifdef SUPPORT_MULTI_INST_INTR
  103. unsigned long interrupt_reason[MAX_NUM_INSTANCE];
  104. #else
  105. unsigned long interrupt_reason;
  106. #endif
  107. u32 open_count; /*!<< device reference count. Not instance count */
  108. } vpu_drv_context_t;
  109. /* To track the allocated memory buffer */
  110. typedef struct vpudrv_buffer_pool_t {
  111. struct list_head list;
  112. struct vpudrv_buffer_t vb;
  113. struct file *filp;
  114. } vpudrv_buffer_pool_t;
  115. /* To track the instance index and buffer in instance pool */
  116. typedef struct vpudrv_instanace_list_t {
  117. struct list_head list;
  118. unsigned long inst_idx;
  119. unsigned long core_idx;
  120. struct file *filp;
  121. } vpudrv_instanace_list_t;
  122. typedef struct vpudrv_instance_pool_t {
  123. unsigned char codecInstPool[MAX_NUM_INSTANCE][MAX_INST_HANDLE_SIZE];
  124. } vpudrv_instance_pool_t;
  125. #ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  126. typedef struct vpu_clkgen_t {
  127. void __iomem *en_ctrl;
  128. uint32_t rst_mask;
  129. } vpu_clkgen_t;
  130. #endif
  131. struct clk_bulk_data vpu_clks[] = {
  132. { .id = "apb_clk" },
  133. { .id = "axi_clk" },
  134. { .id = "bpu_clk" },
  135. { .id = "vce_clk" },
  136. { .id = "noc_bus" },
  137. };
  138. typedef struct vpu_clk_t {
  139. #ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  140. void __iomem *clkgen;
  141. void __iomem *rst_ctrl;
  142. void __iomem *rst_status;
  143. void __iomem *noc_bus;
  144. uint32_t en_shift;
  145. uint32_t en_mask;
  146. vpu_clkgen_t apb_clk;
  147. vpu_clkgen_t axi_clk;
  148. vpu_clkgen_t bpu_clk;
  149. vpu_clkgen_t vce_clk;
  150. vpu_clkgen_t aximem_128b;
  151. #else
  152. struct clk_bulk_data *clks;
  153. struct reset_control *resets;
  154. int nr_clks;
  155. #endif
  156. struct device *dev;
  157. bool noc_ctrl;
  158. } vpu_clk_t;
  159. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  160. #include "vmm.h"
  161. static video_mm_t s_vmem;
  162. static vpudrv_buffer_t s_video_memory = {0};
  163. #endif /*VPU_SUPPORT_RESERVED_VIDEO_MEMORY*/
  164. static int vpu_hw_reset(void);
  165. static void vpu_clk_disable(vpu_clk_t *clk);
  166. static int vpu_clk_enable(vpu_clk_t *clk);
  167. static vpu_clk_t *vpu_clk_get(struct platform_device *pdev);
  168. static void vpu_clk_put(vpu_clk_t *clk);
  169. static int vpu_pmu_enable(struct device *dev);
  170. static void vpu_pmu_disable(struct device *dev);
  171. /* end customer definition */
  172. static vpudrv_buffer_t s_instance_pool = {0};
  173. static vpudrv_buffer_t s_common_memory = {0};
  174. static vpu_drv_context_t s_vpu_drv_context;
  175. static dev_t s_vpu_devt;
  176. static int s_vpu_major;
  177. static struct cdev s_vpu_cdev;
  178. static struct class *s_vpu_class;
  179. static vpu_clk_t *s_vpu_clk;
  180. static int s_vpu_open_ref_count;
  181. #ifdef VPU_SUPPORT_ISR
  182. static int s_vpu_irq = VPU_IRQ_NUM;
  183. #endif
  184. static vpudrv_buffer_t s_vpu_register = {0};
  185. #ifdef SUPPORT_MULTI_INST_INTR
  186. static int s_interrupt_flag[MAX_NUM_INSTANCE];
  187. static wait_queue_head_t s_interrupt_wait_q[MAX_NUM_INSTANCE];
  188. typedef struct kfifo kfifo_t;
  189. static kfifo_t s_interrupt_pending_q[MAX_NUM_INSTANCE];
  190. static spinlock_t s_kfifo_lock = __SPIN_LOCK_UNLOCKED(s_kfifo_lock);
  191. #else
  192. static int s_interrupt_flag;
  193. static wait_queue_head_t s_interrupt_wait_q;
  194. #endif
  195. static spinlock_t s_vpu_lock = __SPIN_LOCK_UNLOCKED(s_vpu_lock);
  196. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
  197. static DECLARE_MUTEX(s_vpu_sem);
  198. #else
  199. static DEFINE_SEMAPHORE(s_vpu_sem);
  200. #endif
  201. static struct list_head s_vbp_head = LIST_HEAD_INIT(s_vbp_head);
  202. static struct list_head s_inst_list_head = LIST_HEAD_INIT(s_inst_list_head);
  203. static vpu_bit_firmware_info_t s_bit_firmware_info[MAX_NUM_VPU_CORE];
  204. //#ifdef CONFIG_PM
  205. /* implement to power management functions */
  206. #define BIT_BASE 0x0000
  207. #define BIT_CODE_RUN (BIT_BASE + 0x000)
  208. #define BIT_CODE_DOWN (BIT_BASE + 0x004)
  209. #define BIT_INT_CLEAR (BIT_BASE + 0x00C)
  210. #define BIT_INT_STS (BIT_BASE + 0x010)
  211. #define BIT_CODE_RESET (BIT_BASE + 0x014)
  212. #define BIT_INT_REASON (BIT_BASE + 0x174)
  213. #define BIT_BUSY_FLAG (BIT_BASE + 0x160)
  214. #define BIT_RUN_COMMAND (BIT_BASE + 0x164)
  215. #define BIT_RUN_INDEX (BIT_BASE + 0x168)
  216. #define BIT_RUN_COD_STD (BIT_BASE + 0x16C)
  217. /* WAVE5 registers */
  218. #define W5_REG_BASE 0x0000
  219. #define W5_VPU_BUSY_STATUS (W5_REG_BASE + 0x0070)
  220. #define W5_VPU_INT_REASON_CLEAR (W5_REG_BASE + 0x0034)
  221. #define W5_VPU_VINT_CLEAR (W5_REG_BASE + 0x003C)
  222. #define W5_VPU_VPU_INT_STS (W5_REG_BASE + 0x0044)
  223. #define W5_VPU_INT_REASON (W5_REG_BASE + 0x004c)
  224. #define W5_RET_FAIL_REASON (W5_REG_BASE + 0x010C)
  225. #ifdef SUPPORT_MULTI_INST_INTR
  226. #define W5_RET_BS_EMPTY_INST (W5_REG_BASE + 0x01E4)
  227. #define W5_RET_QUEUE_CMD_DONE_INST (W5_REG_BASE + 0x01E8)
  228. #define W5_RET_SEQ_DONE_INSTANCE_INFO (W5_REG_BASE + 0x01FC)
  229. typedef enum {
  230. INT_WAVE5_INIT_VPU = 0,
  231. INT_WAVE5_WAKEUP_VPU = 1,
  232. INT_WAVE5_SLEEP_VPU = 2,
  233. INT_WAVE5_CREATE_INSTANCE = 3,
  234. INT_WAVE5_FLUSH_INSTANCE = 4,
  235. INT_WAVE5_DESTORY_INSTANCE = 5,
  236. INT_WAVE5_INIT_SEQ = 6,
  237. INT_WAVE5_SET_FRAMEBUF = 7,
  238. INT_WAVE5_DEC_PIC = 8,
  239. INT_WAVE5_ENC_PIC = 8,
  240. INT_WAVE5_ENC_SET_PARAM = 9,
  241. #ifdef SUPPORT_SOURCE_RELEASE_INTERRUPT
  242. INT_WAVE5_ENC_SRC_RELEASE = 10,
  243. #endif
  244. INT_WAVE5_ENC_LOW_LATENCY = 13,
  245. INT_WAVE5_DEC_QUERY = 14,
  246. INT_WAVE5_BSBUF_EMPTY = 15,
  247. INT_WAVE5_BSBUF_FULL = 15,
  248. } Wave5InterruptBit;
  249. #endif
  250. /* WAVE5 INIT, WAKEUP */
  251. #define W5_PO_CONF (W5_REG_BASE + 0x0000)
  252. #define W5_VPU_VINT_ENABLE (W5_REG_BASE + 0x0048)
  253. #define W5_VPU_RESET_REQ (W5_REG_BASE + 0x0050)
  254. #define W5_VPU_RESET_STATUS (W5_REG_BASE + 0x0054)
  255. #define W5_VPU_REMAP_CTRL (W5_REG_BASE + 0x0060)
  256. #define W5_VPU_REMAP_VADDR (W5_REG_BASE + 0x0064)
  257. #define W5_VPU_REMAP_PADDR (W5_REG_BASE + 0x0068)
  258. #define W5_VPU_REMAP_CORE_START (W5_REG_BASE + 0x006C)
  259. #define W5_REMAP_CODE_INDEX 0
  260. /* WAVE5 registers */
  261. #define W5_ADDR_CODE_BASE (W5_REG_BASE + 0x0110)
  262. #define W5_CODE_SIZE (W5_REG_BASE + 0x0114)
  263. #define W5_CODE_PARAM (W5_REG_BASE + 0x0118)
  264. #define W5_INIT_VPU_TIME_OUT_CNT (W5_REG_BASE + 0x0130)
  265. #define W5_HW_OPTION (W5_REG_BASE + 0x012C)
  266. #define W5_RET_SUCCESS (W5_REG_BASE + 0x0108)
  267. #define W5_COMMAND (W5_REG_BASE + 0x0100)
  268. #define W5_VPU_HOST_INT_REQ (W5_REG_BASE + 0x0038)
  269. /* Product register */
  270. #define VPU_PRODUCT_CODE_REGISTER (BIT_BASE + 0x1044)
  271. #if defined(VPU_SUPPORT_PLATFORM_DRIVER_REGISTER) && defined(CONFIG_PM)
  272. static u32 s_vpu_reg_store[MAX_NUM_VPU_CORE][64];
  273. #endif
  274. //#endif //CONFIG_PM
  275. #define ReadVpuRegister(addr) *(volatile unsigned int *)(s_vpu_register.virt_addr + s_bit_firmware_info[core].reg_base_offset + addr)
  276. #define WriteVpuRegister(addr, val) *(volatile unsigned int *)(s_vpu_register.virt_addr + s_bit_firmware_info[core].reg_base_offset + addr) = (unsigned int)val
  277. #define WriteVpu(addr, val) *(volatile unsigned int *)(addr) = (unsigned int)val;
  278. #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_USE_PLL_DYNAMIC_FREQ)
  279. #include <linux/fs.h>
  280. #include <linux/file.h>
  281. struct freq_ctrl {
  282. struct device *dev;
  283. struct file *governor;
  284. struct file *maxfreq;
  285. struct file *parameters_off;
  286. const char *scaling_governor;
  287. const char *scaling_maxfreq;
  288. const char *scaling_parameters_off;
  289. const char *fixed_freq;
  290. char re_cpu_gov[16];
  291. char re_max_freq[16];
  292. struct mutex mutex_lock;
  293. int count;
  294. };
  295. static struct freq_ctrl *vpu_freq_ctrl;
  296. static int vpu_freq_open(struct freq_ctrl *vpu_freq_ctrl)
  297. {
  298. vpu_freq_ctrl->governor = filp_open(
  299. vpu_freq_ctrl->scaling_governor, O_RDWR, 0);
  300. if (IS_ERR(vpu_freq_ctrl->governor))
  301. goto out;
  302. vpu_freq_ctrl->maxfreq = filp_open(
  303. vpu_freq_ctrl->scaling_maxfreq, O_RDWR, 0);
  304. if (IS_ERR(vpu_freq_ctrl->maxfreq))
  305. goto out;
  306. vpu_freq_ctrl->parameters_off = filp_open(
  307. vpu_freq_ctrl->scaling_parameters_off, O_RDWR, 0);
  308. if (IS_ERR(vpu_freq_ctrl->parameters_off))
  309. goto out;
  310. return 0;
  311. out:
  312. dev_err(vpu_freq_ctrl->dev, "failed open scaling_governor.\n");
  313. return -ENXIO;
  314. }
  315. static int vpu_freq_close(void)
  316. {
  317. if (!vpu_freq_ctrl)
  318. return -ENODEV;
  319. mutex_destroy(&vpu_freq_ctrl->mutex_lock);
  320. if (vpu_freq_ctrl->governor && vpu_freq_ctrl->maxfreq
  321. && vpu_freq_ctrl->parameters_off) {
  322. fput(vpu_freq_ctrl->governor);
  323. fput(vpu_freq_ctrl->maxfreq);
  324. fput(vpu_freq_ctrl->parameters_off);
  325. vpu_freq_ctrl->governor = NULL;
  326. vpu_freq_ctrl->maxfreq = NULL;
  327. vpu_freq_ctrl->parameters_off = NULL;
  328. }
  329. return 0;
  330. }
  331. static int vpu_freq_save_env(void)
  332. {
  333. const char *fixed_freq = vpu_freq_ctrl->fixed_freq;
  334. const char *governor_mode = "performance";
  335. size_t rv;
  336. if (!vpu_freq_ctrl)
  337. return -ENODEV;
  338. mutex_lock(&vpu_freq_ctrl->mutex_lock);
  339. if (vpu_freq_ctrl->count == 0) {
  340. /*save env*/
  341. kernel_read(vpu_freq_ctrl->governor, vpu_freq_ctrl->re_cpu_gov,
  342. sizeof(vpu_freq_ctrl->re_cpu_gov), NULL);
  343. kernel_read(vpu_freq_ctrl->maxfreq, vpu_freq_ctrl->re_max_freq,
  344. sizeof(vpu_freq_ctrl->re_max_freq), NULL);
  345. /*setenv*/
  346. rv = kernel_write(vpu_freq_ctrl->maxfreq, fixed_freq,
  347. strlen(fixed_freq), NULL);
  348. rv = kernel_write(vpu_freq_ctrl->governor, governor_mode,
  349. strlen(governor_mode), NULL);
  350. rv = kernel_write(vpu_freq_ctrl->parameters_off, "1", 1, NULL);
  351. }
  352. vpu_freq_ctrl->count++;
  353. mutex_unlock(&vpu_freq_ctrl->mutex_lock);
  354. return 0;
  355. }
  356. static int vpu_freq_put_env(void)
  357. {
  358. size_t rv;
  359. if (!vpu_freq_ctrl)
  360. return -ENODEV;
  361. mutex_lock(&vpu_freq_ctrl->mutex_lock);
  362. vpu_freq_ctrl->count--;
  363. if (vpu_freq_ctrl->count == 0) {
  364. rv = kernel_write(vpu_freq_ctrl->governor, vpu_freq_ctrl->re_cpu_gov,
  365. strlen(vpu_freq_ctrl->re_cpu_gov), NULL);
  366. rv = kernel_write(vpu_freq_ctrl->maxfreq, vpu_freq_ctrl->re_max_freq,
  367. strlen(vpu_freq_ctrl->re_max_freq), NULL);
  368. rv = kernel_write(vpu_freq_ctrl->parameters_off, "0", 1, NULL);
  369. }
  370. mutex_unlock(&vpu_freq_ctrl->mutex_lock);
  371. return 0;
  372. }
  373. static int vpu_freq_init(struct device *dev)
  374. {
  375. int ret;
  376. const char *of_str;
  377. vpu_freq_ctrl = devm_kzalloc(dev, sizeof(*vpu_freq_ctrl), GFP_KERNEL);
  378. if (!vpu_freq_ctrl)
  379. return -ENOMEM;
  380. vpu_freq_ctrl->scaling_governor = "/sys/devices/system/cpu/cpufreq/policy0/scaling_governor";
  381. vpu_freq_ctrl->scaling_maxfreq = "/sys/devices/system/cpu/cpufreq/policy0/scaling_max_freq";
  382. vpu_freq_ctrl->scaling_parameters_off = "/sys/module/cpufreq/parameters/off";
  383. vpu_freq_ctrl->dev = dev;
  384. ret = vpu_freq_open(vpu_freq_ctrl);
  385. if (ret) {
  386. devm_kfree(dev, vpu_freq_ctrl);
  387. vpu_freq_ctrl = NULL;
  388. return ret;
  389. }
  390. if (!device_property_read_string(dev, "vdec,runtime-cpufreq", &of_str))
  391. vpu_freq_ctrl->fixed_freq = of_str;
  392. else
  393. vpu_freq_ctrl->fixed_freq = "1250000";
  394. vpu_freq_ctrl->count = 0;
  395. mutex_init(&vpu_freq_ctrl->mutex_lock);
  396. dev_dbg(dev, "fixed_freq:%s\n", vpu_freq_ctrl->fixed_freq);
  397. return 0;
  398. }
  399. #endif
  400. static int vpu_alloc_dma_buffer(vpudrv_buffer_t *vb)
  401. {
  402. if (!vb)
  403. return -1;
  404. DPRINTK("[VPUDRV] vpu_alloc_dma_buffer \n");
  405. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  406. vb->phys_addr = (unsigned long)vmem_alloc(&s_vmem, vb->size, 0);
  407. if ((unsigned long)vb->phys_addr == (unsigned long)-1) {
  408. printk(KERN_ERR "[VPUDRV] Physical memory allocation error size=%d\n", vb->size);
  409. return -1;
  410. }
  411. vb->base = (unsigned long)(s_video_memory.base + (vb->phys_addr - s_video_memory.phys_addr));
  412. #else
  413. vb->base = (unsigned long)dma_alloc_coherent(vpu_dev, PAGE_ALIGN(vb->size), (dma_addr_t *) (&vb->phys_addr), GFP_DMA | GFP_KERNEL);
  414. if ((void *)(vb->base) == NULL) {
  415. printk(KERN_ERR "[VPUDRV] Physical memory allocation error size=%d\n", vb->size);
  416. return -1;
  417. }
  418. starfive_flush_dcache(vb->phys_addr,PAGE_ALIGN(vb->size));
  419. #endif
  420. return 0;
  421. }
  422. static void vpu_free_dma_buffer(vpudrv_buffer_t *vb)
  423. {
  424. if (!vb)
  425. return;
  426. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  427. if (vb->base)
  428. vmem_free(&s_vmem, vb->phys_addr, 0);
  429. #else
  430. if (vb->base)
  431. dma_free_coherent(vpu_dev, PAGE_ALIGN(vb->size), (void *)vb->base, vb->phys_addr);
  432. #endif
  433. }
  434. static int vpu_free_instances(struct file *filp)
  435. {
  436. vpudrv_instanace_list_t *vil, *n;
  437. vpudrv_instance_pool_t *vip;
  438. void *vip_base;
  439. int instance_pool_size_per_core;
  440. #if !defined(PTHREAD_MUTEX_ROBUST_NP)
  441. void *vdi_mutexes_base;
  442. const int PTHREAD_MUTEX_T_DESTROY_VALUE = 0xdead10cc;
  443. #endif
  444. DPRINTK("[VPUDRV] vpu_free_instances\n");
  445. instance_pool_size_per_core = (s_instance_pool.size/MAX_NUM_VPU_CORE); /* s_instance_pool.size assigned to the size of all core once call VDI_IOCTL_GET_INSTANCE_POOL by user. */
  446. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  447. {
  448. if (vil->filp == filp) {
  449. vip_base = (void *)(s_instance_pool.base + (instance_pool_size_per_core*vil->core_idx));
  450. DPRINTK("[VPUDRV] vpu_free_instances detect instance crash instIdx=%d, coreIdx=%d, vip_base=%p, instance_pool_size_per_core=%d\n", (int)vil->inst_idx, (int)vil->core_idx, vip_base, (int)instance_pool_size_per_core);
  451. vip = (vpudrv_instance_pool_t *)vip_base;
  452. if (vip) {
  453. memset(&vip->codecInstPool[vil->inst_idx], 0x00, 4); /* only first 4 byte is key point(inUse of CodecInst in vpuapi) to free the corresponding instance. */
  454. #if !defined(PTHREAD_MUTEX_ROBUST_NP)
  455. #define PTHREAD_MUTEX_T_HANDLE_SIZE 4
  456. vdi_mutexes_base = (vip_base + (instance_pool_size_per_core - PTHREAD_MUTEX_T_HANDLE_SIZE*4));
  457. DPRINTK("[VPUDRV] vpu_free_instances : force to destroy vdi_mutexes_base=%p in userspace \n", vdi_mutexes_base);
  458. if (vdi_mutexes_base) {
  459. int i;
  460. for (i = 0; i < 4; i++) {
  461. memcpy(vdi_mutexes_base, &PTHREAD_MUTEX_T_DESTROY_VALUE, PTHREAD_MUTEX_T_HANDLE_SIZE);
  462. vdi_mutexes_base += PTHREAD_MUTEX_T_HANDLE_SIZE;
  463. }
  464. }
  465. #endif
  466. }
  467. s_vpu_open_ref_count--;
  468. list_del(&vil->list);
  469. kfree(vil);
  470. }
  471. }
  472. return 1;
  473. }
  474. static int vpu_free_buffers(struct file *filp)
  475. {
  476. vpudrv_buffer_pool_t *pool, *n;
  477. vpudrv_buffer_t vb;
  478. DPRINTK("[VPUDRV] vpu_free_buffers\n");
  479. list_for_each_entry_safe(pool, n, &s_vbp_head, list)
  480. {
  481. if (pool->filp == filp) {
  482. vb = pool->vb;
  483. if (vb.base) {
  484. vpu_free_dma_buffer(&vb);
  485. list_del(&pool->list);
  486. kfree(pool);
  487. }
  488. }
  489. }
  490. return 0;
  491. }
  492. #ifdef SUPPORT_MULTI_INST_INTR
  493. static inline u32 get_inst_idx(u32 reg_val)
  494. {
  495. u32 inst_idx;
  496. int i;
  497. for (i=0; i < MAX_NUM_INSTANCE; i++)
  498. {
  499. if(((reg_val >> i)&0x01) == 1)
  500. break;
  501. }
  502. inst_idx = i;
  503. return inst_idx;
  504. }
  505. static s32 get_vpu_inst_idx(vpu_drv_context_t *dev, u32 *reason, u32 empty_inst, u32 done_inst, u32 seq_inst)
  506. {
  507. s32 inst_idx;
  508. u32 reg_val;
  509. u32 int_reason;
  510. int_reason = *reason;
  511. DPRINTK("[VPUDRV][+]%s, int_reason=0x%x, empty_inst=0x%x, done_inst=0x%x\n", __func__, int_reason, empty_inst, done_inst);
  512. //printk(KERN_ERR "[VPUDRV][+]%s, int_reason=0x%x, empty_inst=0x%x, done_inst=0x%x\n", __func__, int_reason, empty_inst, done_inst);
  513. if (int_reason & (1 << INT_WAVE5_BSBUF_EMPTY))
  514. {
  515. reg_val = (empty_inst & 0xffff);
  516. inst_idx = get_inst_idx(reg_val);
  517. *reason = (1 << INT_WAVE5_BSBUF_EMPTY);
  518. DPRINTK("[VPUDRV] %s, W5_RET_BS_EMPTY_INST reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  519. goto GET_VPU_INST_IDX_HANDLED;
  520. }
  521. if (int_reason & (1 << INT_WAVE5_INIT_SEQ))
  522. {
  523. reg_val = (seq_inst & 0xffff);
  524. inst_idx = get_inst_idx(reg_val);
  525. *reason = (1 << INT_WAVE5_INIT_SEQ);
  526. DPRINTK("[VPUDRV] %s, RET_SEQ_DONE_INSTANCE_INFO INIT_SEQ reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  527. goto GET_VPU_INST_IDX_HANDLED;
  528. }
  529. if (int_reason & (1 << INT_WAVE5_DEC_PIC))
  530. {
  531. reg_val = (done_inst & 0xffff);
  532. inst_idx = get_inst_idx(reg_val);
  533. *reason = (1 << INT_WAVE5_DEC_PIC);
  534. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST DEC_PIC reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  535. if (int_reason & (1 << INT_WAVE5_ENC_LOW_LATENCY))
  536. {
  537. u32 ll_inst_idx;
  538. reg_val = (done_inst >> 16);
  539. ll_inst_idx = get_inst_idx(reg_val);
  540. if (ll_inst_idx == inst_idx)
  541. *reason = ((1 << INT_WAVE5_DEC_PIC) | (1 << INT_WAVE5_ENC_LOW_LATENCY));
  542. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST DEC_PIC and ENC_LOW_LATENCY reg_val=0x%x, inst_idx=%d, ll_inst_idx=%d\n", __func__, reg_val, inst_idx, ll_inst_idx);
  543. }
  544. goto GET_VPU_INST_IDX_HANDLED;
  545. }
  546. if (int_reason & (1 << INT_WAVE5_ENC_SET_PARAM))
  547. {
  548. reg_val = (seq_inst & 0xffff);
  549. inst_idx = get_inst_idx(reg_val);
  550. *reason = (1 << INT_WAVE5_ENC_SET_PARAM);
  551. DPRINTK("[VPUDRV] %s, RET_SEQ_DONE_INSTANCE_INFO ENC_SET_PARAM reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  552. goto GET_VPU_INST_IDX_HANDLED;
  553. }
  554. #ifdef SUPPORT_SOURCE_RELEASE_INTERRUPT
  555. if (int_reason & (1 << INT_WAVE5_ENC_SRC_RELEASE))
  556. {
  557. reg_val = (done_inst & 0xffff);
  558. inst_idx = get_inst_idx(reg_val);
  559. *reason = (1 << INT_WAVE5_ENC_SRC_RELEASE);
  560. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST ENC_SET_PARAM reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  561. goto GET_VPU_INST_IDX_HANDLED;
  562. }
  563. #endif
  564. if (int_reason & (1 << INT_WAVE5_ENC_LOW_LATENCY))
  565. {
  566. reg_val = (done_inst >> 16);
  567. inst_idx = get_inst_idx(reg_val);
  568. *reason = (1 << INT_WAVE5_ENC_LOW_LATENCY);
  569. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST ENC_LOW_LATENCY reg_val=0x%x, inst_idx=%d\n", __func__, reg_val, inst_idx);
  570. goto GET_VPU_INST_IDX_HANDLED;
  571. }
  572. inst_idx = -1;
  573. *reason = 0;
  574. DPRINTK("[VPUDRV] %s, UNKNOWN INTERRUPT REASON: %08x\n", __func__, int_reason);
  575. GET_VPU_INST_IDX_HANDLED:
  576. DPRINTK("[VPUDRV][-]%s, inst_idx=%d. *reason=0x%x\n", __func__, inst_idx, *reason);
  577. return inst_idx;
  578. }
  579. #endif
  580. static irqreturn_t vpu_irq_handler(int irq, void *dev_id)
  581. {
  582. vpu_drv_context_t *dev = (vpu_drv_context_t *)dev_id;
  583. /* this can be removed. it also work in VPU_WaitInterrupt of API function */
  584. int core;
  585. int product_code;
  586. #ifdef SUPPORT_MULTI_INST_INTR
  587. u32 intr_reason;
  588. s32 intr_inst_index;
  589. #endif
  590. DPRINTK("[VPUDRV][+]%s\n", __func__);
  591. #ifdef VPU_IRQ_CONTROL
  592. disable_irq_nosync(s_vpu_irq);
  593. #endif
  594. #ifdef SUPPORT_MULTI_INST_INTR
  595. intr_inst_index = 0;
  596. intr_reason = 0;
  597. #endif
  598. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  599. if (s_bit_firmware_info[core].size == 0) {/* it means that we didn't get an information the current core from API layer. No core activated.*/
  600. printk(KERN_ERR "[VPUDRV] : s_bit_firmware_info[core].size is zero\n");
  601. continue;
  602. }
  603. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  604. if (PRODUCT_CODE_W_SERIES(product_code)) {
  605. if (ReadVpuRegister(W5_VPU_VPU_INT_STS)) {
  606. #ifdef SUPPORT_MULTI_INST_INTR
  607. u32 empty_inst;
  608. u32 done_inst;
  609. u32 seq_inst;
  610. u32 i, reason, reason_clr;
  611. reason = ReadVpuRegister(W5_VPU_INT_REASON);
  612. empty_inst = ReadVpuRegister(W5_RET_BS_EMPTY_INST);
  613. done_inst = ReadVpuRegister(W5_RET_QUEUE_CMD_DONE_INST);
  614. seq_inst = ReadVpuRegister(W5_RET_SEQ_DONE_INSTANCE_INFO);
  615. reason_clr = reason;
  616. DPRINTK("[VPUDRV] vpu_irq_handler reason=0x%x, empty_inst=0x%x, done_inst=0x%x, seq_inst=0x%x \n", reason, empty_inst, done_inst, seq_inst);
  617. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  618. if (0 == empty_inst && 0 == done_inst && 0 == seq_inst) break;
  619. intr_reason = reason;
  620. intr_inst_index = get_vpu_inst_idx(dev, &intr_reason, empty_inst, done_inst, seq_inst);
  621. DPRINTK("[VPUDRV] > instance_index: %d, intr_reason: %08x empty_inst: %08x done_inst: %08x seq_inst: %08x\n", intr_inst_index, intr_reason, empty_inst, done_inst, seq_inst);
  622. if (intr_inst_index >= 0 && intr_inst_index < MAX_NUM_INSTANCE) {
  623. if (intr_reason == (1 << INT_WAVE5_BSBUF_EMPTY)) {
  624. empty_inst = empty_inst & ~(1 << intr_inst_index);
  625. WriteVpuRegister(W5_RET_BS_EMPTY_INST, empty_inst);
  626. if (0 == empty_inst) {
  627. reason &= ~(1<<INT_WAVE5_BSBUF_EMPTY);
  628. }
  629. DPRINTK("[VPUDRV] %s, W5_RET_BS_EMPTY_INST Clear empty_inst=0x%x, intr_inst_index=%d\n", __func__, empty_inst, intr_inst_index);
  630. }
  631. if (intr_reason == (1 << INT_WAVE5_DEC_PIC))
  632. {
  633. done_inst = done_inst & ~(1 << intr_inst_index);
  634. WriteVpuRegister(W5_RET_QUEUE_CMD_DONE_INST, done_inst);
  635. if (0 == done_inst) {
  636. reason &= ~(1<<INT_WAVE5_DEC_PIC);
  637. }
  638. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  639. }
  640. if ((intr_reason == (1 << INT_WAVE5_INIT_SEQ)) || (intr_reason == (1 << INT_WAVE5_ENC_SET_PARAM)))
  641. {
  642. seq_inst = seq_inst & ~(1 << intr_inst_index);
  643. WriteVpuRegister(W5_RET_SEQ_DONE_INSTANCE_INFO, seq_inst);
  644. if (0 == seq_inst) {
  645. reason &= ~(1<<INT_WAVE5_INIT_SEQ | 1<<INT_WAVE5_ENC_SET_PARAM);
  646. }
  647. DPRINTK("[VPUDRV] %s, W5_RET_SEQ_DONE_INSTANCE_INFO Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  648. }
  649. if ((intr_reason == (1 << INT_WAVE5_ENC_LOW_LATENCY)))
  650. {
  651. done_inst = (done_inst >> 16);
  652. done_inst = done_inst & ~(1 << intr_inst_index);
  653. done_inst = (done_inst << 16);
  654. WriteVpuRegister(W5_RET_QUEUE_CMD_DONE_INST, done_inst);
  655. if (0 == done_inst) {
  656. reason &= ~(1 << INT_WAVE5_ENC_LOW_LATENCY);
  657. }
  658. DPRINTK("[VPUDRV] %s, W5_RET_QUEUE_CMD_DONE_INST INT_WAVE5_ENC_LOW_LATENCY Clear done_inst=0x%x, intr_inst_index=%d\n", __func__, done_inst, intr_inst_index);
  659. }
  660. if (!kfifo_is_full(&s_interrupt_pending_q[intr_inst_index])) {
  661. if (intr_reason == ((1 << INT_WAVE5_ENC_PIC) | (1 << INT_WAVE5_ENC_LOW_LATENCY))) {
  662. u32 ll_intr_reason = (1 << INT_WAVE5_ENC_PIC);
  663. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &ll_intr_reason, sizeof(u32), &s_kfifo_lock);
  664. }
  665. else
  666. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason, sizeof(u32), &s_kfifo_lock);
  667. }
  668. else {
  669. printk(KERN_ERR "[VPUDRV] : kfifo_is_full kfifo_count=%d \n", kfifo_len(&s_interrupt_pending_q[intr_inst_index]));
  670. }
  671. }
  672. else {
  673. printk(KERN_ERR "[VPUDRV] : intr_inst_index is wrong intr_inst_index=%d \n", intr_inst_index);
  674. }
  675. }
  676. if (0 != reason)
  677. printk(KERN_ERR "INTERRUPT REASON REMAINED: %08x\n", reason);
  678. WriteVpuRegister(W5_VPU_INT_REASON_CLEAR, reason_clr);
  679. #else
  680. dev->interrupt_reason = ReadVpuRegister(W5_VPU_INT_REASON);
  681. WriteVpuRegister(W5_VPU_INT_REASON_CLEAR, dev->interrupt_reason);
  682. #endif
  683. WriteVpuRegister(W5_VPU_VINT_CLEAR, 0x1);
  684. }
  685. }
  686. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  687. if (ReadVpuRegister(BIT_INT_STS)) {
  688. #ifdef SUPPORT_MULTI_INST_INTR
  689. intr_reason = ReadVpuRegister(BIT_INT_REASON);
  690. intr_inst_index = 0; // in case of coda seriese. treats intr_inst_index is already 0
  691. kfifo_in_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason, sizeof(u32), &s_kfifo_lock);
  692. #else
  693. dev->interrupt_reason = ReadVpuRegister(BIT_INT_REASON);
  694. #endif
  695. WriteVpuRegister(BIT_INT_CLEAR, 0x1);
  696. }
  697. }
  698. else {
  699. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  700. continue;
  701. }
  702. #ifdef SUPPORT_MULTI_INST_INTR
  703. DPRINTK("[VPUDRV] product: 0x%08x intr_reason: 0x%08x\n\n", product_code, intr_reason);
  704. #else
  705. DPRINTK("[VPUDRV] product: 0x%08x intr_reason: 0x%08x\n", product_code, dev->interrupt_reason);
  706. #endif
  707. }
  708. if (dev->async_queue)
  709. kill_fasync(&dev->async_queue, SIGIO, POLL_IN); /* notify the interrupt to user space */
  710. #ifdef SUPPORT_MULTI_INST_INTR
  711. if (intr_inst_index >= 0 && intr_inst_index < MAX_NUM_INSTANCE) {
  712. s_interrupt_flag[intr_inst_index]= 1;
  713. wake_up_interruptible(&s_interrupt_wait_q[intr_inst_index]);
  714. }
  715. #else
  716. s_interrupt_flag = 1;
  717. wake_up_interruptible(&s_interrupt_wait_q);
  718. #endif
  719. DPRINTK("[VPUDRV][-]%s\n", __func__);
  720. return IRQ_HANDLED;
  721. }
  722. static int vpu_open(struct inode *inode, struct file *filp)
  723. {
  724. DPRINTK("[VPUDRV][+] %s\n", __func__);
  725. pm_runtime_get_sync(s_vpu_clk->dev);
  726. spin_lock(&s_vpu_lock);
  727. s_vpu_drv_context.open_count++;
  728. filp->private_data = (void *)(&s_vpu_drv_context);
  729. spin_unlock(&s_vpu_lock);
  730. DPRINTK("[VPUDRV][-] %s\n", __func__);
  731. return 0;
  732. }
  733. /*static int vpu_ioctl(struct inode *inode, struct file *filp, u_int cmd, u_long arg) // for kernel 2.6.9 of C&M*/
  734. static long vpu_ioctl(struct file *filp, u_int cmd, u_long arg)
  735. {
  736. int ret = 0;
  737. struct vpu_drv_context_t *dev = (struct vpu_drv_context_t *)filp->private_data;
  738. switch (cmd) {
  739. case VDI_IOCTL_GET_PHYSICAL_MEMORY:
  740. {
  741. vpudrv_buffer_pool_t *vbp = NULL;
  742. void *user_address = NULL;
  743. struct task_struct *my_struct = NULL;
  744. struct mm_struct *mm = NULL;
  745. unsigned long address = 0;
  746. pgd_t *pgd = NULL;
  747. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  748. vbp = kzalloc(sizeof(*vbp), GFP_KERNEL);
  749. if (!vbp) {
  750. up(&s_vpu_sem);
  751. return -ENOMEM;
  752. }
  753. ret = copy_from_user(&(vbp->vb), (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  754. if (ret) {
  755. kfree(vbp);
  756. up(&s_vpu_sem);
  757. return -EFAULT;
  758. }
  759. user_address = (void *)vbp->vb.virt_addr;
  760. my_struct = get_current();
  761. mm = my_struct->mm;
  762. address = (unsigned long)user_address;
  763. pgd = pgd_offset(mm, address);
  764. if (!pgd_none(*pgd) && !pgd_bad(*pgd)) {
  765. p4d_t *p4d = p4d_offset(pgd, address);
  766. pud_t *pud = pud_offset(p4d, address);
  767. if (!pud_none(*pud) && !pud_bad(*pud)) {
  768. pmd_t *pmd = pmd_offset(pud, address);
  769. if (!pmd_none(*pmd) && !pmd_bad(*pmd)) {
  770. pte_t *pte = pte_offset_map(pmd, address);
  771. if (!pte_none(*pte)) {
  772. struct page *pg = pte_page(*pte);
  773. unsigned long phys = page_to_phys(pg);
  774. unsigned long virt = (unsigned long)phys_to_virt(phys);
  775. printk("attach phy address = %lx, virt = %lx\r\n", phys, virt);
  776. vbp->vb.phys_addr = phys;
  777. vbp->vb.base = virt;
  778. }
  779. pte_unmap(pte);
  780. }
  781. }
  782. }
  783. ret = copy_to_user((void __user *)arg, &(vbp->vb), sizeof(vpudrv_buffer_t));
  784. if (ret) {
  785. kfree(vbp);
  786. ret = -EFAULT;
  787. up(&s_vpu_sem);
  788. break;
  789. }
  790. vbp->filp = filp;
  791. spin_lock(&s_vpu_lock);
  792. list_add(&vbp->list, &s_vbp_head);
  793. spin_unlock(&s_vpu_lock);
  794. up(&s_vpu_sem);
  795. }
  796. }
  797. break;
  798. case VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY:
  799. {
  800. vpudrv_buffer_pool_t *vbp;
  801. DPRINTK("[VPUDRV][+]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  802. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  803. vbp = kzalloc(sizeof(*vbp), GFP_KERNEL);
  804. if (!vbp) {
  805. up(&s_vpu_sem);
  806. return -ENOMEM;
  807. }
  808. ret = copy_from_user(&(vbp->vb), (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  809. if (ret) {
  810. kfree(vbp);
  811. up(&s_vpu_sem);
  812. return -EFAULT;
  813. }
  814. ret = vpu_alloc_dma_buffer(&(vbp->vb));
  815. if (ret == -1) {
  816. ret = -ENOMEM;
  817. kfree(vbp);
  818. up(&s_vpu_sem);
  819. break;
  820. }
  821. ret = copy_to_user((void __user *)arg, &(vbp->vb), sizeof(vpudrv_buffer_t));
  822. if (ret) {
  823. kfree(vbp);
  824. ret = -EFAULT;
  825. up(&s_vpu_sem);
  826. break;
  827. }
  828. vbp->filp = filp;
  829. spin_lock(&s_vpu_lock);
  830. list_add(&vbp->list, &s_vbp_head);
  831. spin_unlock(&s_vpu_lock);
  832. up(&s_vpu_sem);
  833. }
  834. DPRINTK("[VPUDRV][-]VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY\n");
  835. }
  836. break;
  837. case VDI_IOCTL_FREE_PHYSICALMEMORY:
  838. {
  839. vpudrv_buffer_pool_t *vbp, *n;
  840. vpudrv_buffer_t vb;
  841. DPRINTK("[VPUDRV][+]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  842. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  843. ret = copy_from_user(&vb, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  844. if (ret) {
  845. up(&s_vpu_sem);
  846. return -EACCES;
  847. }
  848. if (vb.base)
  849. vpu_free_dma_buffer(&vb);
  850. spin_lock(&s_vpu_lock);
  851. list_for_each_entry_safe(vbp, n, &s_vbp_head, list)
  852. {
  853. if (vbp->vb.base == vb.base) {
  854. list_del(&vbp->list);
  855. kfree(vbp);
  856. break;
  857. }
  858. }
  859. spin_unlock(&s_vpu_lock);
  860. up(&s_vpu_sem);
  861. }
  862. DPRINTK("[VPUDRV][-]VDI_IOCTL_FREE_PHYSICALMEMORY\n");
  863. }
  864. break;
  865. case VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO:
  866. {
  867. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  868. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO\n");
  869. if (s_video_memory.base != 0) {
  870. ret = copy_to_user((void __user *)arg, &s_video_memory, sizeof(vpudrv_buffer_t));
  871. if (ret != 0)
  872. ret = -EFAULT;
  873. } else {
  874. ret = -EFAULT;
  875. }
  876. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO\n");
  877. #endif
  878. }
  879. break;
  880. case VDI_IOCTL_WAIT_INTERRUPT:
  881. {
  882. vpudrv_intr_info_t info;
  883. #ifdef SUPPORT_MULTI_INST_INTR
  884. u32 intr_inst_index;
  885. u32 intr_reason_in_q;
  886. u32 interrupt_flag_in_q;
  887. #endif
  888. DPRINTK("[VPUDRV][+]VDI_IOCTL_WAIT_INTERRUPT\n");
  889. ret = copy_from_user(&info, (vpudrv_intr_info_t *)arg, sizeof(vpudrv_intr_info_t));
  890. if (ret != 0)
  891. {
  892. return -EFAULT;
  893. }
  894. #ifdef SUPPORT_MULTI_INST_INTR
  895. intr_inst_index = info.intr_inst_index;
  896. intr_reason_in_q = 0;
  897. interrupt_flag_in_q = kfifo_out_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason_in_q, sizeof(u32), &s_kfifo_lock);
  898. if (interrupt_flag_in_q > 0)
  899. {
  900. dev->interrupt_reason[intr_inst_index] = intr_reason_in_q;
  901. DPRINTK("[VPUDRV] Interrupt Remain : intr_inst_index=%d, intr_reason_in_q=0x%x, interrupt_flag_in_q=%d\n", intr_inst_index, intr_reason_in_q, interrupt_flag_in_q);
  902. goto INTERRUPT_REMAIN_IN_QUEUE;
  903. }
  904. #endif
  905. #ifdef SUPPORT_MULTI_INST_INTR
  906. #ifdef SUPPORT_TIMEOUT_RESOLUTION
  907. kt = ktime_set(0, info.timeout*1000*1000);
  908. ret = wait_event_interruptible_hrtimeout(s_interrupt_wait_q[intr_inst_index], s_interrupt_flag[intr_inst_index] != 0, kt);
  909. #else
  910. ret = wait_event_interruptible_timeout(s_interrupt_wait_q[intr_inst_index], s_interrupt_flag[intr_inst_index] != 0, msecs_to_jiffies(info.timeout));
  911. #endif
  912. #else
  913. ret = wait_event_interruptible_timeout(s_interrupt_wait_q, s_interrupt_flag != 0, msecs_to_jiffies(info.timeout));
  914. #endif
  915. #ifdef SUPPORT_TIMEOUT_RESOLUTION
  916. if (ret == -ETIME) {
  917. //DPRINTK("[VPUDRV][-]VDI_IOCTL_WAIT_INTERRUPT timeout = %d \n", info.timeout);
  918. break;
  919. }
  920. #endif
  921. if (!ret) {
  922. ret = -ETIME;
  923. break;
  924. }
  925. if (signal_pending(current)) {
  926. ret = -ERESTARTSYS;
  927. break;
  928. }
  929. #ifdef SUPPORT_MULTI_INST_INTR
  930. intr_reason_in_q = 0;
  931. interrupt_flag_in_q = kfifo_out_spinlocked(&s_interrupt_pending_q[intr_inst_index], &intr_reason_in_q, sizeof(u32), &s_kfifo_lock);
  932. if (interrupt_flag_in_q > 0) {
  933. dev->interrupt_reason[intr_inst_index] = intr_reason_in_q;
  934. }
  935. else {
  936. dev->interrupt_reason[intr_inst_index] = 0;
  937. }
  938. #endif
  939. #ifdef SUPPORT_MULTI_INST_INTR
  940. DPRINTK("[VPUDRV] inst_index(%d), s_interrupt_flag(%d), reason(0x%08lx)\n", intr_inst_index, s_interrupt_flag[intr_inst_index], dev->interrupt_reason[intr_inst_index]);
  941. #else
  942. DPRINTK("[VPUDRV] s_interrupt_flag(%d), reason(0x%08lx)\n", s_interrupt_flag, dev->interrupt_reason);
  943. #endif
  944. #ifdef SUPPORT_MULTI_INST_INTR
  945. INTERRUPT_REMAIN_IN_QUEUE:
  946. info.intr_reason = dev->interrupt_reason[intr_inst_index];
  947. s_interrupt_flag[intr_inst_index] = 0;
  948. dev->interrupt_reason[intr_inst_index] = 0;
  949. #else
  950. info.intr_reason = dev->interrupt_reason;
  951. s_interrupt_flag = 0;
  952. dev->interrupt_reason = 0;
  953. #endif
  954. #ifdef VPU_IRQ_CONTROL
  955. enable_irq(s_vpu_irq);
  956. #endif
  957. ret = copy_to_user((void __user *)arg, &info, sizeof(vpudrv_intr_info_t));
  958. DPRINTK("[VPUDRV][-]VDI_IOCTL_WAIT_INTERRUPT\n");
  959. if (ret != 0)
  960. {
  961. return -EFAULT;
  962. }
  963. }
  964. break;
  965. case VDI_IOCTL_SET_CLOCK_GATE:
  966. {
  967. u32 clkgate;
  968. DPRINTK("[VPUDRV][+]VDI_IOCTL_SET_CLOCK_GATE\n");
  969. if (get_user(clkgate, (u32 __user *) arg))
  970. return -EFAULT;
  971. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  972. if (clkgate)
  973. vpu_clk_enable(s_vpu_clk);
  974. else
  975. vpu_clk_disable(s_vpu_clk);
  976. #endif
  977. DPRINTK("[VPUDRV][-]VDI_IOCTL_SET_CLOCK_GATE\n");
  978. }
  979. break;
  980. case VDI_IOCTL_GET_INSTANCE_POOL:
  981. {
  982. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_INSTANCE_POOL\n");
  983. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  984. if (s_instance_pool.base != 0) {
  985. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(vpudrv_buffer_t));
  986. if (ret != 0)
  987. ret = -EFAULT;
  988. } else {
  989. ret = copy_from_user(&s_instance_pool, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  990. if (ret == 0) {
  991. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  992. s_instance_pool.size = PAGE_ALIGN(s_instance_pool.size);
  993. s_instance_pool.base = (unsigned long)vmalloc(s_instance_pool.size);
  994. s_instance_pool.phys_addr = s_instance_pool.base;
  995. if (s_instance_pool.base != 0)
  996. #else
  997. if (vpu_alloc_dma_buffer(&s_instance_pool) != -1)
  998. #endif
  999. {
  1000. memset((void *)s_instance_pool.base, 0x0, s_instance_pool.size); /*clearing memory*/
  1001. ret = copy_to_user((void __user *)arg, &s_instance_pool, sizeof(vpudrv_buffer_t));
  1002. if (ret == 0) {
  1003. /* success to get memory for instance pool */
  1004. up(&s_vpu_sem);
  1005. break;
  1006. }
  1007. }
  1008. }
  1009. ret = -EFAULT;
  1010. }
  1011. up(&s_vpu_sem);
  1012. }
  1013. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_INSTANCE_POOL\n");
  1014. }
  1015. break;
  1016. case VDI_IOCTL_GET_COMMON_MEMORY:
  1017. {
  1018. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_COMMON_MEMORY\n");
  1019. if (s_common_memory.base != 0) {
  1020. ret = copy_to_user((void __user *)arg, &s_common_memory, sizeof(vpudrv_buffer_t));
  1021. if (ret != 0)
  1022. ret = -EFAULT;
  1023. } else {
  1024. ret = copy_from_user(&s_common_memory, (vpudrv_buffer_t *)arg, sizeof(vpudrv_buffer_t));
  1025. if (ret == 0) {
  1026. if (vpu_alloc_dma_buffer(&s_common_memory) != -1) {
  1027. ret = copy_to_user((void __user *)arg, &s_common_memory, sizeof(vpudrv_buffer_t));
  1028. if (ret == 0) {
  1029. /* success to get memory for common memory */
  1030. break;
  1031. }
  1032. }
  1033. }
  1034. ret = -EFAULT;
  1035. }
  1036. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_COMMON_MEMORY\n");
  1037. }
  1038. break;
  1039. case VDI_IOCTL_OPEN_INSTANCE:
  1040. {
  1041. vpudrv_inst_info_t inst_info;
  1042. vpudrv_instanace_list_t *vil, *n;
  1043. vil = kzalloc(sizeof(*vil), GFP_KERNEL);
  1044. if (!vil)
  1045. return -ENOMEM;
  1046. if (copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t)))
  1047. return -EFAULT;
  1048. vil->inst_idx = inst_info.inst_idx;
  1049. vil->core_idx = inst_info.core_idx;
  1050. vil->filp = filp;
  1051. spin_lock(&s_vpu_lock);
  1052. list_add(&vil->list, &s_inst_list_head);
  1053. inst_info.inst_open_count = 0; /* counting the current open instance number */
  1054. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  1055. {
  1056. if (vil->core_idx == inst_info.core_idx)
  1057. inst_info.inst_open_count++;
  1058. }
  1059. #ifdef SUPPORT_MULTI_INST_INTR
  1060. kfifo_reset(&s_interrupt_pending_q[inst_info.inst_idx]);
  1061. #endif
  1062. spin_unlock(&s_vpu_lock);
  1063. s_vpu_open_ref_count++; /* flag just for that vpu is in opened or closed */
  1064. if (copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t))) {
  1065. kfree(vil);
  1066. return -EFAULT;
  1067. }
  1068. DPRINTK("[VPUDRV] VDI_IOCTL_OPEN_INSTANCE core_idx=%d, inst_idx=%d, s_vpu_open_ref_count=%d, inst_open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, s_vpu_open_ref_count, inst_info.inst_open_count);
  1069. }
  1070. break;
  1071. case VDI_IOCTL_CLOSE_INSTANCE:
  1072. {
  1073. vpudrv_inst_info_t inst_info;
  1074. vpudrv_instanace_list_t *vil, *n;
  1075. u32 found = 0;
  1076. DPRINTK("[VPUDRV][+]VDI_IOCTL_CLOSE_INSTANCE\n");
  1077. if (copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t)))
  1078. return -EFAULT;
  1079. spin_lock(&s_vpu_lock);
  1080. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  1081. {
  1082. if (vil->inst_idx == inst_info.inst_idx && vil->core_idx == inst_info.core_idx) {
  1083. list_del(&vil->list);
  1084. kfree(vil);
  1085. found = 1;
  1086. break;
  1087. }
  1088. }
  1089. if (0 == found) {
  1090. spin_unlock(&s_vpu_lock);
  1091. return -EINVAL;
  1092. }
  1093. inst_info.inst_open_count = 0; /* counting the current open instance number */
  1094. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  1095. {
  1096. if (vil->core_idx == inst_info.core_idx)
  1097. inst_info.inst_open_count++;
  1098. }
  1099. #ifdef SUPPORT_MULTI_INST_INTR
  1100. kfifo_reset(&s_interrupt_pending_q[inst_info.inst_idx]);
  1101. #endif
  1102. spin_unlock(&s_vpu_lock);
  1103. s_vpu_open_ref_count--; /* flag just for that vpu is in opened or closed */
  1104. if (copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t)))
  1105. return -EFAULT;
  1106. DPRINTK("[VPUDRV] VDI_IOCTL_CLOSE_INSTANCE core_idx=%d, inst_idx=%d, s_vpu_open_ref_count=%d, inst_open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, s_vpu_open_ref_count, inst_info.inst_open_count);
  1107. }
  1108. break;
  1109. case VDI_IOCTL_GET_INSTANCE_NUM:
  1110. {
  1111. vpudrv_inst_info_t inst_info;
  1112. vpudrv_instanace_list_t *vil, *n;
  1113. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_INSTANCE_NUM\n");
  1114. ret = copy_from_user(&inst_info, (vpudrv_inst_info_t *)arg, sizeof(vpudrv_inst_info_t));
  1115. if (ret != 0)
  1116. break;
  1117. spin_lock(&s_vpu_lock);
  1118. inst_info.inst_open_count = 0;
  1119. list_for_each_entry_safe(vil, n, &s_inst_list_head, list)
  1120. {
  1121. if (vil->core_idx == inst_info.core_idx)
  1122. inst_info.inst_open_count++;
  1123. }
  1124. spin_unlock(&s_vpu_lock);
  1125. ret = copy_to_user((void __user *)arg, &inst_info, sizeof(vpudrv_inst_info_t));
  1126. DPRINTK("[VPUDRV] VDI_IOCTL_GET_INSTANCE_NUM core_idx=%d, inst_idx=%d, open_count=%d\n", (int)inst_info.core_idx, (int)inst_info.inst_idx, inst_info.inst_open_count);
  1127. }
  1128. break;
  1129. case VDI_IOCTL_RESET:
  1130. {
  1131. vpu_hw_reset();
  1132. }
  1133. break;
  1134. case VDI_IOCTL_GET_REGISTER_INFO:
  1135. {
  1136. DPRINTK("[VPUDRV][+]VDI_IOCTL_GET_REGISTER_INFO\n");
  1137. ret = copy_to_user((void __user *)arg, &s_vpu_register, sizeof(vpudrv_buffer_t));
  1138. if (ret != 0)
  1139. ret = -EFAULT;
  1140. DPRINTK("[VPUDRV][-]VDI_IOCTL_GET_REGISTER_INFO s_vpu_register.phys_addr==0x%lx, s_vpu_register.virt_addr=0x%lx, s_vpu_register.size=%d\n", s_vpu_register.phys_addr , s_vpu_register.virt_addr, s_vpu_register.size);
  1141. }
  1142. break;
  1143. case VDI_IOCTL_FLUSH_DCACHE:
  1144. {
  1145. vpudrv_flush_cache_t cache_info;
  1146. ret = copy_from_user(&cache_info, (vpudrv_flush_cache_t *)arg, sizeof(vpudrv_flush_cache_t));
  1147. if (ret != 0)
  1148. ret = -EFAULT;
  1149. if(cache_info.flag)
  1150. starfive_flush_dcache(cache_info.start,cache_info.size);
  1151. }
  1152. break;
  1153. case VDI_IOCTL_CPUFREQ_SAVEENV:
  1154. {
  1155. #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_USE_PLL_DYNAMIC_FREQ)
  1156. vpu_freq_save_env();
  1157. #endif
  1158. }
  1159. break;
  1160. case VDI_IOCTL_CPUFREQ_PUTENV:
  1161. {
  1162. #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_USE_PLL_DYNAMIC_FREQ)
  1163. vpu_freq_put_env();
  1164. #endif
  1165. }
  1166. break;
  1167. default:
  1168. {
  1169. printk(KERN_ERR "[VPUDRV] No such IOCTL, cmd is %d\n", cmd);
  1170. }
  1171. break;
  1172. }
  1173. return ret;
  1174. }
  1175. static ssize_t vpu_read(struct file *filp, char __user *buf, size_t len, loff_t *ppos)
  1176. {
  1177. return -1;
  1178. }
  1179. static ssize_t vpu_write(struct file *filp, const char __user *buf, size_t len, loff_t *ppos)
  1180. {
  1181. /* DPRINTK("[VPUDRV] vpu_write len=%d\n", (int)len); */
  1182. if (!buf) {
  1183. printk(KERN_ERR "[VPUDRV] vpu_write buf = NULL error \n");
  1184. return -EFAULT;
  1185. }
  1186. if (len == sizeof(vpu_bit_firmware_info_t)) {
  1187. vpu_bit_firmware_info_t *bit_firmware_info;
  1188. bit_firmware_info = kmalloc(sizeof(vpu_bit_firmware_info_t), GFP_KERNEL);
  1189. if (!bit_firmware_info) {
  1190. printk(KERN_ERR "[VPUDRV] vpu_write bit_firmware_info allocation error \n");
  1191. return -EFAULT;
  1192. }
  1193. if (copy_from_user(bit_firmware_info, buf, len)) {
  1194. printk(KERN_ERR "[VPUDRV] vpu_write copy_from_user error for bit_firmware_info\n");
  1195. return -EFAULT;
  1196. }
  1197. if (bit_firmware_info->size == sizeof(vpu_bit_firmware_info_t)) {
  1198. DPRINTK("[VPUDRV] vpu_write set bit_firmware_info coreIdx=0x%x, reg_base_offset=0x%x size=0x%x, bit_code[0]=0x%x\n",
  1199. bit_firmware_info->core_idx, (int)bit_firmware_info->reg_base_offset, bit_firmware_info->size, bit_firmware_info->bit_code[0]);
  1200. if (bit_firmware_info->core_idx > MAX_NUM_VPU_CORE) {
  1201. printk(KERN_ERR "[VPUDRV] vpu_write coreIdx[%d] is exceeded than MAX_NUM_VPU_CORE[%d]\n", bit_firmware_info->core_idx, MAX_NUM_VPU_CORE);
  1202. return -ENODEV;
  1203. }
  1204. memcpy((void *)&s_bit_firmware_info[bit_firmware_info->core_idx], bit_firmware_info, sizeof(vpu_bit_firmware_info_t));
  1205. kfree(bit_firmware_info);
  1206. return len;
  1207. }
  1208. kfree(bit_firmware_info);
  1209. }
  1210. return -1;
  1211. }
  1212. static int vpu_release(struct inode *inode, struct file *filp)
  1213. {
  1214. int ret = 0;
  1215. u32 open_count;
  1216. #ifdef SUPPORT_MULTI_INST_INTR
  1217. int i;
  1218. #endif
  1219. DPRINTK("[VPUDRV] vpu_release\n");
  1220. if ((ret = down_interruptible(&s_vpu_sem)) == 0) {
  1221. /* found and free the not handled buffer by user applications */
  1222. vpu_free_buffers(filp);
  1223. /* found and free the not closed instance by user applications */
  1224. vpu_free_instances(filp);
  1225. spin_lock(&s_vpu_lock);
  1226. s_vpu_drv_context.open_count--;
  1227. open_count = s_vpu_drv_context.open_count;
  1228. spin_unlock(&s_vpu_lock);
  1229. if (open_count == 0) {
  1230. #ifdef SUPPORT_MULTI_INST_INTR
  1231. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1232. kfifo_reset(&s_interrupt_pending_q[i]);
  1233. }
  1234. #endif
  1235. if (s_instance_pool.base) {
  1236. DPRINTK("[VPUDRV] free instance pool\n");
  1237. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1238. vfree((const void *)s_instance_pool.base);
  1239. #else
  1240. vpu_free_dma_buffer(&s_instance_pool);
  1241. #endif
  1242. s_instance_pool.base = 0;
  1243. }
  1244. }
  1245. }
  1246. up(&s_vpu_sem);
  1247. pm_runtime_put_sync(s_vpu_clk->dev);
  1248. return 0;
  1249. }
  1250. static int vpu_fasync(int fd, struct file *filp, int mode)
  1251. {
  1252. struct vpu_drv_context_t *dev = (struct vpu_drv_context_t *)filp->private_data;
  1253. return fasync_helper(fd, filp, mode, &dev->async_queue);
  1254. }
  1255. static int vpu_map_to_register(struct file *fp, struct vm_area_struct *vm)
  1256. {
  1257. unsigned long pfn;
  1258. vm->vm_flags |= VM_IO | VM_RESERVED;
  1259. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  1260. pfn = s_vpu_register.phys_addr >> PAGE_SHIFT;
  1261. return remap_pfn_range(vm, vm->vm_start, pfn, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1262. }
  1263. static int vpu_map_to_physical_memory(struct file *fp, struct vm_area_struct *vm)
  1264. {
  1265. vm->vm_flags |= VM_IO | VM_RESERVED;
  1266. vm->vm_page_prot = pgprot_noncached(vm->vm_page_prot);
  1267. return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1268. }
  1269. static int vpu_map_to_instance_pool_memory(struct file *fp, struct vm_area_struct *vm)
  1270. {
  1271. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1272. int ret;
  1273. long length = vm->vm_end - vm->vm_start;
  1274. unsigned long start = vm->vm_start;
  1275. char *vmalloc_area_ptr = (char *)s_instance_pool.base;
  1276. unsigned long pfn;
  1277. vm->vm_flags |= VM_RESERVED;
  1278. /* loop over all pages, map it page individually */
  1279. while (length > 0)
  1280. {
  1281. pfn = vmalloc_to_pfn(vmalloc_area_ptr);
  1282. if ((ret = remap_pfn_range(vm, start, pfn, PAGE_SIZE, PAGE_SHARED)) < 0) {
  1283. return ret;
  1284. }
  1285. start += PAGE_SIZE;
  1286. vmalloc_area_ptr += PAGE_SIZE;
  1287. length -= PAGE_SIZE;
  1288. }
  1289. return 0;
  1290. #else
  1291. vm->vm_flags |= VM_RESERVED;
  1292. return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff, vm->vm_end-vm->vm_start, vm->vm_page_prot) ? -EAGAIN : 0;
  1293. #endif
  1294. }
  1295. /*!
  1296. * @brief memory map interface for vpu file operation
  1297. * @return 0 on success or negative error code on error
  1298. */
  1299. static int vpu_mmap(struct file *fp, struct vm_area_struct *vm)
  1300. {
  1301. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1302. if (vm->vm_pgoff == 0)
  1303. return vpu_map_to_instance_pool_memory(fp, vm);
  1304. if (vm->vm_pgoff == (s_vpu_register.phys_addr>>PAGE_SHIFT))
  1305. return vpu_map_to_register(fp, vm);
  1306. return vpu_map_to_physical_memory(fp, vm);
  1307. #else
  1308. if (vm->vm_pgoff) {
  1309. if (vm->vm_pgoff == (s_instance_pool.phys_addr>>PAGE_SHIFT))
  1310. return vpu_map_to_instance_pool_memory(fp, vm);
  1311. return vpu_map_to_physical_memory(fp, vm);
  1312. } else {
  1313. return vpu_map_to_register(fp, vm);
  1314. }
  1315. #endif
  1316. }
  1317. struct file_operations vpu_fops = {
  1318. .owner = THIS_MODULE,
  1319. .open = vpu_open,
  1320. .read = vpu_read,
  1321. .write = vpu_write,
  1322. /*.ioctl = vpu_ioctl, // for kernel 2.6.9 of C&M*/
  1323. .unlocked_ioctl = vpu_ioctl,
  1324. .release = vpu_release,
  1325. .fasync = vpu_fasync,
  1326. .mmap = vpu_mmap,
  1327. };
  1328. static int vpu_probe(struct platform_device *pdev)
  1329. {
  1330. int err = 0;
  1331. struct resource *res = NULL;
  1332. struct device *devices;
  1333. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1334. struct resource res_cma;
  1335. struct device_node *node;
  1336. #endif
  1337. DPRINTK("[VPUDRV] vpu_probe\n");
  1338. if(pdev){
  1339. vpu_dev = &pdev->dev;
  1340. vpu_dev->coherent_dma_mask = 0xffffffff;;
  1341. dev_info(vpu_dev,"device init.\n");
  1342. }
  1343. if (pdev)
  1344. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1345. if (res) {/* if platform driver is implemented */
  1346. s_vpu_register.phys_addr = res->start;
  1347. s_vpu_register.virt_addr = (unsigned long)ioremap_nocache(res->start, res->end - res->start);
  1348. s_vpu_register.size = res->end - res->start;
  1349. DPRINTK("[VPUDRV] : vpu base address get from platform driver physical base addr==0x%lx, virtual base=0x%lx\n", s_vpu_register.phys_addr , s_vpu_register.virt_addr);
  1350. } else {
  1351. s_vpu_register.phys_addr = VPU_REG_BASE_ADDR;
  1352. s_vpu_register.virt_addr = (unsigned long)ioremap_nocache(s_vpu_register.phys_addr, VPU_REG_SIZE);
  1353. s_vpu_register.size = VPU_REG_SIZE;
  1354. DPRINTK("[VPUDRV] : vpu base address get from defined value physical base addr==0x%lx, virtual base=0x%lx\n", s_vpu_register.phys_addr, s_vpu_register.virt_addr);
  1355. }
  1356. /* get the major number of the character device */
  1357. if ((alloc_chrdev_region(&s_vpu_devt, 0, 1, VPU_DEV_NAME)) < 0) {
  1358. err = -EBUSY;
  1359. printk(KERN_ERR "could not allocate major number\n");
  1360. goto ERROR_PROVE_DEVICE;
  1361. }
  1362. printk(KERN_INFO "SUCCESS alloc_chrdev_region\n");
  1363. s_vpu_major = MAJOR(s_vpu_devt);
  1364. /* initialize the device structure and register the device with the kernel */
  1365. cdev_init(&s_vpu_cdev, &vpu_fops);
  1366. if ((cdev_add(&s_vpu_cdev, s_vpu_devt, 1)) < 0) {
  1367. err = -EBUSY;
  1368. printk(KERN_ERR "could not allocate chrdev\n");
  1369. goto ERROR_PROVE_DEVICE;
  1370. }
  1371. s_vpu_class = class_create(THIS_MODULE, VPU_DEV_NAME);
  1372. if (IS_ERR(s_vpu_class)) {
  1373. dev_err(vpu_dev, "class creat error.\n");
  1374. goto ERROR_CRART_CLASS;
  1375. }
  1376. devices = device_create(s_vpu_class, 0, MKDEV(s_vpu_major, 0),
  1377. NULL, VPU_DEV_NAME);
  1378. if (IS_ERR(devices)) {
  1379. dev_err(vpu_dev, "device creat error.\n");
  1380. goto ERROR_CREAT_DEVICE;
  1381. }
  1382. if (pdev)
  1383. s_vpu_clk = vpu_clk_get(pdev);
  1384. else
  1385. s_vpu_clk = vpu_clk_get(NULL);
  1386. if (!s_vpu_clk)
  1387. printk(KERN_ERR "[VPUDRV] : not support clock controller.\n");
  1388. else
  1389. DPRINTK("[VPUDRV] : get clock controller s_vpu_clk=%p\n", s_vpu_clk);
  1390. #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_USE_PLL_DYNAMIC_FREQ)
  1391. vpu_freq_init(&pdev->dev);
  1392. #endif
  1393. vpu_pmu_enable(s_vpu_clk->dev);
  1394. vpu_clk_enable(s_vpu_clk);
  1395. reset_control_deassert(s_vpu_clk->resets);
  1396. #ifdef VPU_SUPPORT_ISR
  1397. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1398. if (pdev)
  1399. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1400. if (res) {/* if platform driver is implemented */
  1401. s_vpu_irq = res->start;
  1402. DPRINTK("[VPUDRV] : vpu irq number get from platform driver irq=0x%x\n", s_vpu_irq);
  1403. } else {
  1404. DPRINTK("[VPUDRV] : vpu irq number get from defined value irq=0x%x\n", s_vpu_irq);
  1405. }
  1406. #else
  1407. DPRINTK("[VPUDRV] : vpu irq number get from defined value irq=0x%x\n", s_vpu_irq);
  1408. #endif
  1409. err = request_irq(s_vpu_irq, vpu_irq_handler, 0, pdev->name, (void *)(&s_vpu_drv_context));
  1410. if (err) {
  1411. printk(KERN_ERR "[VPUDRV] : fail to register interrupt handler\n");
  1412. goto ERROR_PROVE_DEVICE;
  1413. }
  1414. #endif
  1415. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1416. node = of_parse_phandle(vpu_dev->of_node, "memory-region", 0);
  1417. if(node){
  1418. dev_info(vpu_dev, "Get mem form memory-region\n");
  1419. of_address_to_resource(node, 0, &res_cma);
  1420. s_video_memory.size = resource_size(&res_cma);
  1421. s_video_memory.phys_addr = res_cma.start;
  1422. }else{
  1423. dev_info(vpu_dev, "Get mem form memory-region fiiled.please check the dts file.\n");
  1424. return 0;
  1425. }
  1426. s_video_memory.base = (unsigned long)ioremap_nocache(DRAM_MEM2SYS(s_video_memory.phys_addr), PAGE_ALIGN(s_video_memory.size));
  1427. if (!s_video_memory.base) {
  1428. printk(KERN_ERR "[VPUDRV] : fail to remap video memory physical phys_addr=0x%lx, base=0x%lx, size=%d\n", s_video_memory.phys_addr, s_video_memory.base, (int)s_video_memory.size);
  1429. goto ERROR_PROVE_DEVICE;
  1430. }
  1431. if (vmem_init(&s_vmem, s_video_memory.phys_addr, s_video_memory.size) < 0) {
  1432. printk(KERN_ERR "[VPUDRV] : fail to init vmem system\n");
  1433. goto ERROR_PROVE_DEVICE;
  1434. }
  1435. DPRINTK("[VPUDRV] success to probe vpu device with reserved video memory phys_addr=0x%lx, base=0x%lx, size=%d\n", s_video_memory.phys_addr, s_video_memory.base,s_video_memory.size);
  1436. #else
  1437. DPRINTK("[VPUDRV] success to probe vpu device with non reserved video memory\n");
  1438. #endif
  1439. return 0;
  1440. ERROR_CREAT_DEVICE:
  1441. class_destroy(s_vpu_class);
  1442. ERROR_CRART_CLASS:
  1443. cdev_del(&s_vpu_cdev);
  1444. ERROR_PROVE_DEVICE:
  1445. if (s_vpu_major)
  1446. unregister_chrdev_region(s_vpu_major, 1);
  1447. if (s_vpu_register.virt_addr)
  1448. iounmap((void *)s_vpu_register.virt_addr);
  1449. return err;
  1450. }
  1451. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1452. static int vpu_remove(struct platform_device *pdev)
  1453. {
  1454. DPRINTK("[VPUDRV] vpu_remove\n");
  1455. if (s_instance_pool.base) {
  1456. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1457. vfree((const void *)s_instance_pool.base);
  1458. #else
  1459. vpu_free_dma_buffer(&s_instance_pool);
  1460. #endif
  1461. s_instance_pool.base = 0;
  1462. }
  1463. if (s_common_memory.base) {
  1464. vpu_free_dma_buffer(&s_common_memory);
  1465. s_common_memory.base = 0;
  1466. }
  1467. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1468. if (s_video_memory.base) {
  1469. iounmap((void *)s_video_memory.base);
  1470. s_video_memory.base = 0;
  1471. vmem_exit(&s_vmem);
  1472. }
  1473. #endif
  1474. if (s_vpu_major > 0) {
  1475. device_destroy(s_vpu_class, MKDEV(s_vpu_major, 0));
  1476. class_destroy(s_vpu_class);
  1477. cdev_del(&s_vpu_cdev);
  1478. unregister_chrdev_region(s_vpu_devt, 1);
  1479. s_vpu_major = 0;
  1480. }
  1481. #ifdef VPU_SUPPORT_ISR
  1482. if (s_vpu_irq)
  1483. free_irq(s_vpu_irq, &s_vpu_drv_context);
  1484. #endif
  1485. if (s_vpu_register.virt_addr)
  1486. iounmap((void *)s_vpu_register.virt_addr);
  1487. vpu_clk_put(s_vpu_clk);
  1488. vpu_pmu_disable(s_vpu_clk->dev);
  1489. return 0;
  1490. }
  1491. #endif /*VPU_SUPPORT_PLATFORM_DRIVER_REGISTER*/
  1492. #if defined(VPU_SUPPORT_PLATFORM_DRIVER_REGISTER) && defined(CONFIG_PM)
  1493. #define W5_MAX_CODE_BUF_SIZE (512*1024)
  1494. #define W5_CMD_INIT_VPU (0x0001)
  1495. #define W5_CMD_SLEEP_VPU (0x0004)
  1496. #define W5_CMD_WAKEUP_VPU (0x0002)
  1497. static void Wave5BitIssueCommand(int core, u32 cmd)
  1498. {
  1499. WriteVpuRegister(W5_VPU_BUSY_STATUS, 1);
  1500. WriteVpuRegister(W5_COMMAND, cmd);
  1501. WriteVpuRegister(W5_VPU_HOST_INT_REQ, 1);
  1502. return;
  1503. }
  1504. static int __maybe_unused vpu_runtime_suspend(struct device *dev)
  1505. {
  1506. reset_control_assert(s_vpu_clk->resets);
  1507. vpu_clk_disable(s_vpu_clk);
  1508. return 0;
  1509. }
  1510. static int __maybe_unused vpu_runtime_resume(struct device *dev)
  1511. {
  1512. vpu_clk_enable(s_vpu_clk);
  1513. return reset_control_deassert(s_vpu_clk->resets);
  1514. }
  1515. #ifdef CONFIG_PM_SLEEP
  1516. static int __maybe_unused vpu_suspend(struct device *dev)
  1517. {
  1518. int i;
  1519. int core;
  1520. unsigned long timeout = jiffies + HZ; /* vpu wait timeout to 1sec */
  1521. int product_code;
  1522. DPRINTK("[VPUDRV] vpu_suspend\n");
  1523. if (s_vpu_open_ref_count > 0) {
  1524. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  1525. if (s_bit_firmware_info[core].size == 0)
  1526. continue;
  1527. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  1528. if (PRODUCT_CODE_W_SERIES(product_code)) {
  1529. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1530. if (time_after(jiffies, timeout)) {
  1531. DPRINTK("SLEEP_VPU BUSY timeout");
  1532. goto DONE_SUSPEND;
  1533. }
  1534. }
  1535. Wave5BitIssueCommand(core, W5_CMD_SLEEP_VPU);
  1536. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1537. if (time_after(jiffies, timeout)) {
  1538. DPRINTK("SLEEP_VPU BUSY timeout");
  1539. goto DONE_SUSPEND;
  1540. }
  1541. }
  1542. if (ReadVpuRegister(W5_RET_SUCCESS) == 0) {
  1543. DPRINTK("SLEEP_VPU failed [0x%x]", ReadVpuRegister(W5_RET_FAIL_REASON));
  1544. goto DONE_SUSPEND;
  1545. }
  1546. }
  1547. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  1548. while (ReadVpuRegister(BIT_BUSY_FLAG)) {
  1549. if (time_after(jiffies, timeout))
  1550. goto DONE_SUSPEND;
  1551. }
  1552. for (i = 0; i < 64; i++)
  1553. s_vpu_reg_store[core][i] = ReadVpuRegister(BIT_BASE+(0x100+(i * 4)));
  1554. }
  1555. else {
  1556. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  1557. goto DONE_SUSPEND;
  1558. }
  1559. }
  1560. }
  1561. pm_runtime_set_suspended(dev);
  1562. return 0;
  1563. DONE_SUSPEND:
  1564. pm_runtime_set_suspended(dev);
  1565. return -EAGAIN;
  1566. }
  1567. static int __maybe_unused vpu_resume(struct device *dev)
  1568. {
  1569. int i;
  1570. int core;
  1571. u32 val;
  1572. unsigned long timeout = jiffies + HZ; /* vpu wait timeout to 1sec */
  1573. int product_code;
  1574. unsigned long code_base;
  1575. u32 code_size;
  1576. u32 remap_size;
  1577. int regVal;
  1578. u32 hwOption = 0;
  1579. DPRINTK("[VPUDRV] vpu_resume\n");
  1580. if (s_vpu_open_ref_count == 0)
  1581. pm_runtime_get_sync(dev);
  1582. else
  1583. pm_runtime_set_active(dev);
  1584. for (core = 0; core < MAX_NUM_VPU_CORE; core++) {
  1585. if (s_bit_firmware_info[core].size == 0) {
  1586. continue;
  1587. }
  1588. product_code = ReadVpuRegister(VPU_PRODUCT_CODE_REGISTER);
  1589. if (PRODUCT_CODE_W_SERIES(product_code)) {
  1590. code_base = s_common_memory.phys_addr;
  1591. /* ALIGN TO 4KB */
  1592. code_size = (W5_MAX_CODE_BUF_SIZE&~0xfff);
  1593. if (code_size < s_bit_firmware_info[core].size*2) {
  1594. goto DONE_WAKEUP;
  1595. }
  1596. regVal = 0;
  1597. WriteVpuRegister(W5_PO_CONF, regVal);
  1598. /* Reset All blocks */
  1599. regVal = 0x7ffffff;
  1600. WriteVpuRegister(W5_VPU_RESET_REQ, regVal); /*Reset All blocks*/
  1601. /* Waiting reset done */
  1602. while (ReadVpuRegister(W5_VPU_RESET_STATUS)) {
  1603. if (time_after(jiffies, timeout))
  1604. goto DONE_WAKEUP;
  1605. }
  1606. WriteVpuRegister(W5_VPU_RESET_REQ, 0);
  1607. /* remap page size */
  1608. remap_size = (code_size >> 12) & 0x1ff;
  1609. regVal = 0x80000000 | (W5_REMAP_CODE_INDEX<<12) | (0 << 16) | (1<<11) | remap_size;
  1610. WriteVpuRegister(W5_VPU_REMAP_CTRL, regVal);
  1611. WriteVpuRegister(W5_VPU_REMAP_VADDR,0x00000000); /* DO NOT CHANGE! */
  1612. WriteVpuRegister(W5_VPU_REMAP_PADDR,code_base);
  1613. WriteVpuRegister(W5_ADDR_CODE_BASE, code_base);
  1614. WriteVpuRegister(W5_CODE_SIZE, code_size);
  1615. WriteVpuRegister(W5_CODE_PARAM, 0);
  1616. WriteVpuRegister(W5_INIT_VPU_TIME_OUT_CNT, timeout);
  1617. WriteVpuRegister(W5_HW_OPTION, hwOption);
  1618. /* Interrupt */
  1619. if (product_code == WAVE521_CODE || product_code == WAVE521C_CODE ) {
  1620. regVal = (1<<INT_WAVE5_ENC_SET_PARAM);
  1621. regVal |= (1<<INT_WAVE5_ENC_PIC);
  1622. regVal |= (1<<INT_WAVE5_INIT_SEQ);
  1623. regVal |= (1<<INT_WAVE5_DEC_PIC);
  1624. regVal |= (1<<INT_WAVE5_BSBUF_EMPTY);
  1625. }
  1626. else {
  1627. // decoder
  1628. regVal = (1<<INT_WAVE5_INIT_SEQ);
  1629. regVal |= (1<<INT_WAVE5_DEC_PIC);
  1630. regVal |= (1<<INT_WAVE5_BSBUF_EMPTY);
  1631. }
  1632. WriteVpuRegister(W5_VPU_VINT_ENABLE, regVal);
  1633. Wave5BitIssueCommand(core, W5_CMD_INIT_VPU);
  1634. WriteVpuRegister(W5_VPU_REMAP_CORE_START, 1);
  1635. while (ReadVpuRegister(W5_VPU_BUSY_STATUS)) {
  1636. if (time_after(jiffies, timeout))
  1637. goto DONE_WAKEUP;
  1638. }
  1639. if (ReadVpuRegister(W5_RET_SUCCESS) == 0) {
  1640. DPRINTK("WAKEUP_VPU failed [0x%x]", ReadVpuRegister(W5_RET_FAIL_REASON));
  1641. goto DONE_WAKEUP;
  1642. }
  1643. }
  1644. else if (PRODUCT_CODE_NOT_W_SERIES(product_code)) {
  1645. WriteVpuRegister(BIT_CODE_RUN, 0);
  1646. /*---- LOAD BOOT CODE*/
  1647. for (i = 0; i < 512; i++) {
  1648. val = s_bit_firmware_info[core].bit_code[i];
  1649. WriteVpuRegister(BIT_CODE_DOWN, ((i << 16) | val));
  1650. }
  1651. for (i = 0 ; i < 64 ; i++)
  1652. WriteVpuRegister(BIT_BASE+(0x100+(i * 4)), s_vpu_reg_store[core][i]);
  1653. WriteVpuRegister(BIT_BUSY_FLAG, 1);
  1654. WriteVpuRegister(BIT_CODE_RESET, 1);
  1655. WriteVpuRegister(BIT_CODE_RUN, 1);
  1656. while (ReadVpuRegister(BIT_BUSY_FLAG)) {
  1657. if (time_after(jiffies, timeout))
  1658. goto DONE_WAKEUP;
  1659. }
  1660. }
  1661. else {
  1662. DPRINTK("[VPUDRV] Unknown product id : %08x\n", product_code);
  1663. goto DONE_WAKEUP;
  1664. }
  1665. }
  1666. if (s_vpu_open_ref_count == 0) {
  1667. pm_runtime_put_sync(dev);
  1668. pm_runtime_set_suspended(dev);
  1669. }
  1670. DONE_WAKEUP:
  1671. //if (s_vpu_open_ref_count > 0)
  1672. // vpu_clk_enable(s_vpu_clk);
  1673. return 0;
  1674. }
  1675. #endif /* CONFIG_PM_SLEEP */
  1676. #endif /* !CONFIG_PM */
  1677. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1678. static const struct of_device_id cm_vpu_match[] = {
  1679. {
  1680. .compatible = "c&m,cm511-vpu",
  1681. },
  1682. {
  1683. .compatible = "starfive,vdec",
  1684. },
  1685. {
  1686. /* end of table */
  1687. },
  1688. };
  1689. MODULE_DEVICE_TABLE(of, cm_vpu_match);
  1690. static const struct dev_pm_ops cm_vpu_pm_ops = {
  1691. SET_RUNTIME_PM_OPS(vpu_runtime_suspend,
  1692. vpu_runtime_resume, NULL)
  1693. //SET_SYSTEM_SLEEP_PM_OPS(vpu_suspend, vpu_resume)
  1694. };
  1695. static struct platform_driver vpu_driver = {
  1696. .driver = {
  1697. .name = VPU_PLATFORM_DEVICE_NAME,
  1698. .of_match_table = cm_vpu_match,
  1699. .pm = &cm_vpu_pm_ops,
  1700. },
  1701. .probe = vpu_probe,
  1702. .remove = vpu_remove,
  1703. };
  1704. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1705. static int __init vpu_init(void)
  1706. {
  1707. int res;
  1708. #ifdef SUPPORT_MULTI_INST_INTR
  1709. int i;
  1710. #endif
  1711. DPRINTK("[VPUDRV] begin vpu_init\n");
  1712. #ifdef SUPPORT_MULTI_INST_INTR
  1713. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1714. init_waitqueue_head(&s_interrupt_wait_q[i]);
  1715. }
  1716. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1717. #define MAX_INTERRUPT_QUEUE (16*MAX_NUM_INSTANCE)
  1718. res = kfifo_alloc(&s_interrupt_pending_q[i], MAX_INTERRUPT_QUEUE*sizeof(u32), GFP_KERNEL);
  1719. if (res) {
  1720. DPRINTK("[VPUDRV] kfifo_alloc failed 0x%x\n", res);
  1721. }
  1722. }
  1723. #else
  1724. init_waitqueue_head(&s_interrupt_wait_q);
  1725. #endif
  1726. s_common_memory.base = 0;
  1727. s_instance_pool.base = 0;
  1728. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1729. res = platform_driver_register(&vpu_driver);
  1730. #else
  1731. res = vpu_probe(NULL);
  1732. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1733. DPRINTK("[VPUDRV] end vpu_init result=0x%x\n", res);
  1734. return res;
  1735. }
  1736. static void __exit vpu_exit(void)
  1737. {
  1738. #ifdef VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
  1739. DPRINTK("[VPUDRV] vpu_exit\n");
  1740. platform_driver_unregister(&vpu_driver);
  1741. #else /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1742. #ifdef VPU_SUPPORT_CLOCK_CONTROL
  1743. #else
  1744. vpu_clk_disable(s_vpu_clk);
  1745. #endif
  1746. vpu_clk_put(s_vpu_clk);
  1747. if (s_instance_pool.base) {
  1748. #ifdef USE_VMALLOC_FOR_INSTANCE_POOL_MEMORY
  1749. vfree((const void *)s_instance_pool.base);
  1750. #else
  1751. vpu_free_dma_buffer(&s_instance_pool);
  1752. #endif
  1753. s_instance_pool.base = 0;
  1754. }
  1755. if (s_common_memory.base) {
  1756. vpu_free_dma_buffer(&s_common_memory);
  1757. s_common_memory.base = 0;
  1758. }
  1759. #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_USE_PLL_DYNAMIC_FREQ)
  1760. vpu_freq_close();
  1761. #endif
  1762. #ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
  1763. if (s_video_memory.base) {
  1764. iounmap((void *)s_video_memory.base);
  1765. s_video_memory.base = 0;
  1766. vmem_exit(&s_vmem);
  1767. }
  1768. #endif
  1769. if (s_vpu_major > 0) {
  1770. device_destroy(s_vpu_class, MKDEV(s_vpu_major, 0));
  1771. class_destroy(s_vpu_class);
  1772. cdev_del(&s_vpu_cdev);
  1773. unregister_chrdev_region(s_vpu_devt, 1);
  1774. s_vpu_major = 0;
  1775. }
  1776. #ifdef VPU_SUPPORT_ISR
  1777. if (s_vpu_irq)
  1778. free_irq(s_vpu_irq, &s_vpu_drv_context);
  1779. #endif
  1780. #ifdef SUPPORT_MULTI_INST_INTR
  1781. {
  1782. int i;
  1783. for (i=0; i<MAX_NUM_INSTANCE; i++) {
  1784. kfifo_free(&s_interrupt_pending_q[i]);
  1785. }
  1786. }
  1787. #endif
  1788. if (s_vpu_register.virt_addr) {
  1789. iounmap((void *)s_vpu_register.virt_addr);
  1790. s_vpu_register.virt_addr = 0x00;
  1791. }
  1792. #endif /* VPU_SUPPORT_PLATFORM_DRIVER_REGISTER */
  1793. return;
  1794. }
  1795. MODULE_AUTHOR("A customer using C&M VPU, Inc.");
  1796. MODULE_DESCRIPTION("VPU linux driver");
  1797. MODULE_LICENSE("Dual BSD/GPL");
  1798. module_init(vpu_init);
  1799. module_exit(vpu_exit);
  1800. static int vpu_pmu_enable(struct device *dev)
  1801. {
  1802. pm_runtime_set_active(dev);
  1803. pm_runtime_enable(dev);
  1804. return 0;
  1805. }
  1806. static void vpu_pmu_disable(struct device *dev)
  1807. {
  1808. pm_runtime_disable(dev);
  1809. pm_runtime_set_suspended(dev);
  1810. }
  1811. /* clk&reset for starfive jh7110*/
  1812. #ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
  1813. #define CLK_ENABLE_DATA 1
  1814. #define CLK_DISABLE_DATA 0
  1815. #define CLK_EN_SHIFT 31
  1816. #define CLK_EN_MASK 0x80000000U
  1817. #define SAIF_BD_APBS_BASE 0x13020000
  1818. #define WAVE511_CLK_AXI_CTRL 0x118U
  1819. #define WAVE511_CLK_BPU_CTRL 0x11cU
  1820. #define WAVE511_CLK_VCE_CTRL 0x120U
  1821. #define WAVE511_CLK_APB_CTRL 0x124U
  1822. #define WAVE511_CLK_NOCBUS_CTRL 0x130U
  1823. #define RSTGEN_SOFTWARE_RESET_ASSERT1 0x2FCU
  1824. #define RSTGEN_SOFTWARE_RESET_STATUS1 0x30CU
  1825. #define RSTN_AXI_MASK (0x1 << 15)
  1826. #define RSTN_BPU_MASK (0x1 << 16)
  1827. #define RSTN_VCE_MASK (0x1 << 17)
  1828. #define RSTN_APB_MASK (0x1 << 18)
  1829. #define RSTN_128B_AXIMEM_MASK (0x1 << 21)
  1830. static uint32_t saif_get_reg(const volatile void __iomem *addr,
  1831. uint32_t shift, uint32_t mask)
  1832. {
  1833. u32 tmp;
  1834. tmp = readl(addr);
  1835. tmp = (tmp & mask) >> shift;
  1836. return tmp;
  1837. }
  1838. static void saif_set_reg(volatile void __iomem *addr, uint32_t data,
  1839. uint32_t shift, uint32_t mask)
  1840. {
  1841. uint32_t tmp;
  1842. tmp = readl(addr);
  1843. tmp &= ~mask;
  1844. tmp |= (data << shift) & mask;
  1845. writel(tmp, addr);
  1846. }
  1847. static void saif_assert_rst(volatile void __iomem *addr,
  1848. const volatile void __iomem *addr_status, uint32_t mask)
  1849. {
  1850. uint32_t tmp;
  1851. tmp = readl(addr);
  1852. tmp |= mask;
  1853. writel(tmp, addr);
  1854. do {
  1855. tmp = readl(addr_status);
  1856. } while ((tmp & mask) != 0);
  1857. }
  1858. static void saif_clear_rst(volatile void __iomem *addr,
  1859. const volatile void __iomem *addr_status, uint32_t mask)
  1860. {
  1861. uint32_t tmp;
  1862. tmp = readl(addr);
  1863. tmp &= ~mask;
  1864. writel(tmp, addr);
  1865. do {
  1866. tmp = readl(addr_status);
  1867. } while ((tmp & mask) != mask);
  1868. }
  1869. static void vpu_noc_vdec_bus_control(vpu_clk_t *clk, bool enable)
  1870. {
  1871. if (enable)
  1872. saif_set_reg(clk->noc_bus, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1873. else
  1874. saif_set_reg(clk->noc_bus, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1875. }
  1876. static void vpu_clk_control(vpu_clk_t *clk, bool enable)
  1877. {
  1878. if (enable) {
  1879. /*enable*/
  1880. saif_set_reg(clk->apb_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1881. saif_set_reg(clk->axi_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1882. saif_set_reg(clk->bpu_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1883. saif_set_reg(clk->vce_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
  1884. /*clr-reset*/
  1885. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1886. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1887. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1888. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1889. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->aximem_128b.rst_mask);
  1890. } else {
  1891. /*assert-reset*/
  1892. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1893. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1894. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1895. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1896. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->aximem_128b.rst_mask);
  1897. /*disable*/
  1898. saif_set_reg(clk->apb_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1899. saif_set_reg(clk->axi_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1900. saif_set_reg(clk->bpu_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1901. saif_set_reg(clk->vce_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
  1902. }
  1903. }
  1904. static void vpu_clk_reset(vpu_clk_t *clk)
  1905. {
  1906. /*assert-reset*/
  1907. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1908. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1909. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1910. saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1911. /*clr-reset*/
  1912. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
  1913. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
  1914. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
  1915. saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
  1916. }
  1917. int vpu_hw_reset(void)
  1918. {
  1919. if (!s_vpu_clk)
  1920. return -1;
  1921. vpu_clk_reset(s_vpu_clk);
  1922. DPRINTK("[VPUDRV] reset vpu hardware. \n");
  1923. return 0;
  1924. }
  1925. static int vpu_of_clk_get(struct platform_device *pdev, vpu_clk_t *vpu_clk)
  1926. {
  1927. if (!pdev)
  1928. return -ENXIO;
  1929. vpu_clk->clkgen = ioremap(SAIF_BD_APBS_BASE, 0x400);
  1930. if (IS_ERR(vpu_clk->clkgen)) {
  1931. dev_err(&pdev->dev, "ioremap clkgen failed.\n");
  1932. return PTR_ERR(vpu_clk->clkgen);
  1933. }
  1934. /* clkgen define */
  1935. vpu_clk->axi_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_AXI_CTRL;
  1936. vpu_clk->bpu_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_BPU_CTRL;
  1937. vpu_clk->vce_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_VCE_CTRL;
  1938. vpu_clk->apb_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_APB_CTRL;
  1939. vpu_clk->noc_bus = vpu_clk->clkgen + WAVE511_CLK_NOCBUS_CTRL;
  1940. vpu_clk->en_mask = CLK_EN_MASK;
  1941. vpu_clk->en_shift = CLK_EN_SHIFT;
  1942. /* rstgen define */
  1943. vpu_clk->rst_ctrl = vpu_clk->clkgen + RSTGEN_SOFTWARE_RESET_ASSERT1;
  1944. vpu_clk->rst_status = vpu_clk->clkgen + RSTGEN_SOFTWARE_RESET_STATUS1;
  1945. vpu_clk->axi_clk.rst_mask = RSTN_AXI_MASK;
  1946. vpu_clk->bpu_clk.rst_mask = RSTN_BPU_MASK;
  1947. vpu_clk->vce_clk.rst_mask = RSTN_VCE_MASK;
  1948. vpu_clk->apb_clk.rst_mask = RSTN_APB_MASK;
  1949. vpu_clk->aximem_128b.rst_mask = RSTN_128B_AXIMEM_MASK;
  1950. if (device_property_read_bool(&pdev->dev, "starfive,vdec_noc_ctrl"))
  1951. vpu_clk->noc_ctrl = true;
  1952. return 0;
  1953. }
  1954. static vpu_clk_t *vpu_clk_get(struct platform_device *pdev)
  1955. {
  1956. vpu_clk_t *vpu_clk;
  1957. vpu_clk = devm_kzalloc(&pdev->dev, sizeof(*vpu_clk), GFP_KERNEL);
  1958. if (!vpu_clk)
  1959. return NULL;
  1960. if (vpu_of_clk_get(pdev, vpu_clk))
  1961. goto err_get_clk;
  1962. return vpu_clk;
  1963. err_get_clk:
  1964. devm_kfree(&pdev->dev, vpu_clk);
  1965. return NULL;
  1966. }
  1967. static void vpu_clk_put(vpu_clk_t *clk)
  1968. {
  1969. if (clk->clkgen) {
  1970. iounmap(clk->clkgen);
  1971. clk->clkgen = NULL;
  1972. }
  1973. }
  1974. static int vpu_clk_enable(vpu_clk_t *clk)
  1975. {
  1976. if (clk == NULL || IS_ERR(clk))
  1977. return -1;
  1978. vpu_pmu_enable(clk->dev);
  1979. vpu_clk_control(clk, true);
  1980. if (clk->noc_ctrl == true)
  1981. vpu_noc_vdec_bus_control(clk, true);
  1982. DPRINTK("[VPUDRV] vpu_clk_enable\n");
  1983. return 0;
  1984. }
  1985. static void vpu_clk_disable(vpu_clk_t *clk)
  1986. {
  1987. if (clk == NULL || IS_ERR(clk))
  1988. return;
  1989. vpu_clk_control(clk, false);
  1990. vpu_pmu_disable(clk->dev);
  1991. if (clk->noc_ctrl == true)
  1992. vpu_noc_vdec_bus_control(clk, false);
  1993. DPRINTK("[VPUDRV] vpu_clk_disable\n");
  1994. }
  1995. #else /*STARFIVE_VPU_SUPPORT_CLOCK_CONTROL*/
  1996. int vpu_hw_reset(void)
  1997. {
  1998. DPRINTK("[VPUDRV] reset vpu hardware. \n");
  1999. /* sram do not need reset */
  2000. return reset_control_reset(s_vpu_clk->resets);
  2001. }
  2002. static int vpu_of_clk_get(struct platform_device *pdev, vpu_clk_t *vpu_clk)
  2003. {
  2004. struct device *dev = &pdev->dev;
  2005. int ret;
  2006. vpu_clk->dev = dev;
  2007. vpu_clk->clks = vpu_clks;
  2008. vpu_clk->nr_clks = ARRAY_SIZE(vpu_clks);
  2009. vpu_clk->resets = devm_reset_control_array_get_shared(dev);
  2010. if (IS_ERR(vpu_clk->resets)) {
  2011. ret = PTR_ERR(vpu_clk->resets);
  2012. dev_err(dev, "faied to get vpu reset controls\n");
  2013. }
  2014. ret = devm_clk_bulk_get(dev, vpu_clk->nr_clks, vpu_clk->clks);
  2015. if (ret)
  2016. dev_err(dev, "faied to get vpu clk controls\n");
  2017. if (device_property_read_bool(dev, "starfive,vdec_noc_ctrl"))
  2018. vpu_clk->noc_ctrl = true;
  2019. return 0;
  2020. }
  2021. static vpu_clk_t *vpu_clk_get(struct platform_device *pdev)
  2022. {
  2023. vpu_clk_t *vpu_clk;
  2024. if (!pdev)
  2025. return NULL;
  2026. vpu_clk = devm_kzalloc(&pdev->dev, sizeof(*vpu_clk), GFP_KERNEL);
  2027. if (!vpu_clk)
  2028. return NULL;
  2029. if (vpu_of_clk_get(pdev, vpu_clk))
  2030. goto err_of_clk_get;
  2031. return vpu_clk;
  2032. err_of_clk_get:
  2033. devm_kfree(&pdev->dev, vpu_clk);
  2034. return NULL;
  2035. }
  2036. static void vpu_clk_put(vpu_clk_t *clk)
  2037. {
  2038. clk_bulk_put(clk->nr_clks, clk->clks);
  2039. }
  2040. static int vpu_clk_enable(vpu_clk_t *clk)
  2041. {
  2042. int ret;
  2043. ret = clk_bulk_prepare_enable(clk->nr_clks, clk->clks);
  2044. if (ret)
  2045. dev_err(clk->dev, "enable clk error.\n");
  2046. DPRINTK("[VPUDRV] vpu_clk_enable\n");
  2047. return ret;
  2048. }
  2049. static void vpu_clk_disable(vpu_clk_t *clk)
  2050. {
  2051. clk_bulk_disable_unprepare(clk->nr_clks, clk->clks);
  2052. }
  2053. #endif